CN117133800B - Insulated gate bipolar transistor and manufacturing method thereof - Google Patents
Insulated gate bipolar transistor and manufacturing method thereof Download PDFInfo
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- CN117133800B CN117133800B CN202311387395.0A CN202311387395A CN117133800B CN 117133800 B CN117133800 B CN 117133800B CN 202311387395 A CN202311387395 A CN 202311387395A CN 117133800 B CN117133800 B CN 117133800B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 156
- 229920005591 polysilicon Polymers 0.000 claims abstract description 154
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 230000007704 transition Effects 0.000 claims abstract description 40
- 230000001413 cellular effect Effects 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 description 34
- 239000002184 metal Substances 0.000 description 34
- 239000012535 impurity Substances 0.000 description 25
- 238000000034 method Methods 0.000 description 20
- 230000008569 process Effects 0.000 description 15
- 239000004065 semiconductor Substances 0.000 description 14
- 239000000463 material Substances 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 8
- -1 phosphorus (P) Chemical class 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229910015900 BF3 Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000004146 energy storage Methods 0.000 description 1
- OJCDKHXKHLJDOT-UHFFFAOYSA-N fluoro hypofluorite;silicon Chemical compound [Si].FOF OJCDKHXKHLJDOT-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000003137 locomotive effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides an insulated gate bipolar transistor and a manufacturing method thereof, wherein the device comprises: the substrate comprises a terminal area and a source area, wherein the source area comprises a cell area and a grid area, and the grid area is arranged around the cell area; source region polysilicon which spans the cell region and the gate region and comprises source region short polysilicon and source region long polysilicon; the terminal transition region is arranged in the substrate of the gate region and partially extends into the substrate of the cell region; the gate region contact hole is arranged on the source region polysilicon on the gate region; and the source region contact hole is arranged on the cellular region, the depth of the source region contact hole arranged on one side of the source region polysilicon is a first depth, the depth of the source region contact hole arranged at the end part of the source region polysilicon is a second depth, and the second depth is larger than the first depth. By the insulated gate bipolar transistor and the manufacturing method thereof, the short-circuit tolerance of the insulated gate bipolar transistor can be improved, and the device performance can be improved.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to an insulated gate bipolar transistor and a manufacturing method thereof.
Background
Insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) is an important power semiconductor device, and is currently widely used in various fields of medium-high voltage power electronic systems, such as household appliances, uninterruptible power supplies, photovoltaic energy storage, industrial motor drives, electric vehicles, hybrid electric vehicles, and locomotive trains. Field Stop-Insulated Gate Bipolar Transistor (FS-IGBT) has smaller saturation voltage drop V ce(sat) And stronger heat dissipation capability, but the traditional FS-IGBT cannot resist short-circuit current due to design limitation, so that potential risks are brought to the reliability of the device.
Disclosure of Invention
The invention provides an insulated gate bipolar transistor and a manufacturing method thereof, and the insulated gate bipolar transistor and the manufacturing method thereof provided by the invention improve the short-circuit resistance of a semiconductor device, can improve the reliability of the insulated gate bipolar transistor and improve the performance of the device.
In order to solve the technical problems, the invention is realized by the following technical scheme.
The invention proposes an insulated gate bipolar transistor, comprising at least:
the substrate comprises a terminal area and a source area, wherein the source area comprises a cell area and a gate area, and the gate area is arranged at the periphery of the cell area;
the source region polysilicon spans the cell region and the gate region, and comprises source region short polysilicon and source region long polysilicon;
a terminal transition region disposed within the substrate of the gate region and extending partially into the substrate of the cell region;
a gate contact hole arranged on the source region polysilicon on the gate; and
the source region contact hole is arranged on the cell region, the depth of the source region contact hole arranged on one side of the source region polysilicon is a first depth, the depth of the source region contact hole arranged at the end part is a second depth, and the second depth is larger than the first depth.
In an embodiment of the present invention, the shape of the cellular region is concave, and one end of the gate region extends into the cellular region.
In an embodiment of the present invention, the source long polysilicon close to the source short polysilicon is a source first main polysilicon, the source first main polysilicon is a polysilicon segment arranged at opposite intervals, and the source long polysilicon far away from the source short polysilicon is a source last main polysilicon.
In an embodiment of the present invention, the gate contact hole at least includes a gate first contact hole and a gate second contact hole, where the gate first contact hole is disposed at an end portion of the source polysilicon overlapping the gate, and the gate second contact hole is disposed at a position where a center of the source long polysilicon overlaps the source.
In an embodiment of the present invention, the source contact hole includes a source first contact hole, the source first contact hole is disposed between adjacent source short polysilicon and source long polysilicon, and the source first contact hole has a first depth.
In an embodiment of the present invention, the source contact hole includes a source second contact hole, the source second contact hole is disposed between adjacent source long polysilicon, and the source second contact hole has a first depth.
In an embodiment of the present invention, the source contact hole includes a source third contact hole, where the source third contact hole is disposed at an end of the source short polysilicon away from the gate first contact hole, and the source third contact hole has a second depth.
In an embodiment of the present invention, the source region contact hole includes a source region fourth contact hole, the source region fourth contact hole is disposed at an end of the source region first main polysilicon away from the gate region first contact hole, and the source region fourth contact hole has a second depth.
In an embodiment of the present invention, the source contact hole includes a source fifth contact hole, the source fifth contact hole is disposed at an end of the source end, which is far away from the source short polysilicon, of the main polysilicon, and the source fifth contact hole has a first depth.
In an embodiment of the present invention, the terminal transition region completely covers the third contact hole of the source region, the fourth contact hole of the source region, the fifth contact hole of the source region, the first contact hole of the gate region and the second contact hole of the gate region, and partially covers the first contact hole of the source region and the second contact hole of the source region.
The invention also provides a manufacturing method of the insulated gate bipolar transistor, which at least comprises the following steps:
providing a substrate, forming a terminal area and a source area on the substrate, forming a cell area and a gate area in the source area, and arranging the gate area around the cell area;
forming source region polysilicon on the cell region, wherein the source region polysilicon comprises source region short polysilicon and source region long polysilicon;
forming a terminal transition region in the substrate of the gate region, and extending part of the terminal transition region into the substrate of the cell region;
forming a gate contact hole in the source region polysilicon on the gate region; and
and forming a source region contact hole on the cellular region, wherein the depth of the source region contact hole arranged on one side of the source region polysilicon is a first depth, the depth of the source region contact hole arranged at the end part is a second depth, and the second depth is larger than the first depth.
In summary, the present invention provides an insulated gate bipolar transistor and a method for manufacturing the same, which can enhance the short-circuit tolerance of the insulated gate bipolar transistor and avoid the occurrence of avalanche breakdown of a semiconductor device. By adding the arrangement of the source region contact hole in the terminal transition region in the center of the source region, the short-circuit resistance near the center of the insulated gate bipolar transistor is enhanced, and by adding the arrangement of the source region contact hole in the terminal transition region near the gate region, the short-circuit resistance near the gate region of the insulated gate bipolar transistor is enhanced, the reliability of the device is greatly improved, and the performance of the insulated gate bipolar transistor is improved. The manufacturing process of the insulated gate bipolar transistor is compatible with the existing manufacturing process, and is beneficial to the mass production of the power of the semiconductor device.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic plan view of an igbt according to an embodiment of the invention.
Fig. 2 is a schematic plan view of source metal and gate metal in an embodiment of the invention.
Fig. 3 is a schematic plan view of gate contact holes, source contact holes and source polysilicon according to an embodiment of the present invention.
FIG. 4 is a schematic plan view illustrating a terminal region, a source region, a cell region, a gate region and a terminal transition region according to an embodiment of the present invention.
Fig. 5 is a cross-sectional view of the insulated gate bipolar transistor of fig. 1 taken along A1-A1.
Fig. 6 is a cross-sectional view of the insulated gate bipolar transistor of fig. 1 taken along A2-A2.
Fig. 7 is a cross-sectional view of the insulated gate bipolar transistor of fig. 1 along the direction B-B.
Description of the reference numerals:
10. a substrate; 11. a termination region; 12. a source region; 121. source region metal; 13. a cell region; 14. a gate region; 1401. a central gate region connection region; 1402. a gate region bonding region; 1403. an edge gate region connection region; 141. the gate region is connected with metal; 142. a bonding region metal; 143. a gate oxide layer; 144. a dielectric layer; 15. source region polysilicon; 151. short polysilicon of source region; 152. source region long polysilicon; 153. a source region first main polysilicon; 154. main polysilicon at the end of the source region; 16. a terminal transition zone; 161. a P-type well region; 162. an n+ source region; 1501. a source region first contact hole; 1502. a source region second contact hole; 1503. a source region third contact hole; 1504. a source region fourth contact hole; 1505. a source region fifth contact hole; 1404. a gate region first contact hole; 1405. a gate region second contact hole; 17. an N-drift layer; 21. a field stop layer; 22. a collector region; 23. and a back metal layer.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In the present invention, it should be noted that, as terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience of description and simplification of the description, and does not indicate or imply that the indicated apparatus or element must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.
Referring to fig. 1 to 4, the present application provides a schematic plan layout of an insulated gate bipolar transistor, which includes a substrate 10, and a terminal region 11 and a source region 12 disposed on the substrate 10, wherein the terminal region 11 is disposed around the source region 12, and the source region 12 is provided with a cell region 13, a gate region 14, a terminal transition region 16, a gate contact hole, a source contact hole, and other structures. Through setting up the distribution of cell district 13, gate district 14, terminal transition district 16, gate district contact hole and source district contact hole on source district 12, set up multiple source district contact hole on source district 12, and terminal transition district 16 cooperates source district contact hole setting for example, when insulated gate bipolar transistor terminal avalanche current and source district avalanche current carry out the bleeder, improve the anti short circuit performance of device, the device is wider from the central and all around omnidirectional collection avalanche current's of chip scope, the collection ability is stronger, and be difficult for taking place avalanche breakdown, thereby the short circuit tolerance of insulated gate bipolar transistor has been greatly strengthened. The source region 12 is distributed in different insulated gate bipolar transistors, such as forming a planar FS-IGBT, a trench FS-IGBT, or a high voltage Vertical Double-diffused MOSFET (VDMOS), to improve the performance of the power device. In the present embodiment, for example, the source region structure forming the planar FS-IGBT is explained.
Referring to fig. 1 to 4, in an embodiment of the present invention, the source region 12 includes a gate region 14 and a cell region 13, and the gate region 14 is disposed around the cell region 13 and extends into the cell region 13. The gate region 14 extends into the cell region 13 at one end in the central length direction of the source region 12, and is not connected with the gate region 14 at the other end, for example, a preset distance is arranged between the gate region 14 extending into the source region 12 and the gate region 14 at one end in the extending direction, for example, and then, for example, the main polysilicon 154 at the end of the source region is arranged, that is, the cell region 13 is arranged in a concave shape, for example, and the opening of the concave shape faces the length direction, for example. The gate regions 14 and the cell regions 13, and other structures on the source region 12 are arranged symmetrically along a central axis of the length direction of the source region 12, wherein, as shown in fig. 1, the central length direction of the source region 12 is, for example, the X direction, the width direction of the source region 12 is, for example, the Y direction, and the width direction of the source region 12 is, for example, a direction perpendicular to the length direction of the source region 12. In this embodiment, the gate regions 14 located around the cell region 13 are named as edge gate region connection regions 1403, and the gate regions 14 extending into the cell region 13 are named as central gate region connection regions 1401. The gate region 14 extending into the cell region 13 includes, for example, a gate region bonding region 1402, and the gate region bonding region 1402 connects the edge gate region connection region 1403 and the central gate region connection region 1401, for example, away from the gate region 14 in the direction extending into the cell region 13. The gate 14 is provided with a gate connection metal 141 and a bonding pad metal 142, for example, the gate connection metal 141 is provided on the edge gate connection region 1403 and the center gate connection region 1401, and the bonding pad metal 142 is provided on the gate bonding pad 1402, for example.
Referring to fig. 1 to 4, in an embodiment of the present invention, an active region polysilicon 15 is disposed on a source region 12, the active region polysilicon 15 is disposed on a gate region 14 and a cell region 13, the active region polysilicon 15 includes a source region short polysilicon 151 and a source region long polysilicon 152, for example, and the source region short polysilicon 151 and the source region long polysilicon 152 are disposed on the source region 12 in equal distance in sequence along a length direction of the source region 12, for example. The source region polysilicon 15 does not exceed the extent of the cell region 13 in the length direction of the source region 12, for example, and a portion of the source region polysilicon 15 spans the gate region 14 and the cell region 13 in the width direction of the source region 12, for example. In this embodiment, the source short polysilicon 151 is disposed on both sides of the gate bonding area 1402, and a first distance is provided between the source short polysilicon 151 and the gate bonding area 1402, so that the source connection hole is disposed on the source 12 at the first distance later, and part of the source long polysilicon 152 spans the edge gate connection area 1403, the cell area 13 and the central gate connection area 1401, for example. In this embodiment, the number of the source short polysilicon 151 is, for example, four, and the four source short polysilicon 151 have the same size and are, for example, symmetrically disposed on both sides of the gate bonding region 1402. The number of source long polysilicon 152 is, for example, seven, the source long polysilicon 152 disposed close to the source short polysilicon 151 is, for example, the source first main polysilicon 153, and the source long polysilicon 152 disposed far from the source short polysilicon 151 is, for example, the source last main polysilicon 154. The source region first main polysilicon 153 is, for example, a polysilicon segment disposed at opposite intervals, and is disposed at two sides of the central gate region connecting region 1401, and a second distance is disposed between the source region first main polysilicon 153 and the central gate region connecting region 1401, for example, for setting source region connecting holes on the source region 12 at the second distance. The source long polysilicon 152 except for the source first main polysilicon 153 is, for example, the same size, and the source long polysilicon 152 except for the source first main polysilicon 153 and the source last main polysilicon 154 is, for example, disposed on both sides of the central gate connection region 1401 across the edge gate connection region 1403, the cell region 13, and the central terminal transition region 16. In other embodiments, the source short polysilicon 151 and the source long polysilicon 152 are, for example, other sub-structures that facilitate subsequent contact hole placement to improve the performance of the power device.
Referring to fig. 1 to 4, in an embodiment of the present invention, a terminal transition region 16 is disposed in the substrate 10, for example, under the gate region 14, the terminal transition region 16 under the edge gate region connection region 1403 extends toward the cell region 13, and the terminal transition regions 16 under the central gate region connection region 1401 and the gate region bonding region 1402 extend toward the cell region 13, for example, along the X-direction and the Y-direction of the source region 12, respectively, and are connected to the terminal transition regions 16 under the edge gate region connection region 1403 on both sides of the X-direction of the source region 12. And the terminal transition region 16 extends into a portion of the cell region 13, for example, over a larger range than the gate connection metal 141 and the bonding pad metal 142.
Referring to fig. 1, in an embodiment of the present invention, a gate contact hole is disposed on the source polysilicon 15, and the gate contact hole includes, for example, a gate first contact hole 1404 and a gate second contact hole 1405. The gate first contact hole 1404 is disposed, for example, on two ends of the source polysilicon 15 near the gate connection metal 141. And is disposed, for example, on the source region polysilicon 15 on both side edge gate region connection regions 1403 in the width direction of the source region 12. The gate second contact hole 1405 is provided on the source long polysilicon 152 excluding the source first main polysilicon 153 and the source last main polysilicon 154, for example, and is provided on the source long polysilicon 152 on the gate pad 1402, for example, to connect the gate connection metal 141 and the pad metal 142.
Referring to fig. 1 to 4, in an embodiment of the present invention, a source contact hole is disposed on a cellular region 13, and the source contact hole includes, for example, a source first contact hole 1501 and a source second contact hole 1502. The source first contact hole 1501 is disposed, for example, on the cell region 13 on the side of the source short polysilicon 151 close to the source long polysilicon 152, the source second contact hole 1502 is disposed, for example, on the cell region 13 on the side of the source long polysilicon 152 away from the source short polysilicon 151 except for the source end main polysilicon 154, and the source first contact hole 1501 and the source second contact hole 1502 are disposed, for example, symmetrically on both sides of the central gate connection region 1401 and the gate bonding region 1402. In this embodiment, the length of the source first contact hole 1501 is smaller than the length of the source short polysilicon 151, for example, and the width of the source first contact hole 1501 is smaller than the distance between adjacent source polysilicon 15, for example. The length of the source region second contact hole 1502 is, for example, less than half the length of the source region last main polysilicon 154, and the width of the source region second contact hole 1502 is, for example, less than the distance between adjacent source region polysilicon 15. In this embodiment, the first source contact hole 1501 and the second source contact hole 1502 have a first depth, i.e., the first source contact hole 1501 and the second source contact hole 1502 have the same depth, for example, to match the device avalanche current discharge requirements at the source short polysilicon 151 and the source long polysilicon 152, respectively.
Referring to fig. 1 to fig. 4, in an embodiment of the present invention, the source contact hole further includes, for example, a source third contact hole 1503, a source fourth contact hole 1504 and a source fifth contact hole 1505, where the source third contact hole 1503 is disposed on the substrate 10 on both sides of the source short polysilicon 151 near the gate bonding region 1402, specifically, in the present embodiment, the source third contact hole 1503 is disposed on the cell region 13 between the source short polysilicon 151 and the gate bonding region 1402, and the length of the source third contact hole 1503 is, for example, greater than the distance between the two source short polysilicon 151, and, for example, equal to the sum of the widths of the two source short polysilicon 151, and the width of the third contact hole is, for example, less than the first distance. The source fourth contact hole 1504 is, for example, disposed on the cell region 13 between the source first main polysilicon 153 and the central gate connection region 1401, and the length of the source fourth contact hole 1504 is, for example, less than or equal to the width of the source short polysilicon 151, and the width of the source fourth contact hole 1504 is, for example, less than the second distance. The source fifth contact hole 1505 is, for example, disposed on the cell region 13 on the side of the source last main polysilicon 154 near the gate region 14, and the source fifth contact hole 1505 is, for example, symmetrically disposed on the side of the source last main polysilicon 154. The width of the source fifth contact hole 1505 is, for example, the same as the width of the source fourth contact hole 1504, and the length of the source fifth contact hole 1505 is, for example, greater than twice the length of the source fifth contact hole 1505 and less than the length of the source last main polysilicon 154. In this embodiment, the third contact hole 1503 and the fourth contact hole 1504 have a second depth, for example, and the fifth contact hole 1505 has a first depth, for example, which is greater than the first depth, i.e. source contact holes with different depths are provided on the cell region 13, so that the path of the avalanche current leaking to the metal in the deep contact holes is shorter, and the anti-short-circuit capability of different regions of the igbt is enhanced, thereby improving the short-circuit tolerance of the igbt.
Referring to fig. 1 to 5, the present invention also provides a method for fabricating an insulated gate bipolar transistor, which comprises providing a substrate 10, wherein the substrate 10 is selected from silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (sige), for example(GeSi), sapphire, silicon wafer, or other III/V compound, and also includes a stacked structure of these semiconductor materials, or silicon on insulator, stacked silicon on insulator, silicon germanium on insulator, and the like. In the present embodiment, the substrate 10 is an N-type doped substrate, the doping concentration of the substrate 10 is set according to the production condition, and the doping concentration of the N-type impurity is 5×10 11 atmos/cm 2 ~5×10 12 atmos/cm 2 . In this embodiment, the N-type doped substrate 10 further includes an N-drift layer 17, and the N-drift layer 17 and a field stop layer 21 obtained later form, for example, a voltage-resistant layer, so as to optimize the field distribution in the semiconductor device. In other embodiments, the substrate 10 is selected and arranged according to the insulated gate bipolar transistor being fabricated.
Referring to fig. 1-6, in one embodiment of the present invention, a field oxide layer (not shown), such as silicon oxide (SiO), is formed on a substrate 10 2 ) The field oxide layer is formed by wet oxidation, for example, the oxidation temperature is 1000 ℃ to 1150 ℃, and the thickness of the formed field oxide layer is 1000nm to 2500nm, for example. After forming the field oxide layer, a photo-lithography process of the termination region 11 and the termination transition region 16 is performed on the field oxide layer, and the photoresist layer exposes the field oxide layer on the termination region 11 and, for example, a wet etching process is selected, and, for example, a buffer oxide etching process (Buffered Oxide Etch, BOE) is selected to remove the exposed field oxide layer. In this embodiment, P-type impurities are implanted into the termination region 11 and the termination transition region 16 using the field oxide layer as a mask, and the termination region 11 and the termination transition region 16 are formed by ion implantation and ion diffusion. Specifically, the terminal diffusion temperature is 1100 ℃ to 1250 ℃, the diffusion time is 120min to 500min, and a small amount of oxygen is introduced after the diffusion setting time to control the ion diffusion depth, and the finally formed terminal region 11 is located around the source region 12.
Referring to fig. 1 to 6, in an embodiment of the invention, after forming the termination region 11, a photoresist layer (not shown) formed by forming the termination region 11 is removed. Then, a photolithography process is performed on the source region 12, and the photoresist layer exposes the field oxide layer on the source region 12, and a BOE etching process is selected to etch away the exposed field oxide layer on the source region 12, thereby opening the window of the source region 12. And after opening the window of the source region 12, the photoresist layer formed is removed.
Referring to fig. 1 to 7, in an embodiment of the present invention, after the window of the source region 12 is opened, a gate oxide layer 143 is formed on the source region 12. In the present embodiment, the gate oxide layer 143 is, for example, silicon oxide, and is formed by, for example, thermal oxidation, in-situ vapor growth, chemical vapor deposition, or the like, and the gate oxide layer 143 is grown by, for example, thermal oxidation. The gate oxide layer 143 may be grown by a dry-oxygen process or a wet-oxygen oxidation process, or by a dry-wet-dry (dry-wet-dry-oxygen) process. In this embodiment, for example, a dry-wet process is adopted, in the formation process, the reaction temperature is, for example, 1000 ℃ to 1150 ℃, and, for example, 1050 ℃, oxygen mixed with a small amount of hydrogen is introduced, the mixture of the hydrogen and the oxygen forms substances such as water vapor, OH radicals, O radicals and the like on the surface of the substrate 10, and oxidation reaction is performed with the exposed silicon to form the gate oxide layer 143. The ratio of hydrogen to oxygen and the gas flow rate are controlled, and the thickness of the gate oxide layer 143 is not limited in the present invention, and can be selected according to the requirements of the manufactured insulated gate bipolar transistor, and the present invention is not particularly limited.
Referring to fig. 1 to 7, in one embodiment of the present invention, after the gate oxide layer 143 is formed, a gate material layer is deposited on the cellular region 13 to form the source polysilicon 15. And the gate material layer is, for example, a polysilicon material or the like. In this embodiment, the gate material layer is an N-type doped polysilicon material, and the doped ions are N-type ions such As phosphorus (P), arsenic (As), or tin (Sn). The gate material layer is manufactured, for example, by a low-pressure chemical vapor deposition method, and then an etching process is used to form source region polysilicon 15, and source region polysilicon 15 includes, for example, source region short polysilicon 151 and source region long polysilicon 152, source region long polysilicon 152 close to source region short polysilicon 151 is source region first main polysilicon 153, and source region long polysilicon 152 far from source region short polysilicon 151 is source region last main polysilicon 154. And etching to remove part of the source region polysilicon 15 for subsequent contact hole manufacture while forming the gate structure and the source region polysilicon 15 by etching. In this embodiment, the gate material layer between adjacent source region polysilicon 15 is etched away, for example, to leave the locations where the source region first contact holes 1501 and the source region second contact holes 1502 are subsequently formed. The portion of the source region short polysilicon 151 near the gate region 14 is etched away to remain as a location for the subsequent formation of the source region third contact hole 1503. The portion of the source region first main polysilicon 153 adjacent to the gate structure is etched away to leave a location for subsequently forming a source region fourth contact hole 1504. I.e., the locations of the source region third contact hole 1503 and the source region fourth contact hole 1504 are not covered with photoresist after photolithography at the time of gate material layer photolithography.
Referring to fig. 1 to 7, in an embodiment of the present invention, after forming the source region polysilicon 15, P-type impurities such as boron (B) or boron fluoride ions are implanted into the entire substrate 10, and a P-type well region 161 is formed in the substrate 10. In this embodiment, the impurity ions in the P-type well region 161 are, for example, boron ions. The P-type well region 161 extends from the surface of the substrate 10 into the substrate 10, and the depth of the P-type well region 161 is less than the depth of the termination transition region 16. Wherein the implantation concentration of the impurity in the P-type well region 161 is, for example, 5×10 13 atoms/cm 2 ~2×10 14 atoms/cm 2 The implantation energy of the P-type impurity is, for example, 70KeV to 180KeV. After the formation of the implanted P-type impurity, the substrate 10 is subjected to an annealing process to activate and diffuse the P-type impurity, so that the P-type impurity is diffused to a proper depth to form the P-type well region 161. In this embodiment, the diffusion temperature is 1100 ℃ to 1250 ℃ for example, and the diffusion time is 60min to 150min for example.
Referring to fig. 1 to 7, in an embodiment of the present invention, after forming a P-type well region 161, an N-type impurity such As arsenic (As) or tin (Sn) is implanted into the P-type well region 161 of the source region 12 to form an n+ source region 162. In this embodiment, the impurity ions in the n+ source region 162 are, for example, arsenic ions. The n+ source region 162 extends from the surface of the substrate 10 into the substrate 10, and the n+ source region 162 has a depth smaller than that of the P-type well region 161. The impurity implantation concentration of the n+ source region 162 is, for example, 1×10 15 atoms/cm 2 ~1×10 16 atoms/cm 2 The implantation energy of the N-type impurity is, for example, 100KeV to 150KeV. After the formation of the implanted N-type impurity, the substrate 10 is subjected to an annealing process to activate and diffuse the N-type impurity, so that the N-type impurity is diffused to a proper depth to form the n+ source region 162. In this embodiment, the diffusion temperature is 950 ℃ to 1150 ℃ for example, and the diffusion time is 30min to 150min for example.
Referring to fig. 1 to 7, the terminal transition region 16 has no doped region of N-type ions, so that no parasitic NPN transistor is formed, and the avalanche current does not cause turn-on of the parasitic transistor, thereby increasing the short-circuit resistance near the terminal transition region 16 of the semiconductor device. In the present embodiment, the impurity ions in the terminal transition region 16 are, for example, boron ions. A termination transition region 16 extends from the surface of the substrate 10 into the substrate 10, the termination transition region 16 being disposed, for example, within the substrate 10 below the gate oxide layer 143, and the termination transition region 16 having a depth greater than the depth of the P-type well region 161.
Referring to fig. 1 to 7, in an embodiment of the present invention, a dielectric layer 144 is formed on the substrate 10, the gate oxide layer 143 and the source polysilicon 15, wherein the dielectric layer 144 is a Low-K material such as silicon oxide, silicon fluoride (SiF), silicon oxycarbide (SiOC) or silicon oxyfluoride (SiOF), and the thickness of the dielectric layer 144 is selected according to the manufacturing requirements, for example, by chemical vapor deposition or Low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD).
Referring to fig. 1 to 7, in an embodiment of the present invention, after forming the dielectric layer 144, the photoresist exposes the contact hole, and the dielectric layer 144, a portion of the substrate 10 and a portion of polysilicon are etched to form a source contact hole and a gate contact hole, respectively. The source contact holes include a source first contact hole 1501, a source second contact hole 1502, a source third contact hole 1503, a source fourth contact hole 1504, and a source fifth contact hole 1505, and the gate contact holes include a gate first contact hole 1404 and a gate second contact hole 1405. In this embodiment, for example, one of wet etching, dry etching or an etching method combining wet etching and dry etching is selected, and for example, wet etching is also selected, and the widths of the source region third contact hole 1503 and the source region fourth contact hole 1504 are larger than the widths of the remaining contact holes, so that after wet etching, the depths of the source region third contact hole 1503 and the source region fourth contact hole 1504 are larger than the depths of the other contact holes, so as to improve the capability of discharging avalanche current of the insulated gate bipolar transistor. The depths of the gate first contact hole 1404 and the gate second contact hole 1405 extend, for example, into the dielectric layer 144 to the surface of the source polysilicon 15 or into the inner portion of the polysilicon. The source first contact holes 1501 extend, for example, into the n+ source regions 162 up to the depth of the P-type well regions 161, no more than the depth of the P-type well regions 161, and a portion of the source first contact holes 1501 extend, for example, into the termination transition region 16. The source second contact hole 1502, the source third contact hole 1503, the source fourth contact hole 1504, and the source fifth contact hole 1505 penetrate, for example, into the terminal transition region 16, and the depths of the source third contact hole 1503 and the source fourth contact hole 1504 are, for example, greater than the depths of the source first contact hole 1501, the source second contact hole 1502, and the source fifth contact hole 1505.
Referring to fig. 1 to 7, in an embodiment of the present invention, when the avalanche current of the termination transition region 16 near the center of the semiconductor device and the avalanche current of the source region 12 bleed through the source region fourth contact hole 1504 and the source region second contact hole 1502 in the termination transition region 16 near the center of the source region 12, the termination avalanche current at the end of the source region main polysilicon 154 and the avalanche current of the nearby source region 12 bleed through the source region fifth contact hole 1505 in the termination transition region 16, and the termination avalanche current near the gate bonding region 1402 and the avalanche current of the nearby source region 12 bleed through the source region third contact hole 1503 and the source region first contact hole 1501 in the termination transition region 16 near the gate region 14, since there is no n+ source region 162 in the termination transition region 16, there is no parasitic NPN transistor, and the avalanche current does not cause turn-on of the parasitic NPN transistor. Meanwhile, the depth of the source region fourth contact hole 1504 is larger than that of the source region second contact hole 1502, the depth of the source region third contact hole 1503 is larger than that of the source region first contact hole 1501, and the path of avalanche current entering the P-well region from the N-drift layer 17 flowing from the source region third contact hole 1503 and the source region fourth contact hole 1504 to the source region metal 121 is shorter, so that the avalanche current is easier to discharge through the deep source region third contact hole 1503 and the source region fourth contact hole 1504, the semiconductor power device is prevented from being burnt due to avalanche current in the center or the edge of the device, the short-circuit resistance near the gate region 14 of the semiconductor power device is greatly enhanced, and the short-circuit resistance of the semiconductor power device is improved.
Referring to fig. 1 to 7, in an embodiment of the present invention, after forming the dielectric layer 144 and the contact hole, a metal layer, such as a metal aluminum silicon layer, is formed on the dielectric layer 144, and further such as a metal aluminum silicon copper layer. And the metal layer is deposited, for example, by physical vapor deposition or the like, with a thickness of, for example, 4 μm to 5 μm, and, for example, 4 μm or the like. After the metal layer is formed, a patterned photoresist layer (not shown) is formed on the metal layer. The metal layer is etched to form source region metal 121, gate region connection metal 141 and bonding region metal 142.
Referring to fig. 1 and 5, in one embodiment of the present invention, after forming a metal layer, a passivation layer (not shown) such as silicon oxide (SiO) is formed on the metal layer 2 ) Layer or silicon oxide and silicon nitride (Si 3 N 4 ) And the like. In this embodiment, the passivation layer is a stack of silicon oxide and silicon nitride, and is formed, for example, by thermal oxidation or chemical vapor deposition, and the thickness of the passivation layer formed is, for example, 800nm to 1500nm, so as to satisfy the requirement of effectively protecting the device structure after the subsequent electrode structure is formed, and ensure the stability of the device.
Referring to fig. 1 and 5, in an embodiment of the present invention, after the passivation layer, the substrate 10 is thinned relative to the side where the passivation layer is disposed, and the side of the substrate 10 relative to the side where the metal layer is disposed is defined as the back side of the substrate 10, where the thinned thickness is, for example, a thickness reaching a voltage withstanding value of the device. After the thinning, an N-type impurity such As arsenic (As) or tin (Sn) is implanted into a thinned surface of the substrate 10 to form a field stop layer 21, and the field stop layer 21 extends from the back surface of the substrate 10 into the substrate 10. After the formation of the implanted N-type impurity, the substrate 10 is subjected to an annealing process to activate and diffuse the N-type impurity, so that the N-type impurity is diffused to a proper depth to form the field stop layer 21. And the field stop layer 21 and the N-drift layer 17 form a withstand voltage layer of the device.
Referring to fig. 1 and 5, in one embodiment of the present invention, after forming the field stop layer 21, P-type impurities such as boron (B) or boron fluoride ions are implanted into the back surface of the entire substrate 10, and a collector region 22 is formed in the substrate 10. The collector region 22 extends from the back surface of the substrate 10 toward the field stop layer 21, and the depth of the collector region 22 is, for example, less than the depth of the field stop layer 21. After the formation of the implanted P-type impurity, the substrate 10 is subjected to an annealing process to activate and diffuse the P-type impurity, so that the P-type impurity is diffused to a proper depth to form the collector region 22. When the device is turned on, minority carriers are injected into the voltage-resistant layer in the collector region 22, so that conductivity modulation can be generated, and the current capacity of the device is increased.
Referring to fig. 1 and 5, in one embodiment of the present invention, after forming the collector region 22, a back metal layer 23 is formed on the collector region 22. The back metal layer 23 is, for example, a composite metal layer of a layer of metallic aluminum, titanium, nickel, silver, or the like, and the back metal layer 23 is deposited by, for example, physical vapor deposition or the like, and the thickness thereof is, for example, 1 μm to 3 μm.
In summary, the present invention provides an insulated gate bipolar transistor and a method for manufacturing the same, in which the range of a terminal transition region is controlled to extend into a cell region, and a contact hole is added to the cell region of a source region short polysilicon and a source region long polysilicon, and the depth of the added contact hole is greater than that of the original contact hole, so that avalanche current is more easily discharged through the added contact hole, the short-circuit resistance of the insulated gate bipolar transistor near the center and near the gate region is enhanced, the short-circuit resistance of the insulated gate bipolar transistor is enhanced, and avalanche breakdown of a semiconductor device is avoided. The reliability of the device is greatly improved, and the performance of the insulated gate bipolar transistor is improved. The manufacturing process of the insulated gate bipolar transistor is compatible with the existing manufacturing process, and is beneficial to the mass production of the power of the semiconductor device.
Reference throughout this specification to "one embodiment," "an embodiment," or "a particular embodiment (a specific embodiment)" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment, and not necessarily in all embodiments, of the invention. Thus, the appearances of the phrases "in one embodiment (in one embodiment)", "in an embodiment (in an embodiment)", or "in a specific embodiment (in a specific embodiment)" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics of any specific embodiment of the present invention may be combined in any suitable manner with one or more other embodiments. It will be appreciated that other variations and modifications of the embodiments of the invention described and illustrated herein are possible in light of the teachings herein and are to be considered as part of the spirit and scope of the invention.
The foregoing description is only illustrative of the preferred embodiments of the present application and the technical principles employed, and it should be understood by those skilled in the art that the scope of the invention in question is not limited to the specific combination of features described above, but encompasses other technical solutions which may be formed by any combination of features described above or their equivalents without departing from the inventive concept, such as the features described above and the features disclosed in the present application (but not limited to) having similar functions being interchanged. Other technical features besides those described in the specification are known to those skilled in the art, and are not described herein in detail to highlight the innovative features of the present invention.
Claims (11)
1. An insulated gate bipolar transistor, comprising at least:
the substrate comprises a terminal area and a source area, wherein the source area comprises a cell area and a gate area, and the gate area is arranged at the periphery of the cell area;
the source region polysilicon spans the cell region and the gate region, and comprises source region short polysilicon and source region long polysilicon;
a terminal transition region disposed within the substrate of the gate region and extending partially into the substrate of the cell region;
a gate contact hole arranged on the source region polysilicon on the gate; and
the source region contact hole is arranged on the cell region, the depth of the source region contact hole arranged on one side of the source region polycrystalline silicon is a first depth, the depth of the source region contact hole arranged at the end part of the source region polycrystalline silicon is a second depth, and the second depth is larger than the first depth.
2. The insulated gate bipolar transistor of claim 1 wherein said cell region has a concave shape and one end of said gate region extends into said cell region.
3. The insulated gate bipolar transistor of claim 1 wherein the source long polysilicon adjacent to the source short polysilicon is a source first main polysilicon, the source first main polysilicon is a polysilicon segment disposed in a relatively spaced apart relationship, and the source long polysilicon remote from the source short polysilicon is a source last main polysilicon.
4. The insulated gate bipolar transistor of claim 3 wherein said gate contact hole comprises at least a gate first contact hole and a gate second contact hole, said gate first contact hole being disposed at an end of said source region polysilicon overlapping said gate, said gate second contact hole being disposed at a location of said source region long polysilicon center overlapping said gate.
5. The insulated gate bipolar transistor of claim 4 wherein the source contact hole comprises a source first contact hole, the source first contact hole is disposed adjacent the source short polysilicon and between the source short polysilicon and source long polysilicon, and the source first contact hole has a first depth.
6. The insulated gate bipolar transistor of claim 5 wherein the source contact hole comprises a source second contact hole, the source second contact hole being disposed between adjacent source long polysilicon and the source second contact hole having a first depth.
7. The insulated gate bipolar transistor of claim 6 wherein the source contact hole comprises a source third contact hole, the source third contact hole is disposed at an end of the source short polysilicon remote from the gate first contact hole, and the source third contact hole has a second depth.
8. The insulated gate bipolar transistor of claim 7 wherein the source contact hole comprises a source fourth contact hole, the source fourth contact hole is disposed at an end of the source first main polysilicon remote from the gate first contact hole, and the source fourth contact hole has a second depth.
9. The insulated gate bipolar transistor of claim 8 wherein the source contact hole comprises a source fifth contact hole, the source fifth contact hole is disposed at an end of the source last main polysilicon that is remote from the source short polysilicon, and the source fifth contact hole has a first depth.
10. The insulated gate bipolar transistor of claim 9 wherein the terminal transition region completely covers the source region third contact hole, the source region fourth contact hole, the source region fifth contact hole, the gate region first contact hole, and the gate region second contact hole, and partially covers the source region first contact hole and the source region second contact hole.
11. The manufacturing method of the insulated gate bipolar transistor is characterized by at least comprising the following steps:
providing a substrate, forming a terminal area and a source area on the substrate, forming a cell area and a gate area in the source area, and arranging the gate area around the cell area;
forming source region polysilicon on the cell region, wherein the source region polysilicon comprises source region short polysilicon and source region long polysilicon;
forming a terminal transition region in the substrate of the gate region, and extending part of the terminal transition region into the substrate of the cell region;
forming a gate contact hole in the source region polysilicon on the gate region; and
and forming a source region contact hole on the cellular region, wherein the depth of the source region contact hole arranged on one side of the source region polysilicon is a first depth, the depth of the source region contact hole arranged at the end part of the source region polysilicon is a second depth, and the second depth is larger than the first depth.
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