JP2014049694A - Igbt - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of the junction termination structure of an IGBT that although use of a multi-state field plate helps to shorten peripheral length than when a multiple floating field ring is used, it is generally necessary to raise the resistivity of a drift region to restrain a rise in electric field strength on substrate surface in order to obtain excellent withstand voltage characteristic by using the multistage field plate, and that for cases where a defect layer is introduced in a buffer region, etc. in an ordinary asymmetric IGBT, however, raising the resistivity of the drift region results in a depletion layer being excessively extended, which in turn may bring about a considerable increase in leakage current.SOLUTION: The present invention is an IGBT including a field stop region within a drift region parted from a buffer region adjacent to a collector region on the reverse side of a semiconductor chip, and having a crystal defect region between it and the buffer region, wherein the IGBT has a ring-shaped multistage field plate around a cell region on the surface of a semiconductor chip.

Description

  The present application relates to a technology effective when applied to a device structure of a power semiconductor device (or semiconductor integrated circuit device) such as an IGBT (Insulated Gate Bipolar Transistor) and a diode, and a junction termination technology.

  Japanese Unexamined Patent Publication No. 2001-77357 (Patent Document 1) relates to a punch through IGBT type (Integrated Gate Bipolar Transistor). There is disclosed a technique in which an N− layer having a low lifetime layer is provided between a P + collector layer and an N + buffer layer.

  Japanese Unexamined Patent Publication No. 2006-332127 (Patent Document 2) or US Pat. No. 7,518,197 (Patent Document 3) corresponding thereto relates to an IGBT. For example, a technique for providing a local lifetime control region in the middle of an N-drift region in a punch-through IGBT is disclosed.

  Japanese Unexamined Patent Publication No. 2011-238872 (Patent Document 4) relates to a punch-through IGBT. Similarly, there is disclosed a technique of providing a lifetime control region in the middle of the N-drift region.

  Japanese Patent Publication No. 2002-52085 (Patent Document 5) or US Pat. No. 6,441,408 (Patent Document 6) corresponding thereto relates to power semiconductor elements such as IGBTs and power diodes. For example, a technique of providing an N-type buffer layer thicker than usual on the collector side of the N-type drift region of the IGBT is disclosed.

  Japanese Unexamined Patent Publication No. 2005-217152 (Patent Document 7) or US Patent Publication No. 2005-167694 (Patent Document 8) corresponding thereto relates to a junction termination of an IGBT. There is disclosed a junction termination structure comprising a field plate, a guard ring (reverse field plate or channel stop electrode) provided around the IGBT chip, and an intermediate potential electrode therebetween.

  Japanese Laid-Open Patent Publication No. 58-77242 (Patent Document 9) or US Pat. No. 5,310,052 (Patent Document 10) corresponding thereto relates to a planar type semiconductor device. There is disclosed a junction termination structure composed of a multi-stage field plate and a guard ring (reverse field plate or channel stop electrode) provided around a planar semiconductor device chip.

JP 2001-77357 A JP 2006-332127 A U.S. Pat. No. 7,518,197 JP2011-238872A Japanese translation of PCT publication No. 2002-52085 U.S. Pat. No. 6,441,408 JP-A-2005-217152 US Patent Publication No. 2005-167694 JP 58-77242 A US Pat. No. 5,311,052

  When considering junction termination structures such as IGBTs and diodes, those using multistage FP (Field Plate) and those using multiple FFR (Floating Field Ring) (including those using multiple FP) It is considered that the former is considerably longer when the peripheral lengths of the former are compared. This is because the critical electric field strength in the insulating film is considerably higher than the critical electric field strength in the drift region or the like.

  Here, in order to obtain a good breakdown voltage characteristic by applying a junction termination structure using a multistage FP, it is necessary to increase the resistivity of the drift region in order to suppress an increase in the electric field strength on the substrate surface.

  However, in a conventional asymmetric IGBT having a buffer region in contact with the collector region, when a defect layer for controlling the lifetime of minority carriers is introduced into the buffer region or the like, the resistivity of the drift region If the value is increased, the depletion layer may extend too much, resulting in a significant increase in leakage current.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  An outline of representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, the outline of an embodiment of the present application is that a drift region has a field stop region separated from a buffer region in contact with the collector region on the back surface of the semiconductor chip, and a crystal defect region is formed between this and the buffer region. An IGBT having a ring-shaped multistage field plate around a cell region on the surface of a semiconductor chip.

  The effects obtained by the representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, according to the embodiment of the present application, the peripheral length can be shortened without causing a significant increase in leakage current.

It is an interconnection diagram of IGBT and a diode pair which shows the usage form of the semiconductor device (IGBT and diode) of each embodiment of this application. FIG. 2 is a circuit diagram of a motor drive circuit in which the IGBT and the diode pair shown in FIG. 1 are applied to drive a three-phase motor. It is a top surface schematic layout figure of the cell region of IE type | mold trench gate IGBT device chip | tip for describing the outline of main embodiment of this application, and its periphery. FIG. 4 is a device schematic cross-sectional view corresponding to the A-A ′ cross section of the cell region end cutout region R <b> 1 of FIG. 3. FIG. 9 is an enlarged top view of the linear unit cell region of FIG. 3 and its periphery R5 regarding one embodiment of the present application (one-dimensional active cell thinning structure: corresponding to FIGS. 6 to 8). FIG. 6 is an overall top view of the IE-type trench gate IGBT device chip of the one embodiment of the present application (common to other embodiments) (almost corresponding to FIG. 3 but close to a more specific shape). FIG. 7 is an enlarged top view of the cell region internal cutout region R3 of FIG. 6. It is device sectional drawing corresponding to the D-D 'cross section of FIG. FIG. 9 is a device sectional view in the manufacturing process (hole barrier region introducing step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (P-type floating region introduction step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (trench processing hard mask film forming step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application; FIG. 9 is a device sectional view in the manufacturing process (trench hard mask processing step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (trench hard mask processing resist removal step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application; FIG. 9 is a device sectional view in the manufacturing process (trench processing step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (trench processing hard mask removal step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application; FIG. 9 is a device cross-sectional view in the manufacturing process (stretch diffusion and gate oxidation step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (gate polysilicon film forming step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (gate polysilicon etchback step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (gate oxide film etchback step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application; FIG. 9 is a device sectional view in the manufacturing process (P-type body region and N + type emitter region introduction step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (interlayer insulating film forming step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. It is device sectional drawing in the manufacturing process (contact hole formation process) corresponding to FIG. 8 for demonstrating the manufacturing method corresponding to the device structure of the said one Embodiment of this application. FIG. 9 is a device cross-sectional view in the manufacturing process (substrate etching process) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (P + type body contact region and P + type latch-up prevention region introducing step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application; . FIG. 9 is a device sectional view in the manufacturing process (surface metal film forming step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (N-type field stop region introduction step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (back grinding process) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (N-type buffer region introduction step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (P + type collector region introduction step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (metal collector electrode formation step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 7 is an enlarged top view of the cell region internal cutout region R3 of FIG. 6 relating to a modification (full active cell region) of the IGBT cell structure according to the embodiment of the present application. FIG. 32 is a device cross-sectional view corresponding to the D-D ′ cross section of FIG. 31; It is local detailed sectional drawing of the device back surface for demonstrating the device structure of the modified example (aluminum dope contact) of the back surface detailed structure of IGBT of the said one Embodiment of this application, and its manufacturing method. FIG. 9 is a device sectional view in the manufacturing process (N-type field stop region introduction step) corresponding to FIG. 8 for describing the modification (epitaxial process) of the surface device formation process regarding the IGBT according to the embodiment of the present application; FIG. 9 is a device cross-sectional view in the manufacturing process (N-type silicon epitaxial region forming step) corresponding to FIG. 8 for describing a modification (epitaxial process) of the surface device forming process related to the IGBT according to the embodiment of the present invention; . FIG. 7 is an overall top view of a diode chip corresponding to FIG. 6 relating to a basic example (a PIN diode having a crystal defect region and an intermediate field stop region) of a power diode according to an embodiment of the present application. FIG. 37 is a device cross-sectional view of a main device region corresponding to the F-F ′ cross section of FIG. 36. FIG. 38 is a device cross-sectional view during the manufacturing process (P-type anode region introducing step) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. FIG. 38 is a device cross-sectional view during the manufacturing process (metal anode electrode formation step) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. FIG. 38 is a device cross-sectional view during the manufacturing process (N-type field stop region introduction step) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. FIG. 38 is a device cross-sectional view during the manufacturing process (back grinding process) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode according to the embodiment of the present application. FIG. 38 is a device cross-sectional view during the manufacturing process (N-type cathode region introduction step) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. FIG. 38 is a device cross-sectional view during the manufacturing process (metal cathode electrode forming step) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. FIG. 37 is a device cross-sectional view of a unit cell portion corresponding to the FF ′ cross section of FIG. 36 regarding Modification 1 (MPS diode having a crystal defect region and an intermediate field stop region) of the power diode according to the embodiment of the present application. . FIG. 37 is a device cross-sectional view of a unit cell portion corresponding to the F-F ′ cross section of FIG. 36 regarding Modification 1 (SSD having a crystal defect region and an intermediate field stop region) of the power diode according to the embodiment of the present application. The junction termination structure (basic structure: back surface intermediate field stop-front surface single polysilicon & double metal field plate combination structure) of the IGBT according to the one embodiment of the present application from the semiconductor chip end to the cell peripheral junction region FIG. 5 is a schematic cross-sectional view (corresponding substantially to a chip peripheral region in FIG. 4). FIG. 46 is a schematic cross-sectional view corresponding to FIG. 46 for explaining Modification 1 (back surface intermediate field stop-front surface double polysilicon & double metal field plate combination structure) relating to the junction termination structure of the IGBT according to the embodiment of the present invention. 4 substantially corresponds to the chip peripheral area). 46 is a schematic cross-sectional view corresponding to FIG. 46 (FIG. 4) for explaining a modification 2 (back surface intermediate field stop-front surface field plate & junction termination extension combined structure) relating to the junction termination structure of the IGBT according to the embodiment of the present invention. It almost corresponds to the chip peripheral area). 46 is a schematic cross-sectional view corresponding to FIG. 46 (chip peripheral region in FIG. 4) for explaining a third modification (back surface thick film buffer-front surface multistage field plate combination structure) relating to the junction termination structure of the IGBT according to the embodiment of the present invention Almost corresponding). FIG. 4 is a schematic cross-sectional view corresponding to FIG. 46 for explaining Modification 4 (back surface thick film buffer & high concentration buffer-front surface multi-stage field plate combination structure) relating to the junction termination structure of the IGBT according to the embodiment of the present invention. Corresponding to the peripheral area of the chip). Device in the manufacturing process (thin film field silicon oxide film forming process) of the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT of the one embodiment of the present application It is sectional drawing. Device cross section during the manufacturing process (thin film field silicon oxide film processing step) of the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT of the one embodiment of the present application. FIG. Device sectional view in the manufacturing process (P-type well region introducing step) of the part of FIG. 46 corresponding to FIGS. 9 to 30 of the cell region for explaining the chip peripheral process in the IGBT of the embodiment of the present application. It is. In the manufacturing process (the trench forming hard mask film forming process) of the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT of the one embodiment of the present application. It is device sectional drawing. Device in the manufacturing process (trench forming hard mask film processing step) of the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present application. It is sectional drawing. FIG. 47 is a device cross-sectional view during the manufacturing process (trench formation step) of the portion of FIG. 46 corresponding approximately to FIGS. 9 to 30 in the cell region for illustrating the chip peripheral process in the IGBT according to the embodiment of the present application; Device in the manufacturing process (trench forming hard mask film removing process) of the part of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT of the one embodiment of the present application It is sectional drawing. Device sectional view in the manufacturing process (gate insulating film forming process) of the part of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT of the one embodiment of the present application. It is. Device sectional view in the manufacturing process (polysilicon film forming process) of the part of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present application. It is. 46 is a device sectional view in the manufacturing step (polysilicon film processing step) of the portion in FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present application; FIG. is there. In the manufacturing process (the silicon oxide film forming process for ion implantation) of the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT of the one embodiment of the present application. It is device sectional drawing. Device sectional view in the manufacturing process (P-type body region introducing step) of the portion of FIG. 46 corresponding to FIG. 9 to FIG. 30 of the cell region for explaining the chip peripheral process in the IGBT of the embodiment of the present application. It is. During the manufacturing process of the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present invention (chip end N + type substrate contact region introducing step) FIG. Device sectional view in the manufacturing process (etch stop film forming step) of the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT of the one embodiment of the present application. It is. During the manufacturing process (thick film field silicon oxide film forming process) of the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT of the one embodiment of the present application. It is device sectional drawing. The device in the manufacturing process (thick film field silicon oxide film processing step) of the part of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT of the one embodiment of the present application It is sectional drawing. In the manufacturing process (interlayer insulating film formation & contact first stage process) of the part of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT of the one embodiment of the present application. It is device sectional drawing. FIG. 47 is a device cross-sectional view of the cell region for explaining a chip peripheral process in the IGBT according to the embodiment of the invention of the present application during the manufacturing step (contact final step) of the portion in FIG. 46 substantially corresponding to FIGS. 9 to 30. . FIG. 47 is a device cross-sectional view during the manufacturing step (substrate etching step) of the portion in FIG. 46 corresponding approximately to FIGS. 9 to 30 in the cell region for describing the chip peripheral process in the IGBT according to the embodiment of the present application; During the manufacturing process of the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present invention (chip end P + type body contact region introducing step) FIG. Device sectional view in the manufacturing process (aluminum-based metal electrode forming process) of the part of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present application. It is. Device cross section during the manufacturing process (N-type field stop region forming step) of the portion of FIG. 46 corresponding to FIGS. 9 to 30 of the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present application. FIG. FIG. 47 is a device cross-sectional view during the manufacturing process (back grinding process) of the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present application; . During the manufacturing process of the portion of FIG. 46 corresponding to FIGS. 9 to 30 of the cell region for explaining the chip peripheral process in the IGBT of the embodiment of the present invention (N-type buffer region & P + type collector region introduction step) FIG. FIG. 7 is an enlarged top plan view of a cell region corner cutout region R4 of FIG. 6 for explaining a cell peripheral structure in the IGBT according to the embodiment of the present application. FIG. 76 is a device sectional view corresponding to a section taken along line H-H ′ of FIG. 75. FIG. 38 is a device cross-sectional view of the main junction main part of Modification 1 (an example in which the N-type thick film cathode region is applied) of the power diode of FIG. 37. FIG. 38 is a device cross-sectional view of the main junction main part of Modification 2 of the power diode of FIG. 37 (an example in which an N-type thick film cathode region and a high concentration cathode region are applied). FIG. 45 is a device cross-sectional view of the main junction part of a further modification 2 (example in which the N-type thick film cathode region is applied) of the power diode in FIG. 44. FIG. 45 is a device cross-sectional view of a main junction part of a further modification 3 (an example in which an N-type thick film cathode region and a high concentration cathode region are applied) of the power diode of FIG. 44; FIG. 46 is a device cross-sectional view of the main junction part of a further modification 2 (example in which an N-type thick film cathode region is applied) of the power diode in FIG. 45. FIG. 46 is a device cross-sectional view of a main junction part of a further modification 3 (an example in which an N-type thick film cathode region and a high concentration cathode region are applied) of the power diode of FIG. 45. It is a chip | tip upper surface schematic whole figure for demonstrating the outline of the junction termination | terminus structure of IGBT of the said one Embodiment of this application. FIG. 84 is a schematic top view of a chip upper surface for explaining an example of outline variations of the junction termination structure of FIG. 83.

[Outline of Embodiment]
First, an outline of a typical embodiment disclosed in the present application will be described.

1. IGBT including:
(A) a semiconductor substrate having a first main surface and a second main surface;
(B) a drift region of a first conductivity type that occupies the main part from the first main surface of the semiconductor substrate to the inside;
(C) a cell region provided from the first main surface to the inside of the drift region;
(D) a ring-like shape that is a surface region on the first main surface side of the drift region and that surrounds the periphery of the cell region and has a second conductivity type opposite to the first conductivity type. Cell peripheral junction area;
(E) a ring-shaped multistage field plate provided so as to surround the periphery of the cell region between the cell peripheral junction region and the peripheral edge of the semiconductor substrate;
(F) The channel region of the second conductivity type provided in the first principal surface side surface region of the drift region in the cell region;
(G) the emitter region of the first conductivity type provided in the first principal surface side surface region of the channel region;
(H) the collector region of the second conductivity type provided in the second principal surface side surface region of the drift region;
(I) the buffer region of the first conductivity type provided between the collector region and the drift region and having a higher concentration than this;
(J) A crystal defect region provided in the vicinity of the boundary from the vicinity of the boundary along the buffer region;
(K) A field stop region of the first conductivity type provided in the drift region on the first main surface side along the crystal defect region and having a higher concentration than the drift region.

  2. In the IGBT according to Item 1, the semiconductor substrate is a single crystal silicon substrate.

  3. In the IGBT according to Item 1 or 2, the single crystal silicon substrate is formed by an FZ method.

  4). In the IGBT according to any one of Items 1 to 3, the IGBT is a trench gate type.

  5. In the IGBT according to any one of Items 1 to 4, the field stop region is formed by irradiation with hydrogen ions or helium ions.

  6). In the IGBT according to any one of Items 1 to 5, the crystal defect region is left during activation annealing of the collector region and the buffer region.

7). The IGBT according to any one of Items 1 to 6, further comprising:
(L) A ring-shaped surface resurf region having the second conductivity type, which is provided on the first main surface side surface region of the drift region and surrounds the periphery of the cell peripheral junction region.

8). In the IGBT according to any one of Items 1 to 7, the multi-stage field plate has the following:
(E1) Multistage metal field plate.

9. In the IGBT of paragraph 8, the multi-stage field plate has the following:
(E2) A poly-Si field plate provided between the inner end of the metal field plate and the outer end of the cell peripheral junction region.

  10. In the IGBT according to Item 9, the poly-Si field plate is a multi-stage poly-Si field plate.

11. IGBT including:
(A) a semiconductor substrate having a first main surface and a second main surface;
(B) a drift region of a first conductivity type that occupies the main part from the first main surface of the semiconductor substrate to the inside;
(C) a cell region provided from the first main surface to the inside of the drift region;
(D) a ring-like shape that is a surface region on the first main surface side of the drift region and that surrounds the periphery of the cell region and has a second conductivity type opposite to the first conductivity type. Cell peripheral junction area;
(E) a ring-shaped multistage field plate provided so as to surround the periphery of the cell region between the cell peripheral junction region and the peripheral edge of the semiconductor substrate;
(F) The channel region of the second conductivity type provided in the first principal surface side surface region of the drift region in the cell region;
(G) the emitter region of the first conductivity type provided in the first principal surface side surface region of the channel region;
(H) the collector region of the second conductivity type provided in the second principal surface side surface region of the drift region;
(I) The thick film buffer region of the first conductivity type provided between the collector region and the drift region, thicker than the collector region, and higher in concentration than the drift region;
(J) A crystal defect region provided in the thick film buffer region.

  12 In the IGBT according to Item 11, the semiconductor substrate is a single crystal silicon substrate.

  13. In the IGBT according to Item 11 or 12, the single crystal silicon substrate is formed by an FZ method.

  14 In the IGBT according to any one of Items 11 to 13, the IGBT is a trench gate type.

  15. In the IGBT according to any one of Items 11 to 14, the crystal defect region is formed by irradiation with hydrogen ions or helium ions.

16. The IGBT according to any one of Items 11 to 14, further comprising:
(K) The first conductivity type high concentration buffer region provided between the collector region and the thick film buffer region and having a higher concentration than the thick film buffer region.

  17. In the IGBT of item 16, the crystal defect region is left during activation annealing of the high concentration buffer region.

18. In the IGBT according to any one of Items 11 to 17, the multi-stage field plate has the following:
(E1) Multistage metal field plate.

19. In the IGBT of paragraph 18, the multi-stage field plate comprises:
(E2) A poly-Si field plate provided between the inner end of the metal field plate and the outer end of the cell peripheral junction region.

  20. In the IGBT of Item 19, the poly-Si field plate is a multi-stage poly-Si field plate.

  Next, the other outline | summary is demonstrated about typical embodiment disclosed in this application.

21. Diode including:
(A) a semiconductor substrate having a first main surface and a second main surface;
(B) a drift region of a first conductivity type that occupies the main part from the first main surface of the semiconductor substrate to the inside;
(C) an anode region provided in a surface region on the first main surface side of the semiconductor substrate and having a second conductivity type opposite to the first conductivity type;
(D) a ring-shaped multi-stage field plate provided so as to surround the periphery of the anode region between the anode region and the peripheral edge of the semiconductor substrate;
(E) the cathode region of the first conductivity type provided in the surface region on the second main surface side of the drift region and having a higher concentration;
(F) A crystal defect region provided in the vicinity of the boundary from the vicinity of the boundary along the cathode region;
(G) A field stop region of the first conductivity type provided in the drift region on the first main surface side along the crystal defect region and having a higher concentration than the drift region.

  22. In the diode of item 21, the semiconductor substrate is a single crystal silicon substrate.

  23. In the diode of item 21 or 22, the single crystal silicon substrate is formed by an FZ method.

  24. 24. In the diode according to any one of Items 21 to 23, the field stop region is formed by hydrogen ion or helium ion implantation.

25. Diode including:
(A) a semiconductor substrate having a first main surface and a second main surface;
(B) a drift region of a first conductivity type that occupies the main part from the first main surface of the semiconductor substrate to the inside;
(C) a cell region provided from the first main surface to the inside of the drift region;
(D) a ring-like shape that is a surface region on the first main surface side of the drift region and that surrounds the periphery of the cell region and has a second conductivity type opposite to the first conductivity type. Cell peripheral junction area;
(E) a ring-shaped multi-stage field plate provided between the periphery of the cell peripheral junction region and the peripheral edge of the semiconductor substrate so as to surround the periphery of the cell peripheral junction region;
(F) the cathode region of the first conductivity type provided in the surface region on the second main surface side of the drift region and having a higher concentration;
(G) a crystal defect region provided in the vicinity of the boundary from the vicinity of the boundary along the cathode region;
(H) A field stop region of the first conductivity type provided in the drift region closer to the first main surface along the crystal defect region and having a higher concentration than the drift region.

  26. 26. In the diode of item 25, the semiconductor substrate is a single crystal silicon substrate.

  27. In the diode of the item 25 or 26, the single crystal silicon substrate is formed by an FZ method.

  28. 26. In the diode according to any one of items 25 to 27, the field stop region is formed by hydrogen ion or helium ion implantation.

29. Diode including:
(A) a semiconductor substrate having a first main surface and a second main surface;
(B) a drift region of a first conductivity type that occupies the main part from the first main surface of the semiconductor substrate to the inside;
(C) an anode region provided in a surface region on the first main surface side of the semiconductor substrate and having a second conductivity type opposite to the first conductivity type;
(D) a ring-shaped multi-stage field plate provided so as to surround the periphery of the anode region between the anode region and the peripheral edge of the semiconductor substrate;
(E) a thick film cathode region provided in the surface region on the second main surface side of the drift region and doped with sulfur or selenium at a higher concentration than this;
(F) A crystal defect region provided in the thick film cathode region.

  30. In the diode of item 29, the semiconductor substrate is a single crystal silicon substrate.

  31. In the diode of item 29 or 30, the single crystal silicon substrate is formed by an FZ method.

  32. 32. In the diode according to any one of Items 29 to 31, the crystal defect region is formed by irradiation with hydrogen ions or helium ions.

33. The diode according to any one of Items 29 to 31, further comprising:
(G) The high-concentration cathode region of the first conductivity type provided on the second main surface side surface of the thick-film cathode region and having a higher concentration than the thick-film cathode region.

  34. 34. In the diode of item 33, the crystal defect region is left during activation annealing of the high concentration cathode region.

35. Diode including:
(A) a semiconductor substrate having a first main surface and a second main surface;
(B) a drift region of a first conductivity type that occupies the main part from the first main surface of the semiconductor substrate to the inside;
(C) a cell region provided from the first main surface to the inside of the drift region;
(D) a ring-like shape that is a surface region on the first main surface side of the drift region and that surrounds the periphery of the cell region and has a second conductivity type opposite to the first conductivity type. Cell peripheral junction area;
(E) a ring-shaped multi-stage field plate provided between the periphery of the cell peripheral junction region and the peripheral edge of the semiconductor substrate so as to surround the periphery of the cell peripheral junction region;
(F) a thick film cathode region provided in the surface region on the second main surface side of the drift region and doped with sulfur or selenium at a higher concentration than this;
(G) A crystal defect region provided in the thick film cathode region.

  36. 36. In the diode of item 35, the semiconductor substrate is a single crystal silicon substrate.

  37. In the diode of the item 35 or 36, the single crystal silicon substrate is formed by an FZ method.

  38. 38. In the diode according to any one of Items 35 to 37, the crystal defect region is formed by irradiation with hydrogen ions or helium ions.

39. The diode according to any one of Items 35 to 37, further including:
(G) The high-concentration cathode region of the first conductivity type provided on the second main surface side surface of the thick-film cathode region and having a higher concentration than the thick-film buffer region.

  40. 40. In the diode of item 39, the crystal defect region is left during activation annealing of the high concentration cathode region.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Further, in the present application, the term “semiconductor device” mainly refers to various types of transistors, diodes (active elements) alone, or resistors, capacitors, etc., such as semiconductor chips (for example, single crystal silicon substrates, circuit boards, etc.). ) Integrated on top and packaged semiconductor chip or the like. Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. At this time, typical examples of various single transistors include power MOSFETs and IGBTs (Insulated Gate Bipolar Transistors). These are generally classified as power semiconductor devices, and include power MOSFETs, IGBTs, bipolar power transistors, thyristors, power diodes, and the like.

  A typical form of IGBT is a double-diffused vertical IGBT, which can be mainly classified into two types, the first being a planar gate type, and the second being an implementation. It is a trench gate type mainly described in the embodiment.

  Other IGBTs include LD-IGBT (Lateral-Diffused IGBT).

  In the present application, when the term “IGBT” or “diode” is used, it goes without saying that it includes a device including the IGBT or diode.

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say.

  Similarly, “silicon oxide film”, “silicon oxide insulating film” and the like are not only relatively pure undoped silicon oxide but also other silicon oxide as main components. Including membrane. For example, a silicon oxide insulating film doped with impurities such as TEOS-based silicon oxide (TEOS-based silicon oxide), PSG (phosphorus silicon glass), BPSG (borophosphosilicate glass) is also a silicon oxide film. In addition to a thermal oxide film and a CVD oxide film, a coating system film such as SOG (Spin On Glass) or nano-clustering silica (NSC) is also a silicon oxide film or a silicon oxide insulating film. In addition, a low-k insulating film such as FSG (Fluorosilicate Glass), SiOC (Silicon Oxide silicide), carbon-doped silicon oxide (OSD), or OSG (Organosilicate Glass) is similarly used. It is a membrane. Further, a silica-based Low-k insulating film (porous insulating film, including “porous” or “porous”) including a hole in a member similar to these is also a silicon oxide film or silicon oxide. It is a system insulating film.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like. Here, “silicon nitride” includes both SiN and SiNH unless otherwise specified. Similarly, “SiCN” includes both SiCN and SiCNH, unless otherwise specified.

  Although SiC has properties similar to SiN, SiON should be classified as a silicon oxide insulating film in many cases, but in the case of an etch stop film, it is close to SiC, SiN, or the like.

  A silicon nitride film is frequently used as an etch stop film in SAC (Self-Aligned Contact) technology, that is, CESL (Contact Etch-Stop Layer), and also as a stress applying film in SMT (Stress Measurement Technique). .

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context. Therefore, for example, “square” includes a substantially square, “orthogonal” includes a case where the two are substantially orthogonal, and “match” includes a case where the two substantially match. The same applies to “parallel” and “right angle”. Therefore, for example, a deviation of about 10 degrees from perfect parallel belongs to substantially parallel.

  In addition, for a certain region, “whole”, “whole”, “whole area” and the like include cases of “substantially whole”, “substantially general”, “substantially whole area” and the like. Therefore, for example, 80% or more of a certain region can be referred to as “substantially the whole”, “substantially general”, and “substantially the entire region”. The same applies to “all circumferences”, “full lengths”, and the like.

  Further, regarding the shape of a certain object, “rectangular” includes “substantially rectangular”. Therefore, for example, if the area of the portion different from the rectangle is less than about 20% of the whole, it can be said to be almost rectangular. The same applies to “annular” and the like.

  Also, with regard to periodicity, “periodic” includes almost periodic, and for each element, for example, if the deviation of the period is less than about 20%, each element is said to be “almost periodic”. it can. Furthermore, if what is out of this range is, for example, less than about 20% of all elements that are targets of the periodicity, it can be said to be “substantially periodic” as a whole.

  Note that the definitions in this section are general, and when there are different definitions in the following individual descriptions, priority is given to the individual descriptions for this part. However, the definition, provisions, etc. of this section are still valid for parts that are not stipulated in the individual description part, unless explicitly denied.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value. In the present application, regarding the number, “many” is a concept including “plurality”.

  5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor integrated circuit device (same as a semiconductor device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

  6). Although the trench gate type IGBT has a relatively low on-resistance, in order to further promote conductivity modulation and further lower the on-resistance, an “IE type trench gate IGBT” using an IE (Injection Enhancement) effect (or “Active cell thinning-out type trench gate IGBT”) has been developed. The IE type trench gate IGBT has an active cell (Active Cell) actually connected to an emitter electrode and an inactive cell (Inactive Cell) having a P type floating region in a cell region, or a comb-like structure. By arranging in a tooth shape, the structure is such that holes are easily accumulated on the device main surface side (emitter side) of the semiconductor substrate.

  In the present application, when it is necessary to distinguish a conventional trench gate IGBT that is not an IE trench gate IGBT, that is, a non-active cell thinning type, from an IE trench gate IGBT, it is referred to as “full active type”. This is referred to as “trench gate IGBT (or non-IE trench gate IGBT)”. Note that “full active” does not exclude peripheral dummy cells, inactive cells as peripheral structures, and the like.

  7). In the present application, among the IE-type trench gate IGBTs, a main active cell whose width is narrower than a main inactive cell is referred to as a “narrow active cell IE-type trench gate IGBT”.

  The direction crossing the trench gate is defined as “cell width direction”, and the extending direction (longitudinal direction) of the trench gate (linear gate portion) orthogonal thereto is defined as “cell length direction”.

  In this application, mainly “linear unit cell region” (consisting of a linear active cell region and a linear inactive cell region) is mainly handled, but this linear unit cell region is periodically repeated. Thus, they are arranged in the internal area of the semiconductor chip to constitute a “cell area”.

  A cell peripheral junction region is usually provided around the cell region, and a field plate (Field Plate), a floating field ring (Floating Field Ring), etc. are provided around the cell region to form a termination structure. doing. Here, the floating field ring (also referred to as “field limiting ring”) refers to the following. In other words, the surface of the drift region (device surface) is provided separately from the P-type body region (P-type well region), and has the same conductivity type and similar concentration (reverse voltage is applied to the main junction). An impurity region or a group of impurity regions having a single or multiple cell regions in a ring shape. In the following example, a typical floating field ring is not provided in order to shorten the peripheral length, but application of this is not excluded.

  The field plate is a conductor film pattern, which extends above the surface of the drift region (including the device surface and the inside of the trench) through the insulating film and refers to a portion surrounding the cell region in a ring shape. .

  Although it is reasonable to treat the linear unit cell area as a periodic element constituting the cell area as a set of linear inactive cell areas arranged on both sides centering on the linear active cell area, Specifically, when the linear inactive cell region is individually described, it is inconvenient because it is separated on both sides. In this case, a specific integral part is referred to as a linear inactive cell region.

  8). In this application, when describing a diode, the description regarding IGBT is used as needed. When the diode is viewed as a bipolar structure without the gate of the IGBT, the anode of the diode corresponds to the emitter of the IGBT and the cathode of the diode corresponds to the collector of the IGBT.

  Diodes used as fly-back diodes are classified into PIN diodes (Pin Diodes) and Schottky diodes (Schottky Diodes). Further, as a composite device, there are an MPS (Merged Pin-Schottky) diode, an SSD (Static-Shielding-Diode) and the like.

  9. In the present application, an IGBT having a buffer region or a field stop region on the back side is referred to as an “asymmetric IGBT”. In this asymmetric IGBT, an IGBT in which a defect layer for minority carrier lifetime control is introduced on the back side is referred to as a “defect layer introduction type asymmetric IGBT”. Further, an IGBT in which a buffer region having a thickness of 10 micrometers or more is introduced on the back surface side is referred to as a “thick film buffer asymmetric IGBT”, and the buffer region is referred to as a “thick film buffer region”. A structure in which a defect layer is introduced into the thick film buffer region is particularly referred to as “defect layer introduction type thick film buffer asymmetric IGBT”. When distinguishing those in which a defective layer is not introduced, it is referred to as “defect layer non-introduced thick film buffer asymmetric IGBT”.

  In addition, a defect layer introduction type asymmetric IGBT having an intermediate field stop introduced instead of the thick film buffer asymmetric IGBT is referred to as an “intermediate field stop type asymmetric IGBT”. On the other hand, an asymmetric IGBT that is not a thick film buffer asymmetric IGBT and is not an intermediate field stop asymmetric IGBT is referred to as a “general asymmetric IGBT”.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

  In addition, regarding the designation in the case of the alternative, when one is referred to as “first” or the like and the other is referred to as “second” or the like, it is exemplified in association with the representative embodiment. Of course, for example, “first” is not limited to the illustrated option.

  For example, Japanese Patent Application No. 2011-127305 (Japanese application date: June 7, 2011) discloses a prior art application that discloses a device structure having a field stop layer inside an N-type drift region in an asymmetric IGBT. Day).

1. Description of main application fields such as semiconductor device (IGBT, diode) of each embodiment of the present application (mainly FIG. 1 and FIG. 2)
Hereinafter, the motor drive circuit will be specifically described as an application example, but it is needless to say that the application field of the semiconductor device (IGBT, diode) and the like of each embodiment of the present application is not limited to this.

  FIG. 1 is an interconnection diagram of an IGBT and a diode pair showing how the semiconductor device (IGBT and diode) of each embodiment of the present application is used. FIG. 2 is a circuit diagram of a motor drive circuit in which the IGBT and the diode pair shown in FIG. 1 are applied to drive a three-phase motor. Based on these, main application fields such as the semiconductor device (IGBT, diode) of each embodiment of the present application will be described.

  The IGBT and the diode constituting the embodiment of the present application are used in a pair connection state (for example, as a pair module) as shown in FIG. That is, the collector terminal C of the IGBT (Q) and the cathode terminal K of the flyback diode D are connected, and the emitter terminal E of the IGBT (Q) and the anode terminal A of the flyback diode D are connected. When viewed from the outside, there are three terminals including the gate terminal G.

  Next, FIG. 2 shows an example of a specific application circuit (three-phase motor drive circuit) of the IGBT & diode pair Pa, Pb, Pc, Pd, Pe, Pf. As shown in FIG. 2, this three-phase motor drive circuit uses the IGBT & diode pairs Pa, Pb, Pc, Pd, Pe, and Pf to switch the output from the DC power supply 31 at high speed, thereby making the three-phase motor 30 Is driving. Each IGBT & diode pair Pa, Pb, Pc, Pd, Pe, Pf is composed of a combination of IGBT elements Qa, Qb, Qc, Qd, Qe, Qf and power diode elements Da, Db, Dc, Dd, De, Df. ing.

  The power diode element described in the present application is not limited to the above-described IGBT, but may be used as a switching element such as a MOS transistor or a bipolar transistor, and is not limited to a three-phase motor. Can be widely used.

2. Description of the overall structure of the IGBT device chip according to an embodiment of the present application (mainly FIGS. 3 to 5)
In this section, specific examples are shown, the above definitions are supplemented, representative specific examples of the present application are extracted, their outlines are explained, and overall preliminary explanations are given.

  In the following description, the IE type trench gate IGBT will be specifically described as an example. However, as will be described later, it goes without saying that the present invention can also be applied to a full active type trench gate IGBT as it is.

  FIG. 3 is a schematic layout diagram of the upper surface of the cell region of the IE trench gate IGBT device chip and its periphery for explaining the outline of the main embodiment of the present application. FIG. 4 is a device schematic cross-sectional view corresponding to the A-A ′ cross section of the cell region end cutout region R <b> 1 of FIG. 3. FIG. 5 is an enlarged top view of the linear unit cell region of FIG. 3 and its periphery R5 relating to the one embodiment of the present application (one-dimensional active cell thinning structure: corresponding to FIGS. 6 to 8). Based on these, the entire structure and the like of the IGBT device chip according to the embodiment of the present application will be described.

(1) Description of the planar structure of the cell region and its periphery (mainly FIG. 3):
First, the upper surface of the inner region of the device chip 2 of the IE-type trench gate IGBT, which is the main object of the description in this section (the inner part of the guard ring or the like that is the outermost part of the termination structure, that is, the main part of the chip 2). The figure is shown in FIG. As shown in FIG. 3, the main part of the internal region of the chip 2 (semiconductor substrate) is occupied by the cell region 10. On the outer periphery of the cell region 10, a P-type cell peripheral junction region 35 is provided so as to surround the cell region 10. A metal field plate 4m having an annular shape is provided outside the cell peripheral junction region 35 at intervals, and together with the cell peripheral junction region 35, the metal guard ring 3m (see FIG. 6), etc., the cell region 10 This constitutes a termination structure.

  In this example, a large number of linear unit cell regions 40 are laid in the cell region 10, and a pair of or more dummy cells (about one or several columns in one case) are provided in these end regions. A region 34 (linear dummy cell region) is arranged.

(2) Description of intermediate field stop region, narrow active cell type unit cells and alternate arrangement method (mainly FIG. 4):
Next, FIG. 4 shows an AA ′ cross section of the cell region end cutout region R1 of FIG. As shown in FIG. 4, a P + type collector region 18 is provided in a semiconductor region (in this example, a silicon single crystal region) on the back surface 1 b (the back main surface or the second main surface of the semiconductor substrate) of the chip 2. The metal collector electrode 17 is provided on the surface. Between the N − type drift region 20 (first conductivity type drift region) and the P + type collector region 18 (second conductivity type collector region) constituting the main part of the semiconductor substrate 2, there is an N − type drift region. An N-type buffer region 19 (first conductivity type buffer region) having a concentration higher than 20 is provided. That is, the N-type buffer region 19 is provided in the N− type drift region 20 inside so as to be in contact with the P + type collector region 18. A crystal defect region 41 is provided along the N-type buffer region 19 in the vicinity of the boundary (the boundary between the N-type buffer region 19 and the N-type drift region 20) and in the vicinity of the N-type drift region 20. Further, an N-type field stop region having a higher concentration than the N-type drift region 20 is formed in the N-type drift region 20 on the first main surface side so as to extend along the crystal defect region 41. 42 is provided.

  Here, the crystal defect region 41 is for improving the switching characteristics by limiting the lifetime of the holes. For example, the activation defect after the introduction of the N-type buffer region 19 and the P + type collector region 18 is performed. The crystal defects that remain are used. The N-type field stop region 42 (intermediate field stop region) has an effect of preventing the depletion layer from reaching the crystal defect region 41 and preventing an increase in leakage current in the off state. Further, since there is an N-type field stop region 42 (intermediate field stop region) with the N-type drift region 20 sandwiched between the N-type buffer region 19 and the P + type collector region that determines the hole injection efficiency. There is an advantage that the concentration relationship of the PN junction between the N-type buffer region 19 and the concentration of the N-type field stop region 42 can be set independently.

  On the other hand, a large number of trenches 21 are provided in the semiconductor region on the surface side 1a (the front-side main surface or the first main surface of the semiconductor substrate) of the N − type drift region 20, and a gate insulating film is included therein. A trench gate electrode 14 is embedded via 22. These trench gate electrodes 14 are connected to the metal gate electrode 5 (FIG. 6) via the metal gate wiring 7 and the like.

  Further, these trenches 21 function to partition each region. For example, the dummy cell region 34 is partitioned from both sides by a pair of trenches 21, and the cell region 10 is formed by one of the trenches 21. The cell peripheral junction region 35 (or the chip peripheral region 90) is partitioned. The cell peripheral junction region 35 is connected to the metal emitter electrode 8 through the P + type body contact region 25p. In the present application, unless otherwise specified, the thickness of the gate insulating film 22 in any part of the trench is substantially the same (however, if necessary, the thickness of a part is different from that of the other part and is different. Is not to eliminate). As described above, by making emitter contact in the cell peripheral junction region 35 and the dummy cell region 34, it is possible to prevent the breakdown voltage from being lowered even when the width of the dummy cell region 34 or the like is changed in a process. it can. Of course, this is not essential.

  On the surface 1 a of the N − type drift region 20 outside the cell peripheral junction region 35, a metal field plate 4 m connected to the emitter potential is provided via an end insulating film 56. A polysilicon field plate 4 p connected to the gate potential is provided in the end insulating film 56 from the outer end of the cell peripheral junction region 35 to the N − type drift region 20. That is, the metal field plate 4m and the polysilicon field plate 4p constitute the field plate 4 that is the main part of the junction termination structure. Note that the gate potential is set to the same potential as the emitter potential when turned off. That is, the polysilicon field plate 4p is a single-stage (one-stage) field plate, the metal field plate 4m is a multi-stage (two-stage) field plate, and the field plate 4 is a multi-stage (three-stage) field plate. Is configured. In this example, the polysilicon field plate 4p is connected to the gate potential. However, it goes without saying that the polysilicon field plate 4p may be connected to the emitter potential. This is because when the IGBT is off, the gate potential becomes equal to the emitter potential, so that it can be said that the field plate is almost equivalent regardless of the connection. In this example, a polysilicon electrode (polysilicon annular film for gate extraction) that is integrated with the trench electrode exists in an annular shape from the gate lead portion 14w to above the ring-shaped P-type cell peripheral junction region 35. Therefore, it is convenient to extend it as it is to the outer edge of the P-type cell peripheral junction region 35. Thus, there is an advantage that the metal gate wiring-trench gate electrode connecting portion 13 can be used as it is as the gate wiring-poly-Si field plate connecting portion 82 shown in FIG.

  This is the same in the following figures.

  Next, the cell region 10 will be further described. The dummy cell region 34 is basically the same in structure and size as the linear active cell region 40a except that it does not have the N + type emitter region 12, and is a P + type body provided on the surface of the P type body region 15. Contact region 25 d is connected to metal emitter electrode 8. Most of the inner region of the cell region 10 basically has a repetitive structure to be translated with the linear unit cell region 40 as a unit cell (note that the objectivity in a strict sense is not required. The same applies hereinafter. ) The linear unit cell region 40 as a unit lattice is composed of a linear active cell region 40a and half-width linear inactive cell regions 40i on both sides thereof, specifically, adjacent linear active cell regions 40i. It can be seen that a linear inactive cell region 40i having a full width is disposed between the layers 40a (see FIG. 5).

  A P-type body region 15 (second-conductivity-type channel region) is provided in a semiconductor surface region on the front-side main surface 1a (first main surface) side of the semiconductor substrate of the linear active cell region 40a. Are provided with an N + type emitter region 12 (first conductivity type emitter region) and a P + type body contact region 25. The P + type body contact region 25 is connected to the metal emitter electrode 8. In the linear active cell region 40 a, an N-type hole barrier region 24 is provided in the N − -type drift region 20 below the P-type body region 15. Needless to say, the N-type hole barrier region 24 is not essential.

  On the other hand, a P-type body region 15 is similarly provided in the semiconductor surface region on the front-side main surface 1a (first main surface) side of the semiconductor substrate in the linear inactive cell region 40i, and the N− The type drift region 20 is provided with a P-type floating region 16 (second conductivity type floating region) that covers the lower ends of the trenches 21 on both sides and is deeper than that. By providing such a P-type floating region 16, the width Wi of the linear inactive cell region can be increased without causing a sharp drop in breakdown voltage. This makes it possible to effectively enhance the hole accumulation effect. In the IE type trench gate IGBT, the P type floating region 16 accumulates holes therein, thereby reducing the hole concentration of the N − type drift region 20 (N base region) below the linear active cell region 40a. As a result, the on-resistance is reduced by increasing the concentration of electrons injected from the MOSFET in the IGBT into the N base region.

  In this example, the width Wa of the linear active cell region 40a is narrower than the width Wi of the linear inactive cell region 40i. In the present application, this is referred to as a “narrow active cell unit cell”. Hereinafter, the device having the narrow active cell unit cell will be specifically described below. However, the following example is not limited thereto, and the device having the “non-narrow active cell unit cell”. Needless to say, it can also be applied.

  In the example of FIG. 4, the linear unit cell region 40 is configured by alternately arranging the linear active cell regions 40a and the linear inactive cell regions 40i. This is called an “arrangement method”. In the following description, the description will be made on the premise of the alternating arrangement method unless otherwise specified. Needless to say, the “non-alternating arrangement method” may be used.

  In FIG. 4, the main part that illustratively includes each part of various embodiments of the present application has been described. However, in the following description, these are constituent elements such as a cell part (cross section, planar structure), a cell peripheral part, and the like. Although these are described separately, they are not individually separated, but as shown in FIG. 4, various modified examples are replaced with the respective constituent elements to constitute the main part.

(3) Description of active cell one-dimensional thinning structure (mainly FIG. 5)
An example of the detailed planar structure of the main part of the linear unit cell region of FIG. 3 and the surrounding cutout region R5 is shown in FIG. As shown in FIG. 5, the N + type emitter region 12 is provided in the entire length direction of the linear active cell region 40a. That is, the entire area of the linear active cell region 40a in the length direction is an active section 40aa. Here, the active section 40aa refers to a section in the length direction of the linear active cell region 40a in which the N + -type emitter region 12 is provided.

  In the present application, this structure is referred to as an “active cell one-dimensional thinning structure”.

3. Description of the cell structure of the IGBT according to the embodiment of the present application (mainly FIGS. 6 to 8)
In this section, based on the description of sections 1 and 2, an example of a specific chip top surface layout and unit cell structure corresponding to the above embodiment (one-dimensional thinning of active cells corresponding to FIGS. 3 to 5 in section 2). Taking the structure as an example). The cell structure described in this section is an alternating array type narrow active cell unit cell.

  In general, when the IGBT element 2 having a withstand voltage of 600 volts is taken as an example, the average chip size is 3 to 6 mm square. Here, for convenience of explanation, a chip having a length of 4 mm and a width of 5.2 mm will be described as an example. Here, description will be made assuming that the breakdown voltage of the device is about 600 volts, for example.

  In some of the drawings described below, the display of an etch stop film, an ion implantation insulating film, and the like that are not important for the description is omitted.

  FIG. 6 is an overall top view (almost corresponding to FIG. 3 but close to a more specific shape) of the IE-type trench gate IGBT device chip according to the one embodiment of the present application (common to other embodiments). is there. FIG. 7 is an enlarged top view (P-type deep floating & hole barrier linear unit cell structure) of the cell region internal cutout region R3 of FIG. FIG. 8 is a device cross-sectional view corresponding to the D-D ′ cross section of FIG. 7. Based on these, the device structure of the IE-type trench gate IGBT in the one embodiment of the present application will be described.

  As shown in FIG. 6, an annular metal guard ring 3 m made of, for example, an aluminum wiring layer is provided on the outer peripheral portion of the upper surface 1 a of the IGBT device chip 2. A metal field plate 4m (for example, composed of the same aluminum-based wiring layer as before) is provided. In this figure, a polysilicon field plate or the like is not shown to ensure clarity of the figure (see FIGS. 4, 46, 84, etc.). A cell region 10 is provided inside the metal field plate 4m and in the main part of the inner region of the upper surface 1a of the chip 2, and the cell region 10 is formed, for example, in the same aluminum as before. It is covered with a metal emitter electrode 8 composed of a system wiring layer or the like. The central portion of the metal emitter electrode 8 is a metal emitter pad 9 for connecting a bonding wire or the like. Between the metal emitter electrode 8 and the metal field plate 4m, for example, the same aluminum-based wiring layer or the like as before. A metal gate wiring 7 composed of The metal gate wiring 7 is connected to, for example, a metal gate electrode 5 composed of the same aluminum-based wiring layer or the like, and the central portion of the metal gate electrode 5 is a gate pad for connecting a bonding wire or the like. 6 The metal field plate 4m is connected to the metal emitter electrode 8 via, for example, a metal field plate-metal emitter electrode connecting portion 4c. Note that portions other than the metal emitter pad 9 and the gate pad 6 are generally covered with a final passivation film 60.

  Next, an enlarged top view of the cell region internal cutout region R3 of FIG. 6 is shown in FIG. As shown in FIG. 7, the cell region 10 is composed of linear active cell regions 40a and linear inactive cell regions 40i arranged alternately in the horizontal direction. A trench gate electrode 14 is disposed between the linear active cell region 40a and the linear inactive cell region 40i, and a linear contact groove 11 (or contact) is formed at the center of the linear active cell region 40a. Hall) is arranged. A linear N + type emitter region 12 is provided in the linear active cell region 40 a on both sides of the contact groove 11. On the other hand, in the linear inactive cell region 40i, a P-type body region 15 and a P-type floating region 16 are provided on the upper and lower sides (see FIG. 4 or FIG. 8) on almost the entire surface.

  Next, FIG. 8 shows a D-D ′ cross section of FIG. 7. As shown in FIG. 8, a P + type collector region 18 and an N type buffer region 19 are formed in the semiconductor region of the back surface 1 b of the semiconductor chip 2 so as to be in contact with the top and bottom, and on the back surface 1 b of the semiconductor chip 2. The metal collector electrode 17 is formed. That is, as described above, the N-type buffer region 19 is provided in the N-type drift region 20 inside thereof so as to be in contact with the P + type collector region 18. A crystal defect region 41 is provided along the N-type buffer region 19 in the vicinity of the boundary (the boundary between the N-type buffer region 19 and the N-type drift region 20) and in the vicinity of the N-type drift region 20. Further, an N-type field stop region 42 having a higher concentration is provided in the N − -type drift region 20 on the first main surface side so as to extend along the crystal defect region 41. Yes.

  An N-type hole barrier region 24 is arranged in this order from the bottom in the N − type drift region 20 (surface side semiconductor region of the semiconductor substrate) on the surface 1a (first main surface) side of the semiconductor chip 2 in the linear active cell region 40a. (First conductivity type hole barrier region), P type body region 15 and N + type emitter region 12 are provided. An interlayer insulating film 26 is formed on the surface 1a of the semiconductor chip 2, and a contact trench 11 (or contact hole) extending inside the semiconductor substrate is formed in the interlayer insulating film 26 portion in the linear active cell region 40a. A P + type body contact region 25 and a P + type latch-up prevention region 23 are provided from the top in the bottom semiconductor region such as the contact groove 11. The P-type body region 15 and the N + -type emitter region 12 are connected to the metal emitter electrode 8 provided on the interlayer insulating film 26 via the contact groove 11 and the like.

  Here, the N-type hole barrier region 24 is a barrier region for preventing holes from flowing into the passage from the N− type drift region 20 to the N + type emitter region 12, and the impurity concentration thereof is N + type emitter region. It is lower than 12 and higher than the N − type drift region 20. Due to the presence of the N-type hole barrier region 24, holes accumulated in the linear inactive cell region 40i are directed to the emitter passage (from the N− type drift region 20 to the P + type body contact region 25) of the linear active cell region 40a. It is possible to effectively prevent entry into the passage.

  In contrast, in the linear inactive cell region 40i, the N − type drift region 20 (the surface side semiconductor region of the semiconductor substrate) on the surface 1a (first main surface) side of the semiconductor chip 2 is sequentially arranged from the bottom. A P-type floating region 16 and a P-type body region 15 are provided. The depth of the P-type floating region 16 is deeper than the depth of the trench 21, and is distributed so as to cover the lower end portion of the trench 21.

  Here, in order to illustrate the device structure more specifically, an example of main dimensions of each part of the device (see FIGS. 8 and 4) is shown. That is, the width Wa of the linear active cell region is about 2.3 micrometers, and the width Wi of the linear inactive cell region is about 6 micrometers (the width Wa of the linear active cell region is the linear inactive cell). It is desirable that the width is smaller than the width Wi of the region, and the value of Wi / Wa is particularly preferably in the range of 2 to 3, for example. The contact width is about 0.5 μm, the trench width is about 0.7 μm (particularly less than 0.8 μm is particularly suitable), the trench depth is about 3 μm, and an N + type emitter. The depth of the region 12 is about 250 nm. Further, the depth of the P-type body region 15 (channel region) is about 0.8 μm, the depth of the P + type latch-up prevention region 23 is about 1.4 μm, and the depth of the P-type floating region 16. Is about 4.5 micrometers. The N-type buffer region 19 has a thickness of about 1.5 micrometers, the P + type collector region has a thickness of about 0.5 micrometers, and the N-type field stop region 42 has a thickness of about 10 micrometers. The position is about 50 micrometers from the substrate surface (in the case of a withstand voltage of about 600 volts). The thickness of the semiconductor substrate 2 is about 60 micrometers (here, an example with a breakdown voltage of about 600 volts is shown). Note that the thickness of the semiconductor substrate 2 strongly depends on the required breakdown voltage. Therefore, for a withstand voltage of 1200 volts, it is about 120 micrometers, for example, and for a withstand voltage of 400 volts, it is about 40 micrometers, for example. Needless to say, the dimensions of each region in the thickness direction of the chip are basically the same in both the cell region and the periphery of the chip.

  In the following example and the example in section 2, the dimensions of the corresponding parts are substantially the same as those shown here, and therefore the description will not be repeated.

  Such a trench gate type IGBT is advantageous in that the on-resistance is extremely low as compared with the planar type.

4). Description of surface device formation process and the like related to the IGBT according to the embodiment of the present application (mainly FIGS. 9 to 25)
In this section, an example of a manufacturing method for the device structure described in Section 3 is shown. In the following description, the cell region 10 will be mainly described. For the peripheral portion and the like, reference is made to FIGS. 3 to 5 as necessary.

  In this section and the next section, for the sake of brevity, in principle, only the process related to the cell region will be described, and the process related to the chip periphery (the description related to the chip peripheral part of the same manufacturing process) will be described separately in section 18. Run in

  FIG. 9 is a device sectional view in the manufacturing process (hole barrier region introducing step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 10 is a device sectional view in the manufacturing process (P-type floating region introduction step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 11 is a device sectional view in the manufacturing process (trench processing hard mask film forming step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 12 is a device sectional view in the manufacturing process (trench hard mask processing step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 13 is a device sectional view in the manufacturing process (trench hard mask processing resist removal step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the embodiment of the present application. FIG. 14 is a device sectional view in the manufacturing process (trench processing step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 15 is a device sectional view in the manufacturing process (trench processing hard mask removal step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 16 is a device sectional view in the manufacturing process (stretch diffusion and gate oxidation step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 17 is a device sectional view in the manufacturing process (gate polysilicon film forming step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 18 is a device sectional view in the manufacturing process (gate polysilicon etch-back step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 19 is a device sectional view in the manufacturing process (gate oxide film etchback step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 20 is a device sectional view in the manufacturing process (P-type body region and N + type emitter region introducing step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the embodiment of the present application. . 21 is a device sectional view in the manufacturing process (interlayer insulating film forming step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 22 is a device sectional view in the manufacturing process (contact hole forming step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 23 is a device sectional view in the manufacturing process (substrate etching step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 24 is a device cross section during the manufacturing process (P + type body contact region and P + type latch-up prevention region introducing step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. FIG. 25 is a device sectional view in the manufacturing process (surface metal film forming step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. Based on these, the surface device formation process and the like related to the IGBT according to the embodiment of the present application will be described.

First, a 200φ wafer (150φ, 100φ, 300φ, 450φ, for example, having a phosphorus concentration of about 2 × 10 ¹⁴ / cm ³ , for example, a resistivity of about 65 Ωcm, for example, a resistivity of about 60 Ωcm to 70 Ωcm) is particularly suitable. Etc.) may be prepared. Here, for example, a wafer by FZ (Floating Zone) method is most suitable, but a wafer by CZ (Czochralski) method may be used. This is because a wafer having a high resistivity is more easily obtained by the FZ method. Since the resistivity of the semiconductor substrate strongly depends on the withstand voltage, the case of a withstand voltage of 600 volts and a withstand voltage of 1200 volts is shown as an example. That is, at a withstand voltage of 600 volts, as described above, the resistivity is, for example, about 65 Ωcm, and the range is generally preferably 50 Ωcm or more and less than 90 Ωcm, and considering mass productivity, 60 Ωcm or more, More preferably less than 80 Ωcm. On the other hand, at a withstand voltage of 1200 volts, as described above, the resistivity is, for example, about 100 Ωcm, and as a range, a range of 90 Ωcm or more and less than 150 Ωcm is generally a preferable range. More preferably less than about 120 Ωcm.

Next, as shown in FIG. 9, an N-type hole barrier region introduction resist film 31 is formed on the entire surface 1a (first main surface) of the semiconductor wafer 1 by coating or the like, and is performed by normal lithography. Patterning. Using the patterned N-type hole barrier region introducing resist film 31 as a mask, for example, by ion implantation, the semiconductor substrate 1s (N− type single crystal silicon substrate) on the surface 1a (first main surface) side of the semiconductor wafer 1 is used. An N-type hole barrier region 24 is formed by introducing N-type impurities therein. As ion implantation conditions at this time, for example, ion species: phosphorus, dose amount: about 6 × 10 ¹² / cm ² , and implantation energy: about 80 KeV can be exemplified as preferable ones. Thereafter, the resist film 31 that has become unnecessary is removed by ashing or the like.

Next, as shown in FIG. 10, a P-type floating region introducing resist film 37 is formed on almost the entire surface 1a of the semiconductor wafer 1 by coating or the like and patterned by ordinary lithography. Using the patterned P-type floating region introducing resist film 37 as a mask, P-type impurities are introduced into the semiconductor substrate 1s on the surface 1a (first main surface) side of the semiconductor wafer 1, for example, by ion implantation. Thus, the P-type floating region 16 is formed. As ion implantation conditions at this time, for example, ion species: boron, dose amount: about 3.5 × 10 ¹³ / cm ² , and implantation energy: about 75 KeV can be exemplified as preferable ones. Thereafter, the resist film 37 that has become unnecessary is removed by ashing or the like. When the P-type floating region 16 is introduced, the cell peripheral junction region 35 of FIG. 3 is also introduced at the same time.

  Next, as shown in FIG. 11, a hard mask film 32 for trench formation such as a silicon oxide insulating film (for example, by CVD (Chemical Vapor Deposition) or the like is formed on almost the entire surface 1a of the semiconductor wafer 1 by, for example, CVD. A thickness of about 450 nm) is formed.

  Next, as shown in FIG. 12, a resist film 33 for trench hard mask film processing is formed on almost the entire surface 1a of the semiconductor wafer 1 by coating or the like, and is patterned by ordinary lithography. Using the patterned trench hard mask film processing resist film 33 as a mask, the trench forming hard mask film 32 is patterned by, for example, dry etching.

  Thereafter, as shown in FIG. 13, the resist film 33 that has become unnecessary is removed by ashing or the like.

Next, as shown in FIG. 14, the trench 21 is formed by anisotropic dry etching, for example, using the patterned trench forming hard mask film 32. As a gas system for this anisotropic dry etching, for example, a Cl ₂ / O ₂ system gas can be exemplified as a suitable one.

  After that, as shown in FIG. 15, the trench forming hard mask film 32 that has become unnecessary is removed by wet etching using, for example, a hydrofluoric acid based silicon oxide film etching solution.

  Next, as shown in FIG. 16, extended diffusion (for example, about 1200 degrees Celsius and about 30 minutes) is performed on the P-type floating region 16 and the N-type hole barrier region 24. Subsequently, a gate insulating film 22 (for example, a thickness of about 120 nm) is formed on the surface 1a of the semiconductor wafer 1 and almost the entire inner surface of the trench 21 by, for example, thermal oxidation.

  Next, as shown in FIG. 17, phosphorus is doped on the surface 1a of the semiconductor wafer 1 on the gate insulating film 22 and almost the entire inner surface of the trench 21 by, for example, CVD so as to fill the trench 21. A doped polysilicon (Doped Poly-Silicon) film 27 is formed (for example, a thickness of about 600 nm).

Next, as shown in FIG. 18, the trench gate electrode 14 is formed in the trench 21 by etching back the polysilicon film 27 by dry etching or the like (for example, gas system is SF ₆ or the like).

  Next, as shown in FIG. 19, the gate insulating film 22 outside the trench 21 is removed, for example, by wet etching using a hydrofluoric acid silicon oxide film etchant or the like.

  Next, as shown in FIG. 20, a relatively thin silicon oxide film 38 for subsequent ion implantation (see FIG. 61, thickness) is formed on almost the entire surface 1a of the semiconductor wafer 1 by, for example, thermal oxidation or CVD. For example, about 20 nm). Next, as a contact etching stop film 51 (see FIG. 64), a silicon nitride film (having a thickness of, for example, about 100 nm) is formed by CVD, for example, on almost the entire surface 1a of the semiconductor wafer 1. As a result, a laminated film 58 of a thin silicon oxide film for lower layer ion implantation and an upper layer etching stop film is formed.

Subsequently, a resist film for introducing a P-type body region is formed on the surface 1a of the semiconductor wafer 1 by ordinary lithography. Using this P-type body region introduction resist film as a mask, P-type body region 15 is formed by introducing P-type impurities into almost the entire surface of cell region 10 and other necessary portions by, for example, ion implantation. As ion implantation conditions at this time, for example, ion species: boron, dose amount: about ² × 10 ¹³ / cm ² , and implantation energy: about 75 KeV can be exemplified as preferable ones. Thereafter, the unnecessary P-type body region introduction resist film is removed by ashing or the like.

Further, an N + type emitter region introduction resist film is formed on the surface 1a of the semiconductor wafer 1 by ordinary lithography. Using this N + type emitter region introduction resist film as a mask, N + type impurities are introduced into almost the entire upper surface of the P type body region 15 of the linear active cell region 40a by, for example, ion implantation, thereby forming an N + type impurity. An emitter region 12 is formed. As ion implantation conditions at this time, for example, ion species: arsenic, dose amount: about 5 × 10 ¹⁵ / cm ² , and implantation energy: about 80 KeV can be exemplified as preferable ones. Thereafter, the resist film for introducing an N + type emitter region that has become unnecessary is removed by ashing or the like.

  Next, as shown in FIG. 21, a PSG (Phosphosilicate Glass) film, for example, is formed as the interlayer insulating film 26 on the almost entire surface 1a of the semiconductor wafer 1 by, for example, CVD (thickness is). For example, about 600 nm). As the material of the interlayer insulating film 26, in addition to the PSG film, a BPSG (Borophosphosilicate Glass) film, an NSG (Non-doped Silicate Glass) film, an SOG (Spin-On-Glass) film, or a composite film thereof is preferable. Can be exemplified.

Next, as shown in FIG. 22, a contact groove forming resist film 28 is formed on the surface 1a of the semiconductor wafer 1 on the interlayer insulating film 26 by ordinary lithography. Subsequently, the contact groove 11 (or contact hole) is formed by, for example, anisotropic dry etching or the like (gas system is, for example, Ar / CHF ₃ / CF ₄ or the like).

Thereafter, as shown in FIG. 23, the resist film 28 that has become unnecessary is removed by ashing or the like. Subsequently, the contact groove 11 (or contact hole) is extended into the semiconductor substrate by, for example, anisotropic dry etching. As a gas system at this time, for example, a Cl ₂ / O ₂ system gas can be exemplified as a suitable one.

Next, as shown in FIG. 24, for example, a P + type body contact region 25 is formed by ion implantation of a P type impurity through the contact groove 11. Here, as ion implantation conditions, for example, ion species: BF ₂ , dose amount: about 5 × 10 ¹⁵ / cm ² , and implantation energy: about 80 KeV can be exemplified as preferable examples.

Similarly, for example, a P + type latch-up prevention region 23 is formed by ion implantation of a P type impurity through the contact groove 11. Here, as ion implantation conditions, for example, ion species: boron, dose: about 5 × 10 ¹⁵ / cm ² , and implantation energy: about 80 KeV can be exemplified as preferable examples.

  Next, as shown in FIG. 25, for example, an aluminum-based electrode film 8 (which becomes the metal emitter electrode 8) is formed by sputtering or the like. Specifically, for example, the following procedure is executed. First, a TiW film (for example, a thickness of about 200 nm) is formed as a barrier metal film on almost the entire surface 1a of the semiconductor wafer 1 by, for example, sputtering film formation (many portions of titanium in the TiW film are Subsequent heat treatment moves to the silicon interface to form silicide and contributes to improvement of contact characteristics, but these processes are complicated and are not shown in the drawing).

Subsequently, for example, silicide annealing is performed for about 10 minutes in a nitrogen atmosphere at about 600 degrees Celsius. Subsequently, aluminum is used as a main component (for example, several percent of silicon is added, and the rest is aluminum) by sputtering, for example, so as to fill the contact groove 11 almost over the entire surface of the barrier metal film. For example, a thickness of about 5 micrometers is formed. Subsequently, the metal emitter electrode 8 made of an aluminum metal film and a barrier metal film is patterned by normal lithography (for example, Cl ₂ / BCl ₃ as a dry etching gas system). Furthermore, as a final passivation film, for example, an organic film (for example, a thickness of about 2.5 micrometers) or the like containing polyimide as a main component is applied to almost the entire device surface 1a of the wafer 1, and by normal lithography, The emitter pad 9 and the gate pad 6 shown in FIG. 6 are opened.

  As a result, the front surface device formation process is completed, and the process proceeds to a process such as a back surface (a process related to the back surface side structure including processing from the front surface side).

5. Description of backside device formation process and the like related to the IGBT of the embodiment of the present application (mainly FIGS. 26 to 30)
In this section, following the section 4, a back surface device formation process (manufacturing process regarding the structure on the back side) and the like related to the IGBT according to the embodiment of the present application will be described.

  FIG. 26 is a device sectional view in the manufacturing process (N-type field stop region introduction step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 27 is a device sectional view in the manufacturing process (back grinding step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 28 is a device sectional view in the manufacturing process (N-type buffer region introduction step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 29 is a device sectional view in the manufacturing process (P + type collector region introduction step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. 30 is a device sectional view in the manufacturing process (metal collector electrode formation step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. Based on these, the back surface device formation process regarding the IGBT of the one embodiment of the present application will be described.

As shown in FIG. 26, for example, by implanting protons (hydrogen ions) from the surface 1a side of the wafer 1 (high energy proton irradiation), for example, the N − type drift region 20 at a position of about 50 μm from the substrate surface. An N-type field stop region 42 having a thickness of about 10 micrometers is introduced almost on the entire surface. Here, as irradiation conditions, for example, ion species (implanted particles): protons (hydrogen ions), implantation method: substantially vertical implantation, implantation energy: about 4.3 MeV, single dose: about 1 × 10 ¹⁵ / cm ² (Half width, for example, about 7.5 micrometers), the number of times of implantation: about 2 can be exemplified as a suitable one. For example, an industrial cyclotron can be used as the driving device. The implanted particles may be helium ions or the like in addition to hydrogen ions.

  Further, proton irradiation can be performed not only from the front surface 1a side of the wafer 1 but also from the back surface 1b side. In this case, it is necessary to consider the range of protons in silicon (normally about several tens of micrometers to several hundreds of micrometers although it varies depending on the configuration of the apparatus and charged particle energy). Considering the controllability of irradiation, it is efficient to set the depth of the N-type field stop region 42 from the back surface of the wafer during irradiation to the same level as in the case of proton irradiation from the surface 1a side. Therefore, when proton irradiation is performed from the back side of the wafer, it is effective to perform back grinding preliminarily and perform preliminary back grinding to a thickness of about 50 micrometers larger than the final target wafer thickness. As described above, the backside irradiation method has a merit that no damage is left on the substrate or the like because the portion damaged by the irradiation is removed by the main backside grinding after the irradiation. On the other hand, the front surface irradiation method has an advantage that an additional back grinding process or the like is unnecessary.

  Subsequently, for example, proton activation annealing is performed at about 420 degrees Celsius (the range is about 400 degrees Celsius to 500 degrees Celsius) for about one hour.

  Next, as shown in FIG. 27, a back grinding process (chemical etching or the like for removing damage on the back surface is also performed if necessary) is performed on the back surface 1b of the wafer 1 in the drawing. The film is thinned by grinding or the like to the back grinding position 43 indicated by the broken line. Here, the final thickness of the wafer 1 is, for example, an original wafer thickness of about 800 micrometers (preferably about 1000 to 450 micrometers), for example, 200 to 30 micrometers. Thin film to the extent. For example, if the withstand voltage is about 600 volts, the final thickness is about 60 micrometers (the lower limit is defined by the required withstand voltage. For example, at a withstand voltage of 1200 volts, the final thickness is about 120 micrometers). is there.

Next, as shown in FIG. 28, for example, ion implantation is performed on almost the entire surface of the thinned wafer 1 from the back surface 1b side, so that the surface region of the back surface 1b of the wafer 1 (before introduction) The N-type buffer region 19 is introduced into the N-type drift region 20). Here, as ion implantation conditions, for example, ion species: phosphorus, implantation method: almost vertical implantation, implantation energy: about 350 KeV, single dose: about 7 × 10 ¹² / cm ² , number of implantation: one time is preferable It can be illustrated as a thing.

Next, as shown in FIG. 29, for example, ion implantation is performed on the substantially entire surface from the back surface 1b side of the wafer 1 to thereby introduce the surface region of the back surface 1b of the wafer 1 (introduction of the N-type buffer region 19). Previously, a P + collector region 18 is introduced into the N− drift region 20). Here, as ion implantation conditions, for example, ion species: boron, implantation method: almost vertical implantation, implantation energy: about 40 KeV, one dose amount: about 1 × 10 ¹³ / cm ² , implantation number: one time is preferable. It can be illustrated as a thing.

Subsequently, activation annealing is performed on the P + type collector region 18 on almost the entire back surface 1b of the wafer 1 (the activation rate is, for example, about 40%, and a preferable range is about 30% to 64%). Here, as annealing conditions (laser irradiation conditions), for example, annealing method: laser irradiation from the back surface 1b side of the wafer 1, wavelength: 527 nm, pulse width: about 100 ns, energy density: about 1.8 J / cm ² , Irradiation method: two-pulse method, delay time of both pulses: about 500 ns, pulse overlap rate: about 66% can be exemplified as preferable examples.

  By these processes, N between the N-type field stop region 42 and the N-type buffer region 19 from the vicinity of the boundary (the boundary between the N-type buffer region 19 and the N− type drift region 20) along the N-type buffer region 19. The crystal defect due to the back surface ion implantation remains in the portion of the − type drift region 20 adjacent to the boundary, and the crystal defect region 41 is formed.

  Next, as shown in FIG. 30, the metal collector electrode 17 is formed on almost the entire back surface 1b of the semiconductor wafer 1 by, for example, sputtering film formation (see FIG. 33 and its description for specific details). ). Thereafter, it is divided into chip regions of the semiconductor wafer 1 by dicing or the like, and sealed in a package as necessary, thereby completing the device.

6). Description of Modification (Full Active Cell Region) of IGBT Cell Structure of One Embodiment of the Present Application (Mainly FIGS. 31 and 32)
In the description of the sections 2 to 5, the IE type trench gate IGBT is mainly described as an example. However, each embodiment of the present application has other unit cell structures, for example, a unit of a full active type trench gate IGBT. Needless to say, the present invention can also be applied to a cell structure. Therefore, in this section, the unit cell structure of the fully active trench gate IGBT will be described.

  FIG. 31 is an enlarged top view (corresponding to FIG. 7 in section 3) of the cell region internal cutout region R3 of FIG. 6 regarding a modification (full active cell region) of the IGBT cell structure of the one embodiment of the present application. . 32 is a device cross-sectional view (corresponding to FIG. 8 of section 3) corresponding to the D-D ′ cross section of FIG. 31. Based on these, a modified example (full active cell region) of the cell structure of the IGBT according to the embodiment of the present application will be described.

  As shown in FIG. 31, the cell region 10 is mainly composed of linear active cell regions 40a repeatedly arranged in the horizontal direction (the entire region of the linear unit cell region 40 is a linear active cell region 40a). . A trench gate electrode 14 is disposed between the linear unit cell regions 40, and a linear contact groove 11 (or contact hole) is disposed in the center of the linear unit cell region 40. Linear N + type emitter regions 12 are provided in the linear unit cell regions 40 on both sides of the contact groove 11.

  Next, FIG. 32 shows a D-D ′ cross section of FIG. 31. As shown in FIG. 32, in the semiconductor region of the back surface 1b of the semiconductor chip 2, a P + type collector region 18 and an N type buffer region 19 are formed so as to be in contact with the top and bottom, and on the back surface 1b of the semiconductor chip 2. The metal collector electrode 17 is formed. That is, as described above, the N-type buffer region 19 is provided in the N-type drift region 20 inside thereof so as to be in contact with the P + type collector region 18. Further, a crystal defect region 41 is provided along the N-type buffer region 19 and over the N − -type drift region 20 in the vicinity of the outside, and further along the crystal defect region 41, Also, the N-type drift region 20 on the first main surface side is provided with an N-type field stop region 42 having a higher concentration than this.

  In the linear unit cell region 40, an N-type hole barrier region 24 is formed in order from the bottom on the N − type drift region 20 (surface side semiconductor region of the semiconductor substrate) on the surface 1 a (first main surface) side of the semiconductor chip 2. , A P-type body region 15 and an N + -type emitter region 12 are provided. An interlayer insulating film 26 is formed on the surface 1a of the semiconductor chip 2, and a contact trench 11 (or contact hole) extending inside the semiconductor substrate is formed in the interlayer insulating film 26 portion in the linear unit cell region 40. A P + type body contact region 25 and a P + type latch-up prevention region 23 are provided from the top in the bottom semiconductor region such as the contact groove 11. The P-type body region 15 and the N + -type emitter region 12 are connected to the metal emitter electrode 8 provided on the interlayer insulating film 26 via the contact groove 11 and the like.

  Here, the N-type hole barrier region 24 is a barrier region for preventing holes from flowing into the passage from the N− type drift region 20 to the N + type emitter region 12, and the impurity concentration thereof is N + type emitter region. It is lower than 12 and higher than the N − type drift region 20. The existence of the N-type hole barrier region 24 effectively allows holes accumulated in the N− type drift region 20 to enter the emitter passage (passage from the N− type drift region 20 to the P + type body contact region 25). Can be blocked. Needless to say, the N-type hole barrier region 24 is not essential.

  As described above, the full active cell region 10 has a structure without the linear inactive cell region 40i in FIG. 4, and the entire linear unit cell region 40 in FIG. 3 is the linear active cell region. 40a.

7). Description of Modified Example (Aluminum Doped Contact) of Backside Detailed Structure of IGBT of One Embodiment of the Present Application (Mainly FIG. 33)
The examples in this section are applicable to all other examples (including diodes) other than this section. Needless to say, the present invention can also be applied to IGBTs having other general surface-side structures.

  In this section, for convenience of explanation, the device structure will be described according to the example in Section 3, and the process will be briefly described with reference to Section 5.

  In the following, the IE trench gate IGBT will be specifically described. However, the back surface structure is not limited to the IE type IGBT or the trench gate IGBT (full active trench gate IGBT), but other forms. Needless to say, the present invention can also be applied to other IGBTs (for example, planar IGBTs).

  FIG. 33 is a local detailed cross-sectional view of a device back surface for explaining a device structure of a modified example (aluminum doped contact) of the back surface detailed structure of the IGBT according to the embodiment of the present application and a manufacturing method thereof.

FIG. 33 shows an enlarged cross-sectional view of the back side of the semiconductor chip 2 in FIG. 8 and the vicinity thereof (a schematic view of the structure in the vicinity of the back surface in the thickness direction of the chip). As shown in FIG. 33, a relatively thin P-type semiconductor region (for example, a thickness of about 0.04 to 0.1 micrometers) is formed in the semiconductor region at the lower end of the P + type collector region 18 on the back surface side of the semiconductor substrate 2. That is, an aluminum doped region 30 (second conductivity type high concentration collector contact region) is provided. This impurity concentration (for example, about 1 × 10 ¹⁹ / cm ³ ) is higher than the impurity concentration of the P + type collector region 18. A metal collector electrode 17 is formed on the back surface 1 b of the semiconductor substrate 2 in contact with the aluminum doped region 30. For example, the metal collector electrode 17 has the following configuration from the side closer to the semiconductor substrate 2. That is, an aluminum back metal film 17a (for example, about 600 nm thick), a titanium back metal film 17b (for example, about 100 nm thick), and a nickel back metal film 17c (for example, 600 nm thick) that are impurity sources of the aluminum doped region 30. And a gold back metal film 17d (for example, a thickness of about 100 nm).

  Next, the production method will be briefly described. In the process of FIG. 30 in section 5, that is, during the sputtering film formation, the aluminum back metal film 17a, the titanium back metal film 17b, the nickel back metal film 17c, and the gold back metal film 17d are sequentially formed by sputtering. The heat generated at this time introduces aluminum into the silicon substrate, and the aluminum doped region 30 is formed. After that, when divided into chip regions of the semiconductor wafer 1 by dicing or the like, it becomes as shown in FIG. 8 (the detailed structure is not clearly shown in FIG. 8).

  In each of the embodiments of the present application, holes are accumulated on the emitter side in the on state to promote electron injection. On the other hand, the PN diode on the back collector side is a diode having low injection efficiency to reduce switching loss. Here, in order to form a backside diode with low injection efficiency, the ratio of the carrier concentration Qp of the P + type collector region 18 to the carrier concentration Qn of the N type field stop region 19 (hereinafter referred to as “carrier concentration ratio”), that is, ( It is effective to reduce Qp / Qn). However, for this reason, if the carrier concentration Qp of the P + type collector region 18 is lowered too much, the characteristics of the back surface metal contact deteriorate. Therefore, in this example, an aluminum doped region 30 having a higher impurity concentration than the P + type collector region 18 introduced from the aluminum film on the back surface is provided. As a carrier concentration ratio, for example, about 1.5 (as a range, for example, about 1.1 to 4) can be exemplified as a suitable one.

  In this section, the back surface metal structure and the like (including the contact region) suitable for the case where the PN diode on the back surface collector side is particularly desired to have a low injection efficiency are exemplified. However, as the back surface metal structure and the like, the aluminum doped region 30 and the like Needless to say, even if the aluminum back surface metal film 17a is not provided, it may be formed of a combination of other metal films.

8). Description of Modification (Epitaxial Process) of Surface Device Formation Process Related to IGBT of One Embodiment of the Present Application (Mainly FIGS. 34 and 35)
While sections 4 and 5 described non-epitaxy processes that do not use an epitaxy process, the various devices described herein can also be fabricated by various epitaxy processes that use an epitaxy process. In this section, an example of an epitaxy process corresponding to sections 4 and 5 is described.

  FIG. 34 is a device sectional view in the manufacturing process (N-type field stop region introduction step) corresponding to FIG. 8 for describing the modification (epitaxial process) of the surface device formation process related to the IGBT according to the embodiment of the present invention. It is. FIG. 35 is a device cross section in the manufacturing process (N-type silicon epitaxial region forming step) corresponding to FIG. 8 for describing the modification (epitaxial process) of the surface device forming process related to the IGBT according to the embodiment of the present invention. FIG. Based on these, a modification (epitaxial process) of the surface device formation process related to the IGBT of the one embodiment of the present application will be described.

First, an N− type silicon single crystal (for example, wafers of various diameters such as 150φ, 100φ, 300φ, 450φ, etc.) with a phosphorus concentration of about 2 × 10 ¹⁴ / cm ³ and a resistivity of 22 Ωcm to 30 Ωcm may be prepared. Here, for example, a wafer by the CZ (Czochralski) method is most suitable, but a wafer by the FZ (Floating Zone) method may be used. This is because the CZ crystal is more economical.

Next, as shown in FIG. 34, for example, ion implantation is performed on almost the entire surface from the surface 1a side of the wafer 1 to thereby form a semiconductor surface region (N− type drift region 20 on the surface 1a of the wafer 1). An N-type field stop region 42 is introduced into the N-type single crystal silicon substrate 1s to be formed. Here, as ion implantation conditions, for example, ion species: phosphorus, implantation method: almost vertical implantation, implantation energy: about 75 KeV, one dose amount: about 5 × 10 ¹¹ / cm ² , implantation number: one time is preferable It can be illustrated as a thing.

  Subsequently, activation annealing (for example, 1200 degrees Celsius, about 30 minutes) is performed on the N-type field stop region 42 as necessary.

  Next, as shown in FIG. 35, by epitaxial growth on the surface 1a side of the wafer 1, assuming that the N-type silicon epitaxial region 1e (withstand voltage of about 600 volts) has a thickness of, for example, about 50 micrometers and a resistivity of For example, about 22 Ωcm.

  Thereafter, the processes of FIGS. 9 to 25 described in the section 4 are executed, and the processes of FIGS. 27 to 30 described in the section 5 are further executed.

  Such a process has the advantage that the use of an industrial cyclotron or the like is unnecessary. On the other hand, the non-epitaxy processes of section 4 and section 5 have an advantage that an expensive epitaxy process can be avoided.

9. Basic example (PIN diode having crystal defect region and intermediate field stop region) of power system diode according to one embodiment of the present application, Modified example 1 (an example in which an N-type thick film cathode region is applied) and Modified example 2 (N-type) Example of application of thick film cathode region & high concentration cathode region (mainly FIG. 36, FIG. 37, FIG. 77 and FIG. 78)
In sections 2 to 8, the basic concept of the main embodiment of the present application is mainly applied to the IGBT. However, in this section 9 to section 13, it is applied to the diode. Is mainly explained.

  In this section, the entire structure of a PIN diode chip having a crystal defect region and an intermediate field stop region and the structure of a main device region (basic example, modified examples 1 and 2) will be described. This is because a PIN diode generally does not have a repetitive structure, and a main PN junction has only a main part (center part) and an end part. Therefore, here, a description will be given by extracting a portion that is a main portion of the main PN junction and corresponds to a unit cell portion of the cell region in the case of the cell structure. The device structures described in sections 11 and 12 generally have a repeated structure as in the case of IGBTs, so that unit cell portions are extracted and described as in the case of IGBTs.

  The peripheral structure is almost the same as that described in FIGS. 3 and 4 except that there is no dummy cell as described in FIG.

(1) Description of basic example (PIN diode having crystal defect region and intermediate field stop region) (mainly FIG. 36 and FIG. 37):
36 is an overall top view of the diode chip corresponding to FIG. 6 (corresponding to FIG. 6 in section 3) relating to a basic example (a PIN diode having a crystal defect region and an intermediate field stop region) of a power diode according to an embodiment of the present application. ). FIG. 37 is a device cross-sectional view (corresponding to FIG. 8 in section 3) of the main device region corresponding to the FF ′ cross-section of FIG. Based on these, a basic example of a power diode according to an embodiment of the present application (a PIN diode having a crystal defect region and an intermediate field stop region) will be described.

  As shown in FIG. 36, an annular metal guard ring 3m made of, for example, an aluminum wiring layer is provided on the outer periphery of the upper surface 1a of the PIN diode device chip 2, and an annular metal guard ring 3m is provided on the inner side thereof. Metal field plate 4m (for example, composed of the same aluminum-based wiring layer as before) is provided. As in FIG. 6, the polysilicon field plate or the like is not shown in this figure (see FIGS. 4, 46, 84, etc.). A main PN junction region 10 (P-type anode region 46) is provided inside the metal field plate 4m and in the main part of the inner region of the upper surface 1a of the chip 2, and on the main PN junction region 10, For example, the metal anode electrode 44 composed of the same aluminum-based wiring layer as before is covered up to the outside. A central portion of the metal anode electrode 44 is an anode pad 45 for connecting a bonding wire or the like. The metal field plate 4m and the metal anode electrode 44 are connected to each other by, for example, a metal field plate-metal anode electrode connecting portion 4d made of the same aluminum-based wiring layer or the like.

  Next, FIG. 37 shows an F-F ′ cross section of the cell region internal cutout region R <b> 3 of FIG. 36. As shown in FIG. 37, an N-type cathode region 47 having a concentration higher than that of the N − -type drift region 20 is formed in the semiconductor region (N − -type drift region 20) of the back surface 1b of the semiconductor chip 2. A metal cathode electrode 17 is formed on the back surface 1 b of the chip 2. A crystal defect region 41 is provided along the N-type cathode region 47 and over the N − type drift region 20 in the vicinity of the outside, and further along the crystal defect region 41, Also, the N-type drift region 20 on the first main surface side is provided with an N-type field stop region 42 having a higher concentration than this.

  In the main PN junction region 10, a P-type anode region 46 is provided in the N − -type drift region 20 (surface-side semiconductor region of the semiconductor substrate) on the surface 1 a (first main surface) side of the semiconductor chip 2. An anode metal electrode 44 is formed on the surface 1a of the semiconductor chip 2, and the anode metal electrode 44 is connected to a P-type anode region 46 (ohmic contact).

(2) Description of Modification 1 (example in which N-type thick film cathode region is applied) (mainly FIG. 77):
77 is a device cross-sectional view of the main junction main part of Modification 1 of the power diode of FIG. 37 (an example in which the N-type thick film cathode region is applied).

  This example corresponds to FIG. 49 when corresponding to the IGBT described in section 17. That is, an N-type thick film cathode region 61 is formed on the back surface side, and a crystal defect region 41 is provided at the lower end thereof.

  Note that the N-type thick film cathode region 61 is formed by, for example, ion implantation of impurities such as sulfur and selenium from the back surface of the wafer and an extension diffusion process in the non-epitaxy process as in the section 10. On the other hand, in the non-epitaxy process as in section 10, for example, the crystal defect region 41 is irradiated with high energy ions (proton irradiation, helium ion irradiation, etc.) from the front surface or the back surface of the wafer as described for the IGBT in FIG. It is possible to use defect formation due to the above. The above points are the same in the subsections (2) of the following sections 11 and 12.

(3) Description of Modification 2 (example in which N-type thick film cathode region & high concentration cathode region is applied) (mainly FIG. 78):
78 is a device cross-sectional view of the main junction main part of Modification 2 (an example in which the N-type thick film cathode region & high-concentration cathode region) of the power diode of FIG. 37 is applied.

  This example corresponds to FIG. 50 corresponding to the IGBT described in section 17. That is, an N-type thick film cathode region 61 is formed on the back side, a crystal defect region 41 is provided at the lower end thereof, and a high-concentration cathode region 67 is provided on the back side. The introduction of the high concentration cathode region 67 has an advantage that the crystal defect region 41 can be introduced during the activation annealing. The above points are the same in the subsections (3) of the following sections 11 and 12.

10. Description of a basic manufacturing process and the like (mainly FIGS. 38 to 43) regarding a basic example (a PIN diode having a crystal defect region and an intermediate field stop region) of the power diode according to the embodiment of the present application
This section describes a diode manufacturing process (non-epitaxy process) that corresponds to that described in sections 4 and 5 for the IGBT manufacturing method.

  FIG. 38 is a device sectional view in the manufacturing process (P-type anode region introduction step) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. FIG. 39 is a device sectional view in the manufacturing process (metal anode electrode formation step) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. FIG. 40 is a device sectional view in the manufacturing process (N-type field stop region introduction step) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. FIG. 41 is a device cross-sectional view during the manufacturing process (back grinding process) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. FIG. 42 is a device sectional view in the manufacturing process (N-type cathode region introduction step) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. FIG. 43 is a device sectional view in the manufacturing process (metal cathode electrode formation step) corresponding to FIG. 37 for illustrating the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. Based on these, a basic manufacturing process relating to a basic example (a PIN diode having a crystal defect region and an intermediate field stop region) of the power diode of the one embodiment of the present application will be described.

First, an N-type silicon single crystal (for example, a wafer having various diameters such as 150φ, 100φ, 300φ, 450φ, etc.) having a phosphor concentration of about 2 × 10 ¹⁴ / cm ³ and having a resistivity of 22 Ωcm to 30 Ωcm is prepared. Here, for example, a wafer by FZ (Floating Zone) method is most suitable, but a wafer by CZ (Czochralski) method may be used.

  Next, as shown in FIG. 38, the semiconductor on the surface 1a of the wafer 1 is ion-implanted from the surface 1a side of the wafer 1 into the entire surface of the main PN junction region 10 by, for example, P-type impurities such as boron. A P-type anode region 46 is introduced into the surface region (inside the N-type single crystal silicon substrate 1s to be the N-type drift region 20).

  Next, as shown in FIG. 39, the anode metal electrode 44 is formed on the surface 1 a of the wafer 1 on the P-type anode region 46 in the same manner as the metal emitter electrode 8 of the previous section 4.

  Next, as shown in FIG. 40, an N-type field stop region 42 is formed in the N−-type drift region 20 as in FIG.

  Next, as shown in FIG. 41, as in FIG. 27 in the previous section 5, back grinding is performed to thin the wafer.

Next, as shown in FIG. 42, an N-type cathode region 47 is formed on the second main surface side surface region of the N − -type drift region 20 in the same manner as the N-type buffer region 19 of FIG. Form. Here, as ion implantation conditions, for example, ion species: phosphorus, implantation method: almost vertical implantation, implantation energy: about 125 KeV, one dose amount: about 1 × 10 ¹⁵ / cm ² , implantation number: one time is preferable. It can be illustrated as a thing.

Here, as the activation annealing conditions (laser irradiation conditions), for example, annealing method: laser irradiation from the back surface 1b side of the wafer 1, wavelength: 527 nm, pulse width: about 100 ns, energy density: 1.8 J / Suitable examples include about cm ² , irradiation method: two-pulse method, delay time of both pulses: about 500 ns, and pulse overlap ratio: about 66%.

  Next, as shown in FIG. 43, the metal cathode electrode 17 and the like are formed on the back surface 1b of the wafer 1 in the same manner as in FIG. The metal cathode electrode 17 and the like may be as shown in FIG.

  Thereafter, it is divided into chip regions of the semiconductor wafer 1 by dicing or the like, and sealed in a package as necessary, thereby completing the device.

11. Modification 1 (MPS diode having a crystal defect region and an intermediate field stop region), Modification 2 (application example of an N-type thick film cathode region), and Modification 3 (N-type) of the power diode of the one embodiment of the present application Example of application of thick film cathode region & high concentration cathode region (mainly FIG. 44, FIG. 79 and FIG. 80)
In this section, Modification 1 to the diode structure described in Section 9 will be described. Since there is no essential difference with respect to the manufacturing method as described in Section 10, the description will not be repeated here in principle.

(1) Description of Modification 1 of Power System Diode (MPS Diode Having Crystal Defect Region and Intermediate Field Stop Region) (Mainly FIG. 44):
44 is a device cross section of a unit cell portion corresponding to the FF ′ cross section of FIG. 36 relating to Modification 1 (MPS diode having a crystal defect region and an intermediate field stop region) of the power diode of the one embodiment of the present application. FIG. Based on this, Modification 1 (MPS diode having a crystal defect region and an intermediate field stop region) of the power diode according to the embodiment of the present invention will be described.

  The unit cell region of the cell region 10 (FIG. 36) in this example generally has a circular P-type anode region 46 on the surface 1a of the semiconductor substrate 2 in the N − -type drift region 20 unlike the IGBT. The two-dimensional hexagonal close-packed lattice is distributed. Therefore, the P-type anode region 46 and the anode metal electrode 44 are in ohmic contact, but the portion without the P-type anode region 46 is a Schottky junction. The other structure is exactly the same as FIG.

(2) Description of Modification 2 (example applying N-type thick film cathode region) (mainly FIG. 79):
FIG. 79 is a device cross-sectional view of the main junction part of a further modification 2 (example in which the N-type thick film cathode region is applied) of the power diode of FIG.

  This example corresponds to FIG. 49 when corresponding to the IGBT described in section 17. That is, an N-type thick film cathode region 61 is formed on the back surface side, and a crystal defect region 41 is provided at the lower end thereof.

(3) Description of Modification 3 (example in which N-type thick film cathode region & high concentration cathode region is applied) (mainly FIG. 80):
FIG. 80 is a device cross-sectional view of the main junction part of a further modification 3 (an example in which an N-type thick film cathode region and a high concentration cathode region are applied) of the power diode of FIG.

  This example corresponds to FIG. 50 corresponding to the IGBT described in section 17. That is, an N-type thick film cathode region 61 is formed on the back side, a crystal defect region 41 is provided at the lower end thereof, and a high-concentration cathode region 67 is provided on the back side. The introduction of the high concentration cathode region 67 has an advantage that the crystal defect region 41 can be introduced during the activation annealing.

12 Modification 1 (SSD having a crystal defect region and an intermediate field stop region), Modification 2 (application example of N-type thick film cathode region), and Modification 3 (N-type thickness) of the power diode according to the embodiment of the present application. Example of application of membrane cathode region & high concentration cathode region) (mainly FIG. 45, FIG. 81 and FIG. 82)
In this section, Modification 2 to the diode structure described in Section 9 will be described. Since there is no essential difference with respect to the manufacturing method as described in Section 10, the description will not be repeated here in principle.

(1) Description of Modification 1 (SSD having a crystal defect region and an intermediate field stop region) (mainly FIG. 45):
FIG. 45 is a device cross-sectional view of a unit cell portion corresponding to the FF ′ cross section of FIG. 36 regarding Modification 1 (SSD having a crystal defect region and an intermediate field stop region) of the power diode according to the embodiment of the present application. It is. Based on this, Modification 1 (SSD having a crystal defect region and an intermediate field stop region) of the power diode according to the embodiment of the present invention will be described.

  This example is a shallow and thin impurity region (for example, doped with aluminum or the like as a P-type impurity) compared to the P-type anode region 46 for relaxing the electric field concentration in the vicinity of the Schottky junction of the MPS diode described in Section 11, That is, a P-type surface region 48 is added.

(2) Description of Modification 2 (example in which N-type thick film cathode region is applied) (mainly FIG. 81):
FIG. 81 is a device cross-sectional view of the main junction part of a further modification 2 (example in which the N-type thick film cathode region is applied) of the power diode of FIG.

  This example corresponds to FIG. 49 when corresponding to the IGBT described in section 17. That is, an N-type thick film cathode region 61 is formed on the back surface side, and a crystal defect region 41 is provided at the lower end thereof.

(3) Description of Modification 3 (example in which N-type thick film cathode region & high concentration cathode region is applied) (mainly FIG. 82):
FIG. 82 is a device cross-sectional view of the main junction part of a further modification 3 (an example in which an N-type thick film cathode region and a high concentration cathode region are applied) of the power diode of FIG.

  This example corresponds to FIG. 50 corresponding to the IGBT described in section 17. That is, an N-type thick film cathode region 61 is formed on the back side, a crystal defect region 41 is provided at the lower end thereof, and a high-concentration cathode region 67 is provided on the back side. The introduction of the high concentration cathode region 67 has an advantage that the crystal defect region 41 can be introduced during the activation annealing.

13. Description of modification of diode manufacturing process (refer mainly to FIG. 34 and FIG. 35)
In this section, the epitaxy process for the diode is described with reference to the manufacturing process for the IGBT (Section 8).

As in section 8, first, it may be a wafer of various diameters such as an N-type silicon single crystal (for example, a phosphorus concentration of about 2 × 10 ¹⁴ / cm ³ and a resistivity of 22 Ωcm to 30 Ωcm) such as 150φ, 100φ, 300φ, and 450φ. Prepare). Here, for example, a wafer by the CZ (Czochralski) method is most suitable, but a wafer by the FZ (Floating Zone) method may be used.

Next, as shown in FIG. 34, for example, ion implantation is performed on almost the entire surface from the surface 1a side of the wafer 1 to thereby form a semiconductor surface region (N− type drift region 20 on the surface 1a of the wafer 1). An N-type field stop region 42 is introduced into the N-type single crystal silicon substrate 1s to be formed. Here, as ion implantation conditions, for example, ion species: phosphorus, implantation method: almost vertical implantation, implantation energy: about 75 KeV, one dose amount: about 5 × 10 ¹¹ / cm ² , implantation number: one time is preferable It can be illustrated as a thing.

  Subsequently, activation annealing (for example, 1200 degrees Celsius, about 30 minutes) is performed on the N-type field stop region 42 as necessary.

  Next, as shown in FIG. 35, by epitaxial growth on the surface 1a side of the wafer 1, assuming that the N-type silicon epitaxial region 1e (withstand voltage of about 600 volts) has a thickness of, for example, about 50 micrometers and a resistivity of For example, about 22 Ωcm.

  Thereafter, the processes of FIGS. 38 and 39 described in the section 10 are executed, and further, the processes of FIGS. 41 to 43 described in the same section are executed.

14 Considerations and supplementary explanations related to sections 1 to 13 etc. In this section, considerations and supplementary explanations related to sections 1 to 13 etc. are given. Although the specific description will be given mainly by taking the IGBT as an example here, what is described here also applies to the diode as it is.

  As described in the beginning, an IGBT or the like having a higher concentration N-type buffer (Buffer) region than the N-type drift region (or N-type base region) in contact with the P-type collector region on the back side (diode of the diode). In some cases, the following is known in an N-type high concentration region or an N-type contact region). That is, this is a device configuration technique for improving the switching speed by leaving defects due to ion implantation for introducing the P-type collector region and the N-type buffer region in the N-type drift region near the N-type buffer region. . Such an “ion implantation defect residual IGBT” improves the switching speed at the time of off by the residual crystal defect acting as a recombination center, while the depletion layer contacts the crystal defect at the time of off, There is a possibility of causing a side effect that leakage current increases.

  Therefore, in each of the embodiments described above, an independent N-type field stop region 42 is provided separately from the N-type buffer region 19 that forms the back-side PN junction that determines the hole injection efficiency. For this reason, in the off state, the depletion layer is at most a portion above the crystal defect region 41 of the N − type drift region 20 between the N type buffer region 19 and the N type field stop region 42 (N type field stop region). 42), the leakage current does not increase. This is because the crystal defect region 41 has an N distribution from the vicinity of the bottom of the N type buffer region 19 on the N type field stop region 42 side (that is, the vicinity of the boundary between the N type buffer region 19 and the N − type drift region 20). This is because the N− type drift region 20 between the type field stop region 42 and the N type buffer region 19 is distributed in a portion close to the boundary.

  The above also applies to diodes. That is, in the diode, the impurity structure on the back surface side is obtained by removing the P + type collector region 18 from the IGBT. Here, in the diode, the N-type cathode region 47 corresponds to the N-type buffer region 19 of the IGBT.

15. Description of the IGBT junction termination structure (basic structure: back surface intermediate field stop-front surface single polysilicon & double metal field plate combination structure) of the one embodiment of the present application (mainly FIG. 46)
In this section, the device cross-sectional structure of the chip peripheral region 90 (including the chip end portion) in FIG. 4 is illustrated more specifically, and the junction termination structure (basic structure: middle of the back surface) of the IGBT according to the embodiment of the present application is described. A field stop-surface single polysilicon & double metal field plate combination structure) will be described.

  In the drawings and the like schematically showing the peripheral structure of the chip, in principle, the final passivation film or the like is not displayed.

  Further, the structure to which the single-stage poly-Si field plate described here is applied can be applied to a structure to which the thick N-type buffer region 52 (thick film buffer region) is applied as shown in FIG. 49 or FIG. Needless to say.

  FIG. 46 shows the junction termination structure of the IGBT from the end portion of the semiconductor chip for explaining the junction termination structure (basic structure: back surface intermediate field stop-front surface single polysilicon & double metal field plate combination structure) of the IGBT according to the embodiment of the present application. FIG. 5 is a schematic cross-sectional view up to a region (substantially corresponding to the chip peripheral region in FIG. 4).

  First, the back surface 1b side of the semiconductor chip 2 will be described. As shown in FIG. 46, the back surface 1b side of the semiconductor substrate 1s (or the semiconductor chip 2) has an intermediate field stop structure. Therefore, the metal collector electrode 17 is provided on the surface of the back surface 1b of the semiconductor chip 2, and the P + type collector region 18 is provided on the surface of the back surface 1b of the semiconductor chip 2 in contact therewith. . An N-type buffer region 19 is provided on the inner side of the P + -type collector region 18 in contact with the N-type drift region 20 at a distance from the N-type buffer region 19. A stop region 42 is provided. In the N − type drift region 20 between the N type field stop region 42 and the N type buffer region 19, a crystal defect region 41 is provided so as to be close to and along the N type buffer region 19. .

  Next, the surface 1a side of the semiconductor chip 2 will be described. For example, a P-type cell peripheral junction region 35 introduced at the same time as the P-type floating region 16 is provided on the semiconductor chip 2, that is, the surface 1 a on the inner side of the semiconductor substrate 1 s (N− type drift region 20). . A P-type body region 15 (P-type channel region) is provided on the surface of the P-type cell peripheral junction region 35. The peripheral contact portion 81 on the surface of the P-type body region 15 has a P + type body contact region 25p. (25) is provided.

  On the other hand, the chip end introduced simultaneously with the P + type body contact region 25, for example, on the surface 1a on the outside (chip end) of the semiconductor substrate 1s (N− type drift region 20), that is, the chip end contact portion 91, is provided. Part P + type body contact region 55 is provided. On the surface of the semiconductor substrate 1s in the vicinity of the chip end P + type body contact region 55, for example, a chip end N + type substrate contact region 49 introduced simultaneously with the N + type emitter region 12 is provided.

  Over the semiconductor substrate 1s, an end insulating film comprising an end insulating film 56pf of the first stage of the polysilicon field plate, an end insulating film 56mf of the first stage of the metal field plate, an end insulating film 56ms of the next stage of the metal field plate, etc. A film 56 (an insulating film mainly composed of a silicon oxide film) is provided. A polysilicon field plate 4p is provided in the end insulating film 56 on the outer end of the P-type cell peripheral junction region 35, and a polysilicon guard ring is provided in the end insulating film 56 at the chip end. 3p is provided.

  The P + type body contact region 25p is connected to the metal emitter electrode 8 extending on the end insulating film 56, and the chip end P + type body contact region 55 extends on the end insulating film 56. For example, it is connected to a metal guard ring 3 m mainly composed of an aluminum-based metal film formed simultaneously with the metal emitter electrode 8. On the other hand, the metal guard ring 3m is connected to the polysilicon guard ring 3p via the inter-guard-ring connecting portion 83, and constitutes the guard ring 3 together with the polysilicon guard ring 3p.

  On the end insulating film 56 on the polysilicon field plate 4p, for example, a metal gate wiring 7 mainly composed of an aluminum-based metal film formed simultaneously with the metal emitter electrode 8 is provided. The wiring 7 is connected to the polysilicon field plate 4p through a gate wiring-poly Si field plate connecting portion 82.

  On the end insulating film 56 between the metal gate wiring 7 and the metal guard ring 3m, for example, a metal field plate 4m mainly composed of an aluminum-based metal film formed simultaneously with the metal emitter electrode 8 is provided. ing. As described with reference to FIG. 6, the metal field plate 4m is connected to the metal emitter electrode 8 through, for example, a metal field plate-metal emitter electrode connecting portion 4c (FIG. 6), and together with the polysilicon field plate 4p, A field plate 4 (multistage field plate) is formed.

  In this example, the metal field plate 4m itself is multi-staged, and is composed of, for example, a metal field plate first stage part 4mf and a metal field plate next stage part 4ms.

  Here, the end insulating film 56pf (insulating film such as a silicon oxide film under the polysilicon field plate 4p) is thinner than the end insulating film 56mf under the metal field plate first stage portion 4mf, and the end insulating film is thin. The thickness of the film 56mf is made thinner than the end insulating film 56ms under the metal field plate next stage 4ms. A specific example is as follows. That is, the thickness of the end insulating film 56pf is, for example, about 120 nm (the range is, for example, about 80 to 160 nm). The thickness of the end insulating film 56mf is, for example, about 1.5 micrometers (the range is, for example, about 1.0 to 2.0 micrometers). Further, the thickness of the end insulating film 56ms is, for example, about 8 micrometers (the range is, for example, about 5 micrometers to 15 micrometers).

  As described above, in this example, since the polysilicon field plate 4p is provided at the outer end portion of the P-type cell peripheral junction region 35, electric field concentration at the outer end portion of the P-type cell peripheral junction region 35 is effectively performed. Can be prevented. Further, since there are multi-stage metal field plates 4m overlapping with the polysilicon field plate 4p, electric field concentration in each part when the depletion layer further extends can be effectively prevented.

  In addition, since it is an intermediate field stop type asymmetric IGBT, it is possible to ensure good switching characteristics with a small tail current.

16. Variations 1 (rear surface intermediate field stop-front surface double polysilicon & double metal field plate combination structure) and 2 (rear surface intermediate field stop-front surface multi-stage field plate & junction termination) relating to the junction termination structure of the IGBT according to the one embodiment of the present application Explanation of extension combination structure (mainly FIG. 47 and FIG. 48)
In this section, a modification of the junction termination structure of section 15 will be described. In the example described in this section, the back surface structure has the same intermediate N-type field stop region as that described in Section 15.

  Since the structure is almost the same as that of FIG. 46, only different parts will be described below in principle.

  FIG. 47 is a schematic cross-sectional view corresponding to FIG. 46 for explaining Modification 1 (back surface intermediate field stop-front surface double polysilicon & double metal field plate combination structure) relating to the junction termination structure of the IGBT according to the embodiment of the present invention. FIG. 5 is a diagram (corresponding almost to the chip peripheral region in FIG. 4). FIG. 48 is a schematic cross-sectional view corresponding to FIG. 46 for explaining Modification 2 (back surface intermediate field stop-front surface field plate & junction termination extension combined structure) relating to the junction termination structure of the IGBT according to the embodiment of the present invention. This corresponds approximately to the chip peripheral area of FIG.

(1) Description of Modification 1 (back surface intermediate field stop-front surface double polysilicon & double metal field plate combination structure) (mainly FIG. 47):
In this example, as shown in FIG. 47, the polysilicon field plate 4p has a polysilicon field plate next stage 4ps in addition to the polysilicon field plate first stage 4pf, and has a multistage structure. ing. Here, the thickness of the end insulating film 56ps is larger than the thickness of the end insulating film 56pf, and the thickness of the end insulating film 56ps is compared with the thickness of the end insulating film 56mf. It is thin. A specific example is as follows. That is, the thickness of the end insulating film 56ps is, for example, about 500 nm (for example, in the range of about 300 nm to 700 nm).

  As described above, in this example, since the multi-stage polysilicon field plate 4p is provided at the outer end portion of the P-type cell peripheral junction region 35, the electric field concentration at the outer end portion of the P-type cell peripheral junction region 35 is reduced. Further, it can be effectively prevented. This is because the electric field tends to concentrate particularly on the outer end portion of the P-type cell peripheral junction region 35. Since there is a multi-stage metal field plate 4m overlapping the polysilicon field plate 4p, electric field concentration in each part when the depletion layer further extends can be effectively prevented.

  Here, regarding the manufacturing process of the multi-stage polysilicon field plate 4p, for example, in the part of FIG. 57 of the manufacturing process described later, the thin film field silicon oxide film 29 is extended to the inner side, and the inner part thereof is extended. It is preferable to use a two-stage structure in which is thin silicon oxide.

(2) Description of Modification 2 (back surface intermediate field stop-front surface multistage field plate & junction termination extension combined structure) (mainly FIG. 48):
This example is structurally almost the same as that of FIG. 47, but as shown in FIG. 48, it is connected to the outer edge of the P-type cell peripheral junction region 35 to form an annular P-type surface RESURF. The difference is that a region 39, that is, a junction termination extension region is provided. The concentration of the P-type surface RESURF region 39 is such that it is completely depleted when the depletion layer extends, and the depth is shallower than the depth of the P-type cell peripheral junction region 35.

  As described above, in this example, the multi-stage polysilicon field plate 4p is provided at the outer end portion of the P-type cell peripheral junction region 35 and the P-type surface RESURF region 39 is added. Electric field concentration at the outer end of the peripheral junction region 35 can be further effectively prevented. This is because the electric field tends to concentrate particularly on the outer end portion of the P-type cell peripheral junction region 35. There is a multi-stage metal field plate 4m that overlaps with the polysilicon field plate 4p, and the P-type surface RESURF region 39 extends over almost the entire area below it, so that the depletion layer extends further. The electric field concentration in each part in the case can be further effectively prevented.

  Needless to say, the P-type surface RESURF region 39 described here can be applied not only to the structure of FIG. 47 but also to a structure using a single-stage poly-Si field plate as shown in FIG. Further, it goes without saying that the P-type surface RESURF region 39 described here can also be applied to those to which the thick film N-type buffer region 52 (thick film buffer region) is applied as shown in FIG. 49 or FIG.

  In terms of process, it is preferable to introduce the P-type surface resurf region 39 before the formation of the thin film field silicon oxide film 29 of FIG. 51, for example.

17. Modification 3 (back surface thick film buffer-front surface multistage field plate combination structure) and Modification 4 (back surface thick film buffer & high concentration buffer-surface multistage field plate combination structure) relating to the junction termination structure of the IGBT according to the embodiment of the present application ) (Mainly FIG. 49 and FIG. 50)
In the example described in this section, the back surface structure is changed from one having an intermediate N type field stop region, that is, “intermediate N type field stop type back surface structure” to so-called “thick film buffer type back surface structure”. Yes. The surface structures of these examples are exactly the same as those in FIG. 47, and the back surface structure has basically the same portions. Therefore, in principle, only different portions will be described below.

  49 is a schematic cross-sectional view corresponding to FIG. 46 (FIG. 4) for explaining a third modification (back surface thick film buffer-front surface multistage field plate combination structure) relating to the junction termination structure of the IGBT according to the embodiment of the present invention. It almost corresponds to the chip peripheral area). FIG. 50 is a schematic cross-sectional view corresponding to FIG. 46 for explaining Modification 4 (back surface thick film buffer & high concentration buffer-surface multi-stage field plate combination structure) related to the junction termination structure of the IGBT according to the embodiment of the present invention. (Almost corresponding to the chip peripheral area in FIG. 4).

(1) Description of Modification 3 (back surface thick film buffer-front surface multistage field plate combination structure) (mainly FIG. 49):
In this example, unlike FIG. 47, there is no N-type buffer region 19 and N-type field stop region 42 (FIG. 47), as shown in FIG. In contact therewith, a thick N-type buffer region 52 (thick film buffer region) having a large thickness is provided, and a crystal defect region 41 is provided in the lower half thereof. The thickness of the thick N-type buffer region 52 is preferably about 25 micrometers (with a range of about 15 to 35 micrometers), for example, with a breakdown voltage of about 600 volts. This also applies to the thick film N-type buffer region 52 and the N-type thick film cathode region 61 of other examples.

  According to such a configuration, the defect-layer-introduced thick film buffer asymmetric IGBT has an advantage that a switching characteristic with a relatively small tail current can be obtained while ensuring a soft recovery characteristic, and the junction termination of FIG. The same merit as the structure can be obtained.

  Note that the N-type thick film cathode region 61 is formed by, for example, ion implantation of impurities such as sulfur and selenium from the back surface of the wafer and an extension diffusion process in the non-epitaxy process as in the section 10 (next subsection). The same applies to On the other hand, in the non-epitaxy process as in section 10, for example, the crystal defect region 41 is irradiated with high energy ions (proton irradiation, helium ion irradiation, etc.) from the front surface or the back surface of the wafer as described for the IGBT in FIG. It is possible to use defect formation due to the above.

(2) Description of Modification 4 (back surface thick film buffer & high concentration buffer-surface multi-stage field plate combination structure) (mainly FIG. 50):
This example is a further modification of the example of FIG. 49, and is between the crystal defect region 41 and the P + type collector region 18 in FIG. The difference is that an N-type high-concentration buffer region 59 having a higher concentration than the buffer region 52 and thinner than the thick N-type buffer region 52 is provided. If such an N-type high concentration buffer region 59 is provided, defects will remain at the time of activation annealing of the P + type collector region 18 and the N-type high concentration buffer region 59 as will be described later in the process description with reference to FIG. By doing so, there is an advantage that the crystal defect region 41 can be easily formed.

18. Description of chip peripheral process in IGBT of one embodiment of the present application (mainly FIGS. 51 to 74)
The following description is basically the same as that described with reference to FIGS. 9 to 30 in sections 4 and 5 (although it includes additional processes), with the chip periphery of the same manufacturing process as the center. In the following description, only the parts not described in the above description will be described in principle.

  FIG. 51 is a view showing a manufacturing process of a portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present invention (thin film field silicon oxide film forming step). FIG. 52 is a manufacturing step of the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present invention (thin film field silicon oxide film processing step). FIG. FIG. 53 is a diagram of the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present invention during the manufacturing process (P-type well region introducing step) of the portion of FIG. 46 substantially corresponding to FIGS. It is device sectional drawing. FIG. 54 shows a manufacturing process of the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present invention (deposition of the hard mask film for forming the trench). It is device sectional drawing in a process. FIG. 55 shows a manufacturing process of the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present invention (hard mask film processing step for forming trenches). FIG. 56 is a device sectional view in the manufacturing step (trench formation step) of the portion in FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present invention. It is. FIG. 57 is a diagram showing a process of manufacturing a portion of FIG. 46 corresponding to FIGS. 9 to 30 substantially corresponding to FIGS. 9 to 30 for explaining the chip peripheral process in the IGBT according to the embodiment of the present invention (trench forming hard mask film removing step). FIG. FIG. 58 is a diagram showing a process of manufacturing a portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present invention (gate insulating film forming step). It is device sectional drawing. FIG. 59 is a manufacturing step (polysilicon film forming step) of the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present invention. It is device sectional drawing. FIG. 60 is a device in the manufacturing process (polysilicon film processing step) of the portion of FIG. 46 that substantially corresponds to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present application. It is sectional drawing. FIG. 61 is a diagram showing the process of manufacturing the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present invention (deposition of a silicon oxide film for ion implantation). It is device sectional drawing in a process. FIG. 62 is a diagram showing a cell region for explaining a chip peripheral process in the IGBT according to the embodiment of the present invention, during the manufacturing process (P-type body region introducing step) of the portion of FIG. 46 corresponding to FIGS. 9 to 30. It is device sectional drawing. FIG. 63 is a diagram illustrating a process of manufacturing the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present invention (chip end N + type substrate contact region). It is device sectional drawing in an introduction process. FIG. 64 is a manufacturing step (etch stop film forming step) of the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present invention. It is device sectional drawing. FIG. 65 is a diagram showing the process of manufacturing the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present application (thick film field silicon oxide film formation). It is device sectional drawing in a process. FIG. 66 is a diagram showing a process of manufacturing the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present invention (thick film field silicon oxide film processing step). FIG. FIG. 67 is a sectional view of the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present invention in the manufacturing process of the portion of FIG. 46 corresponding to FIGS. 9 to 30 (interlayer insulating film formation & first contact stage) It is device sectional drawing in a process. FIG. 68 is a device cross section during the manufacturing process (contact final stage process) of the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present invention. FIG. 69 is a device sectional view in the manufacturing step (substrate etching step) of the portion in FIG. 46 that substantially corresponds to FIGS. 9 to 30 in the cell region for illustrating the chip peripheral process in the IGBT of the embodiment of the present application. It is. FIG. 70 shows a manufacturing process of a portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present invention (chip end P + type body contact region). It is device sectional drawing in an introduction process. FIG. 71 is a diagram of the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present invention, during the manufacturing process (aluminum-based metal electrode forming process) of the portion of FIG. 46 substantially corresponding to FIGS. It is device sectional drawing. FIG. 72 is a manufacturing step of the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present invention (N-type field stop region forming step). FIG. FIG. 73 is a device cross section in the manufacturing step (back grinding step) of the portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT of the embodiment of the present application. FIG. FIG. 74 is a diagram showing the process of manufacturing a portion of FIG. 46 corresponding to FIGS. 9 to 30 in the cell region for explaining the chip peripheral process in the IGBT according to the embodiment of the present invention (N-type buffer region & P + type collector region). It is device sectional drawing in an introduction process.

As described in Section 4, first, an N-type silicon single crystal (for example, a phosphorus concentration of about 2 × 10 ¹⁴ / cm ³ , for example, a resistivity of about 65 Ωcm, and a particularly preferable range is, for example, a resistivity of 60 Ωcm to 70 Ωcm) (Wafers of various diameters such as 150φ, 100φ, 300φ, and 450φ may be used). Here, for example, a wafer by FZ (Floating Zone) method is most suitable, but a wafer by CZ (Czochralski) method may be used. This is because a wafer having a high resistivity is more easily obtained by the FZ method. Since the resistivity of the semiconductor substrate strongly depends on the withstand voltage, the case of a withstand voltage of 600 volts and a withstand voltage of 1200 volts is shown as an example. That is, at a withstand voltage of 600 volts, as described above, the resistivity is, for example, about 65 Ωcm, and the range is generally preferably 50 Ωcm or more and less than 90 Ωcm, and considering mass productivity, 60 Ωcm or more, More preferably less than 80 Ωcm. On the other hand, at a withstand voltage of 1200 volts, as described above, the resistivity is, for example, about 100 Ωcm, and as a range, a range of 90 Ωcm or more and less than 150 Ωcm is generally a preferable range. More preferably less than about 120 Ωcm. Thus, since no epitaxial process is used, it is very economical.

  Next, as shown in FIG. 51, a thin field silicon oxide film 29 having a thickness of about 600 nm is formed on almost the entire surface 1a (first main surface) of the wafer 1 (1s) by, for example, thermal oxidation. Form a film.

  Next, as shown in FIG. 52, the thin film field silicon oxide film 29 is patterned by, for example, ordinary lithography (for example, after this patterning, the hole barrier region introducing step of FIG. 9 in the cell region is performed). Next, a thin silicon oxide film 71 for ion implantation having a thickness of, for example, about 30 nm is formed on almost the entire surface 1a of the wafer 1 by, for example, thermal oxidation.

  Next, as shown in FIG. 53, a resist film 37 for introducing a P-type floating region is formed on the surface 1a of the wafer 1 by, for example, ordinary lithography, and this is used as a mask for ion implantation in the cell region 10. A P-type cell peripheral junction region 35 is introduced simultaneously with the P-type floating region 16 (FIG. 10). Thereafter, the P-type floating region introduction resist film 37 that has become unnecessary is removed by, for example, ashing.

  Next, as shown in FIG. 54 (corresponding to FIG. 11 in the cell region 10), for example, a silicon oxide film having a thickness of about 450 nm is formed as the trench forming hard mask film 32 by CVD or the like.

  Next, as shown in FIG. 55 (corresponding to FIG. 12 in the cell region 10), a resist film 33 for trench hard mask film processing is formed on the surface 1a of the wafer 1 by, for example, ordinary lithography, The trench forming hard mask film 32 is processed as an etching resistant mask. Thereafter, the trench-forming hard mask film 32 that is no longer needed is removed by, for example, ashing (corresponding to FIG. 13 in the cell region 10).

  Next, as shown in FIG. 56 (corresponding to FIG. 14 in the cell region 10), the trench 21 is formed by anisotropic dry etching, for example, using the patterned trench forming hard mask film 32 as an etching resistant mask. .

  Next, as shown in FIG. 57 (corresponding to FIG. 15 in the cell region 10), the trench forming hard mask film 32 is removed by wet etching, for example.

  Next, as shown in FIG. 58 (corresponding to FIG. 16 in the cell region 10), simultaneously with the extension diffusion of the P-type floating region 16 and the like of the cell region 10, the extension diffusion of the P-type cell peripheral junction region 35 is performed. Thereafter, a gate insulating film 22 is formed on almost the entire surface 1a of the wafer 1 (including the inner surface of the trench 21) by, for example, thermal oxidation.

  Next, as shown in FIG. 59 (corresponding to FIG. 17 in the cell region 10), at the same time as the polysilicon film 27 in the cell region 10, on the substantially entire surface 1a of the wafer 1 (including the inner surface of the trench 21), for example, A polysilicon film 27 is formed by CVD.

  Next, as shown in FIG. 60 (corresponding to FIG. 18 in the cell region 10), for example, the polysilicon guard ring 3p and the polysilicon field plate 4p are processed on the surface 1a of the wafer 1 by ordinary lithography. The resist film is formed. Then, using this as a mask, the polysilicon film 27 is processed simultaneously with the etch back of the polysilicon film 27 in the cell region 10 by dry etching, for example. Thereafter, the resist film that is no longer needed is removed by, for example, ashing, and the gate oxide film on the surface is removed by, for example, wet etching (corresponding to FIG. 19 in the cell region 10).

  Next, as shown in FIG. 61, for example, a silicon oxide film 38 for ion implantation is formed on almost the entire surface on the surface 1a side of the wafer 1 by, for example, thermal oxidation or CVD (see FIG. 20 in the cell region 10). Correspondence).

  Next, as shown in FIG. 62, for example, a P-type body region introduction resist film 36 is formed on the surface 1a side of the wafer 1 by, for example, ordinary lithography, and this is used as a mask, for example, by ion implantation. Then, a P-type body region 15 (P-type channel region) is introduced (corresponding to FIG. 20 in the cell region 10). Thereafter, the P-type body region introduction resist film 36 that has become unnecessary is removed by, for example, ashing or the like.

  Next, as shown in FIG. 63, for example, a source / drain region introduction resist film 50 is formed on the surface 1a side of the wafer 1 by, for example, ordinary lithography, and this is used as a mask to form the N + type of the cell region 10. Simultaneously with the introduction of the emitter region 12, a chip end N + type substrate contact region 49 is introduced by ion implantation, for example (corresponding to FIG. 20 in the cell region 10). After that, the source / drain region introduction resist film 50 that is no longer needed is removed by, for example, ashing.

  Next, as shown in FIG. 64, a silicon nitride film (for example, a contact etching stop film 51 (contact process or other etch stop film) is formed on almost the entire surface on the surface 1a side of the wafer 1 by, for example, CVD. A film is formed (corresponding to FIG. 20 in the cell region 10).

  Next, as shown in FIG. 65, for example, a thickness of about 10 micrometers (for example, a range of about 5 to 15 micrometers) is formed on almost the entire surface on the surface 1a side of the wafer 1 by, for example, CVD or SOG. The silicon oxide film is formed as a thick field silicon oxide film 69.

  Next, as shown in FIG. 66, for example, a resist film 57 for edge insulating film processing is formed on the surface 1a side of the wafer 1 by, for example, ordinary lithography, and this is used as a mask to form the contact etching stop film 51. As an etching stop, the thick film field silicon oxide film 69 is processed by wet etching, for example. Thereafter, the end insulating film processing resist film 57 that is no longer needed is removed by, for example, ashing.

  Next, as shown in FIG. 67, for example, an interlayer insulating film 26 is formed on almost the entire surface 1a side of the wafer 1 by, eg, CVD (corresponding to FIG. 21 in the cell region 10). Next, a contact groove forming resist film 28 is formed on the surface 1a side of the wafer 1 by, for example, ordinary lithography. Next, using this as a mask and using the contact etching stop film 51 as an etching stop, for example, by anisotropic dry etching, the contact trench 11 (or contact hole), the peripheral contact portion 81, the gate wiring-poly-Si field plate connection portion. 82, a guard ring connecting portion 83, a chip end contact portion 91, and the like (corresponding to FIG. 22 in the cell region 10).

  Next, as shown in FIG. 68, the contact etching stop film 51 such as the bottom of the contact trench 11, the silicon oxide film 38 for ion implantation, and the like are removed by dry etching or wet etching (FIG. 22 in the cell region 10). Corresponding). Thereafter, the contact groove forming resist film 28 that has become unnecessary is removed by, for example, ashing.

  Next, as shown in FIG. 69 (corresponding to FIG. 23 in the cell region 10), for example, by anisotropic dry etching, the contact trench 11 (or contact hole), the peripheral contact portion 81, the gate wiring-poly-Si field plate The connecting portion 82, the guard ring connecting portion 83, the chip end contact portion 91, and the like are extended inside the semiconductor substrate 1s, the polysilicon film 27, and the like.

  Next, as shown in FIG. 70 (corresponding to FIG. 24 in the cell region 10), simultaneously with the introduction of the P + type body contact region 25 in the cell region 10, the P + type body contact region 25d of the dummy cell and the cell peripheral junction region 35 A P + type body contact region 25p, a chip end P + type body contact region 55, and the like are introduced. In the cell region 10, when the P + type latch-up prevention region 23 is introduced, it may be introduced at the same time.

  Next, as shown in FIG. 71 (corresponding to FIG. 25 in the cell region 10), an aluminum-based metal film is formed on almost the entire surface of the wafer 1 on the surface 1a side and patterned, whereby the metal emitter electrode 8, Metal gate wiring 7, metal field plate 4m, metal guard ring 3m, and the like are formed. Next, if necessary, a final passivation film 60 is formed, and the gate pad 6 and the emitter pad 9 (FIG. 6) are opened. Note that the final passivation film may be at other timing as required.

  Thereafter, this corresponds to the back surface process of section 5 related to the cell region 10 (a manufacturing process related to the structure on the back surface side).

  Next, as shown in FIG. 72 (corresponding to FIG. 26 in the cell region 10), the N-type field stop region 42 is introduced into the N-type drift region 20 by, for example, proton irradiation and annealing. Such high-energy ion irradiation (hydrogen ions, helium ions) is an advantageous method for realizing a non-epitaxy process, and can be applied to formation of a defect layer in addition to doping.

  Next, as shown in FIG. 73 (corresponding to FIG. 27 in the cell region 10), backgrinding is performed on the back surface 1b of the wafer 1 as necessary.

  Next, as shown in FIG. 74, the N-type buffer region 19 and the P + type collector region 18 are introduced as described with reference to FIGS. 28 and 29 regarding the cell region 10. Next, as described with reference to FIG. 29 regarding the cell region 10, the crystal defect region 41 is formed simultaneously with the activation annealing of the N-type buffer region 19 and the P + type collector region 18. Thereafter, the metal collector electrode 17 is formed on the back surface 1b of the wafer 1 as described with reference to FIG. Such a method for forming a defective layer can be formed simultaneously with necessary activation annealing, so that the process can be simplified.

19. Description of cell peripheral structure in IGBT of one embodiment of the present application (mainly FIG. 75 and FIG. 76)
The description in this section is basically a supplementary explanation for sections 2 and 15 (same for sections 16 and 17 describing this variant).

  75 is an enlarged top view of the cell region corner cutout region R4 of FIG. FIG. 76 is a device sectional view corresponding to a section taken along line H-H ′ of FIG. 75. Based on these, a supplementary explanation about the cell region peripheral structure will be given.

  As shown in FIG. 75, at the end of the cell region 10, the width direction of the linear unit cell region 40 (FIG. 5) (the width direction of the linear active cell region 40a, the linear inactive cell region 40i, etc.). 1 to several dummy cell regions 34 (linear dummy cell regions) are provided. Similar to the linear active cell region 40a, a P + type body contact region 25d is provided in the dummy cell region 34.

  On the other hand, at the end in the length direction of the linear unit cell region 40 (FIG. 5), the end trench gate electrode 14p and a relatively narrow width (the same width as the linear active cell region 40a) N + A region where the type emitter region 12 and the like (in this example, the N-type hole barrier region 24 is not formed) is also formed as an end buffer region including the region where the dummy cell region 34 is provided. ing. A ring-shaped P-type cell peripheral junction region 35 is provided outside these end buffer regions so as to surround them. The P-type impurity doped region constituting the P-type cell peripheral junction region 35 is For example, they are simultaneously formed by the same process as that of the P-type floating region 16.

  On the P-type cell peripheral junction region 35, the trench gate electrode 14 extends from the cell region 10 as a gate lead portion 14w. The P-type cell peripheral junction region 35 has a structure similar to that of the cell region 10. A large number of P + type body contact regions 25p (this portion also corresponds to the peripheral contact portion 81 in FIG. 76) are provided.

  The metal emitter electrode 8 covers the outer periphery of the cell region 10 and is electrically connected to the P-type cell peripheral region 35 at the peripheral contact portion 81. A metal gate wiring 7 extends around the periphery of the metal emitter electrode 8, and the gate lead-out portion 14w (in this example, directly, the polysilicon field plate 4p) is connected to the metal gate wiring-trench gate electrode. In the portion 13 (corresponding to the gate wiring-poly-Si field plate connecting portion 82 in FIG. 46 and the like), they are interconnected. Usually, in the periphery of the chip, the metal emitter electrode 8 and the metal gate wiring 7 and the periphery thereof are substantially covered with a final passivation film 60 (FIG. 76).

  Next, FIG. 76 shows a cross section taken along the line H-H ′ of FIG. 75. As shown in FIG. 76, P-type body region 15 is provided on surface 1a of semiconductor substrate 2 in linear inactive cell region 40i, P-type cell peripheral junction region 35, and the like. In the vicinity of the boundary between the linear inactive cell region 40i and the P-type cell peripheral junction region 35, an end trench gate electrode 14p is provided, which is a part of the end buffer region. A P-type floating region 16 is provided below the P-type body region 15 below the linear inactive cell region 40i. The depth of the P-type floating region 16 is the same as that of other portions, as compared to the trench 21e (21). Further, it covers the lower end of the trench 21e (21) in which the end trench gate electrode 14p is accommodated.

  Further, a contact groove (or contact hole) or the like is also provided in the P-type cell peripheral junction region 35, and an emitter contact (peripheral contact portion 81) is also provided. A surface region of the semiconductor substrate 2 under the emitter contact is provided with a P + type body contact region 25p and a P + type latch-up prevention region 23p, and the lower part is a main part of the P type cell peripheral junction region 35. It is a P-type impurity doped region (for example, formed simultaneously with the P-type floating region 16).

  The reason why the peripheral contact portion 81 is provided is that, as shown in FIG. 3, a cell peripheral junction region 35 is provided in a ring shape around the outside of the cell region 10, A P-type impurity doped region (for example, formed simultaneously with P-type floating region 16) is provided. This is because the area of the cell peripheral junction region 35 is considerably large, and if the peripheral contact portion 81 is not provided, holes are likely to accumulate in this portion. If the peripheral contact portion 81 is not provided, the accumulated holes inevitably flow into the cell region (unwanted flow of holes), and the latch-up resistance is reduced. In this regard, as shown in FIG. 76, a P-type impurity doped region (for example, formed at the same time as the P-type floating region 16) which is a main part of the cell peripheral junction region 35 and a P-type floating region 16 of the cell region 10 are electrically connected. Separation is effective in preventing undesired flow of holes. The presence of the end trench 21e also contributes to this. In this example, no trench is provided outside the end trench 21e to connect the gate lead portions 14w to each other. This is because if there is such a trench (similar to or deeper than the end trench 21e), a voltage drop occurs due to the flow of holes in that portion, and the latch-up resistance is lowered. In addition, extending the peripheral contact portion 41 in the width direction of the cell peripheral junction region 35 is limited by the presence of the normally existing metal gate wiring 7. This is because the metal emitter electrode 8 and the metal gate wiring 7 are usually composed of the same metal layer.

20. Consideration and supplementary explanation regarding the entire application and each embodiment (including various modifications) (mainly FIGS. 83 and 84)
FIG. 83 is a schematic top view of a chip for explaining the outline of the IGBT junction termination structure according to the embodiment of the present application. FIG. 84 is a schematic top view of a chip for explaining an example of the outline variation of the junction termination structure of FIG. Based on these, consideration and supplementary explanation regarding the entire present application and each embodiment (including various modifications) will be made.

(1) General considerations regarding termination structures such as IGBT:
As described above, when considering a junction termination structure such as an IGBT or a diode, a peripheral length of a multi-stage field plate (Field Plate) and a multi-floating field ring (Floating Field Ring) ( Comparing the peripheral length of the former (including those using a combination of multiple field plates), the former is considered to be considerably longer. This is because the critical electric field strength in the insulating film is considerably higher than the critical electric field strength in the drift region or the like.

  Here, in order to obtain a good breakdown voltage characteristic by applying a junction termination structure using a multistage field plate, it is necessary to increase the resistivity of the drift region in order to suppress an increase in the electric field strength on the substrate surface.

  However, in a conventional asymmetric IGBT having a buffer region in contact with the collector region, when a defect layer for minority carrier lifetime control is introduced into the buffer region or the like, increasing the resistivity of the drift region, As a result of excessive extension of the depletion layer at the time of off, the depletion layer reaches the defect layer, which may cause a significant increase in leakage current. Therefore, in the “general asymmetric IGBT”, it is difficult to try to shorten the peripheral length by using a multi-stage field plate.

  On the other hand, “thick film buffer asymmetric IGBT” in which a thick film N-type buffer region doped with sulfur or selenium having a large diffusion coefficient and having no defect layer is introduced (strictly speaking, a defect layer non-introduced thick film) Buffer asymmetric IGBT) has been proposed, and in this structure, the depletion layer is gently stopped in the off state, so that rapid carrier depletion can be prevented and soft recovery characteristics can be obtained. Further, the thick film buffer asymmetric IGBT does not have a risk of increasing the leakage current because there is no defective layer even if the resistivity of the substrate is increased. However, on the other hand, it is necessary to introduce a special diffusion process, and the thermal burden is relatively large. Another problem is that the tail current is relatively large because there is no defect layer.

(2) Description of outline of junction termination structure of IGBT according to one embodiment of the present application (mainly referring to FIG. 83 and FIG. 46):
Therefore, the IGBT according to the embodiment of the present application has a field stop region in the drift region separately from the buffer region in contact with the collector region, and a defect between this and the buffer region. In the “intermediate field stop asymmetric IGBT” having a region, a multistage field plate is applied as a junction termination structure.

  An outline of this junction termination structure is shown in FIG. As shown in FIG. 83, in this device, there is a cell region 10 of an intermediate field stop type asymmetric IGBT inside the semiconductor chip 2 and an annular P-type cell peripheral junction region 35 surrounding the periphery thereof. The annular multi-stage field plate 54 is provided from the outer end portion to the outside.

  With such a structure, when the semiconductor substrate having a relatively high resistivity is used, since the extension of the depletion layer stops at the N-type field stop region 42 (for example, FIG. 46) at the time of off, Under these conditions, the crystal defect region 41 (FIG. 46) is not reached. Accordingly, the resistivity of the substrate can be increased to such an extent that the characteristics of the multi-stage field plate can be sufficiently extracted, so that the peripheral length can be efficiently reduced.

(3) Description of variations regarding outline of junction termination structure (mainly FIG. 84):
A variation of the multistage field plate of FIG. 83 is illustrated in FIG. As shown in FIG. 83, the multi-stage field plate 54 may be composed of a single annular body (including an annular portion of a predetermined conductor pattern), or as shown in FIG. A plurality of overlapping annular bodies (including an annular portion of a predetermined conductor pattern) may be used. In FIG. 84, the plurality of annular bodies are, for example, a polysilicon field plate 4p and a metal field plate 4m. Here, the polysilicon field plate 4p and the metal field plate 4m may each be a single stage or multiple stages. Therefore, in FIG. 84, the multistage field plate 54 is composed of a plurality of annular bodies.

(4) Application to thick film buffer asymmetric IGBT (mainly see FIG. 49):
When the multistage field plate 4 is applied to the “defect layer introduction type thick film asymmetric IGBT” in which the defect layer is introduced into the thick film asymmetric IGBT having no defect layer described in FIG. 49, the soft recovery characteristic is maintained. As a result, the tail current can be reduced, and a semiconductor substrate having a relatively high specific resistance can be applied, and the merit of the multistage field plate 4 can be fully exploited.

21. Summary Although the invention made by the inventors of the present application has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, in the above-described embodiment, a device using mainly an aluminum-based surface electrode has been described. However, the present invention is not limited thereto, and it goes without saying that the present invention can also be applied to devices using other metals.

  In the above-described embodiment, the IGBT and the diode mainly using the silicon substrate have been specifically described. However, the present invention is not limited thereto, and the SiC substrate, the GaN substrate, the GaAs substrate, and the InP substrate. Needless to say, the present invention can also be applied to those using the above.

  In the above-described embodiment, the device mainly having an N-type drift region has been specifically described. However, the present invention is not limited thereto, and it goes without saying that the device can also be applied to a device having a P-type drift region. Yes.

  In the above-described embodiment, the flyback diode is specifically described mainly for the diode. However, the present invention is not limited thereto, and it goes without saying that the diode can be applied to other purposes.

  In the above-described embodiment, the defect caused by the ion implantation remains in the crystal defect region during the annealing process, but the present invention is not limited to this, and the ions of hydrogen ions, helium ions, other ions and particles are not limited thereto. It goes without saying that a new one may be formed by driving.

1 Semiconductor wafer 1a Wafer or chip surface (first main surface)
1b Back surface of wafer or chip (second main surface)
1e N-type silicon epitaxial region 1s N-type single crystal silicon substrate 2 Semiconductor chip (semiconductor substrate)
3 guard ring 3m metal guard ring 3p polysilicon guard ring 4 field plate 4c metal field plate-metal emitter electrode connection 4d metal field plate-metal anode electrode connection 4m metal field plate 4mf metal field plate first stage 4ms metal field plate next Step part 4p Polysilicon field plate 4pf Polysilicon field plate first stage part 4ps Polysilicon field plate next stage part 5 Metal gate electrode 6 Gate pad 7 Metal gate wiring 8 Metal emitter electrode 9 Emitter pad 10 Cell region (main PN junction region of diode) )
11 Contact groove (or contact hole)
12 N + type emitter region 13 Metal gate wiring-trench gate electrode connecting portion 14 Trench gate electrode 14p End trench gate electrode 14w Gate lead-out portion 15 P type body region (P type channel region)
16 P-type floating region 17 Metal collector electrode (or metal cathode electrode)
17a Aluminum back surface metal film 17b Titanium back surface metal film 17c Nickel back surface metal film 17d Gold back surface metal film 18 P + type collector region 19 N type buffer region 20 N− type drift region 21 Trench 22 Gate insulating film 23 P + type latch-up prevention region 24 N-type hole barrier region 25 P + type body contact region 25d P + type body contact region of dummy cell 25p P + type body contact region of cell peripheral junction region 25r P + type body contact region of floating field ring 26 Interlayer insulating film 27 Polysilicon film 28 Contact Groove-forming resist film 29 Thin film field silicon oxide film 30 Aluminum doped region (high concentration collector contact region or high concentration back contact region)
31 Resist film for introducing N-type hole barrier region 32 Hard mask film for forming trench 33 Resist film for processing trench hard mask film 34 Dummy cell region (linear dummy cell region)
35 P-type cell peripheral junction region 36 P-type body region introduction resist film 37 P-type floating region introduction resist film 38 Silicon oxide film for ion implantation 39 P-type surface resurf region 40 Linear unit cell region 40a Linear active cell region 40aa Active section 40i Linear inactive cell region 41 Crystal defect region 42 N-type field stop region 43 Back grind position 44 Anode metal electrode 45 Anode pad 46 P-type anode region 47 N-type cathode region 48 P-type surface region 49 Chip edge Part N + type substrate contact region 50 Source / drain region introduction resist film 51 Contact etching stop film 52 Thick film N type buffer region (thick film buffer region)
54 Multi-stage field plate 55 Chip end P + type body contact region 56 End insulating film 56 mf End insulating film of metal field plate first stage 56 ms End insulating film of metal field plate next stage 56 pf End of first stage of polysilicon field plate Insulating film 56 ps End insulating film of polysilicon field plate next stage 57 Resist film for processing end insulating film 58 Laminated film of thin silicon oxide film for upper layer ion implantation and upper layer etching stop film 59 N-type high concentration buffer region 60 Final passivation film 61 N-type thick film cathode region 67 High concentration cathode region 69 Thick film field silicon oxide film 71 Thin silicon oxide film for ion implantation 81 Peripheral contact part 82 Gate wiring-poly Si field plate connection part 83 Connection between drillings 90 Chip peripheral area 91 Chip end contact A Anode terminal C Collector terminal D, Da, Db, Dc, Dd, De, Df Flyback diode E Emitter terminal G Gate terminal K Cathode terminal M Motor Pa, Pb , Pc, Pd, Pe, Pf IGBT and diode pair Q, Qa, Qb, Qc, Qd, Qe, Qf IGBT
R1 Cell region edge cutout region R3 Cell region internal cutout region R4 Cell region corner cutout region R5 Linear unit cell region main portion and surrounding cutout region Vs DC power supply Wa Width of linear active cell region Wi Linear inactive cell Area width

Claims (20)

IGBT including:
(A) a semiconductor substrate having a first main surface and a second main surface;
(B) a drift region of a first conductivity type that occupies the main part from the first main surface of the semiconductor substrate to the inside;
(C) a cell region provided from the first main surface to the inside of the drift region;
(D) a ring-like shape that is a surface region on the first main surface side of the drift region and that surrounds the periphery of the cell region and has a second conductivity type opposite to the first conductivity type. Cell peripheral junction area;
(E) a ring-shaped multistage field plate provided so as to surround the periphery of the cell region between the cell peripheral junction region and the peripheral edge of the semiconductor substrate;
(F) The channel region of the second conductivity type provided in the first principal surface side surface region of the drift region in the cell region;
(G) the emitter region of the first conductivity type provided in the first principal surface side surface region of the channel region;
(H) the collector region of the second conductivity type provided in the second principal surface side surface region of the drift region;
(I) the buffer region of the first conductivity type provided between the collector region and the drift region and having a higher concentration than this;
(J) A crystal defect region provided in the vicinity of the boundary from the vicinity of the boundary along the buffer region;
(K) A field stop region of the first conductivity type provided in the drift region on the first main surface side along the crystal defect region and having a higher concentration than the drift region.     2. The IGBT according to claim 1, wherein the semiconductor substrate is a single crystal silicon substrate.     3. The IGBT according to claim 2, wherein the single crystal silicon substrate is based on an FZ method.     4. The IGBT according to claim 3, wherein the IGBT is a trench gate type.     5. The IGBT according to claim 4, wherein the field stop region is formed by irradiation with hydrogen ions or helium ions.     6. The IGBT according to claim 5, wherein the crystal defect region is left during activation annealing of the collector region and the buffer region. The IGBT of claim 5 further comprising:
(L) A ring-shaped surface resurf region having the second conductivity type, which is provided on the first main surface side surface region of the drift region and surrounds the periphery of the cell peripheral junction region. 6. The IGBT of claim 5, wherein the multi-stage field plate comprises:
(E1) Multistage metal field plate. In the IGBT of paragraph 8, the multi-stage field plate has the following:
(E2) A poly-Si field plate provided between the inner end of the metal field plate and the outer end of the cell peripheral junction region.     10. The IGBT according to claim 9, wherein the poly-Si field plate is a multi-stage poly-Si field plate. IGBT including:
(A) a semiconductor substrate having a first main surface and a second main surface;
(B) a drift region of a first conductivity type that occupies the main part from the first main surface of the semiconductor substrate to the inside;
(C) a cell region provided from the first main surface to the inside of the drift region;
(D) a ring-like shape that is a surface region on the first main surface side of the drift region and that surrounds the periphery of the cell region and has a second conductivity type opposite to the first conductivity type. Cell peripheral junction area;
(E) a ring-shaped multistage field plate provided so as to surround the periphery of the cell region between the cell peripheral junction region and the peripheral edge of the semiconductor substrate;
(F) The channel region of the second conductivity type provided in the first principal surface side surface region of the drift region in the cell region;
(G) the emitter region of the first conductivity type provided in the first principal surface side surface region of the channel region;
(H) the collector region of the second conductivity type provided in the second principal surface side surface region of the drift region;
(I) The thick film buffer region of the first conductivity type provided between the collector region and the drift region, thicker than the collector region, and higher in concentration than the drift region;
(J) A crystal defect region provided in the thick film buffer region.     12. The IGBT according to claim 11, wherein the semiconductor substrate is a single crystal silicon substrate.     The IGBT according to claim 12, wherein the single crystal silicon substrate is formed by an FZ method.     14. The IGBT according to claim 13, wherein the IGBT is a trench gate type.     15. The IGBT according to claim 14, wherein the crystal defect region is formed by irradiation with hydrogen ions or helium ions. 15. The IGBT of claim 14, further comprising:
(K) The first conductivity type high concentration buffer region provided between the collector region and the thick film buffer region and having a higher concentration than the thick film buffer region.     17. The IGBT according to claim 16, wherein the crystal defect region is left during activation annealing of the high concentration buffer region. 16. The IGBT of claim 15, wherein the multi-stage field plate has:
(E1) Multistage metal field plate. 19. The IGBT of claim 18, wherein the multistage field plate comprises:
(E2) A poly-Si field plate provided between the inner end of the metal field plate and the outer end of the cell peripheral junction region.     20. The IGBT according to claim 19, wherein the poly-Si field plate is a multi-stage poly-Si field plate.

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