JP6412617B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a technology effective when applied to a device structure and a manufacturing technology of a power semiconductor device (or semiconductor integrated circuit device) such as an IGBT (Insulated Gate Bipolar Transistor) and a diode.

  In Japanese Patent Laid-Open No. 2004-193212 (Patent Document 1), in a punch-through IGBT or the like, an n + type region is provided in the middle of an n− type drift region in order to suppress oscillation of a voltage / current waveform at turn-off. Technology is disclosed.

  In Japanese Patent Laid-Open No. 2001-77357 (Patent Document 2), in order to realize a low tail current characteristic or the like in a punch-through IGBT or the like, an n − type is provided between a p + type collector region and an n + type field stop region. A technique for providing an intermediate region and a low lifetime region forming a part of the intermediate region is disclosed.

  Japanese Patent Application Laid-Open No. 2008-85050 (Patent Document 3) or US Pat. No. 7777660 (Patent Document 4) corresponding thereto discloses a silicon single crystal having a field stop region and FZ (Floating Zone) method. In an IGBT or the like using a wafer, a technique is disclosed in which a crystal defect caused by ion implantation is left and used as a lifetime killer in annealing after ion implantation for collector formation from the back surface.

JP 2004-193212 A JP 2001-77357 A JP 2008-85050 A US Patent No. 7777660

  In an IGBT or the like having an N-type buffer (Buffer) region in contact with the P-type collector region on the back surface side and having a higher concentration than the N-type drift region (or N-type base region), the N- There is known a device configuration method for improving the switching speed by leaving defects due to ion implantation or the like for introducing a P-type collector region or an N-type buffer region in the type drift region. Such an “ion implantation defect residual IGBT” improves the switching speed at the time of off by the residual crystal defect acting as a recombination center, while the depletion layer contacts the crystal defect at the time of off, There is a possibility of causing a side effect that leakage current increases. These points also apply to a flyback diode connected in reverse parallel to an IGBT or the like.

  The present invention has been made to solve these problems.

  An object of the present invention is to provide a highly reliable IGBT or a diode used in combination with the IGBT.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, according to one aspect of the present invention, there is provided an N-type buffer region that is provided in contact with the P-type collector region on the back surface side and has a higher concentration than the N-type drift region, and the N-type buffer region and the N-type drift region. In an IGBT having a defect residual region (crystal defect region) provided in the vicinity of the boundary of the N − type drift region from the vicinity of the boundary of the N − type drift region, A higher concentration N-type field stop region is provided.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the N-type buffer region having a higher concentration than the N-type drift region provided in contact with the P-type collector region on the back surface side, and the N-type drift region from the vicinity of the boundary between the N-type buffer region and the N-type drift region. In an IGBT having a defect residual region provided in a portion adjacent to the type drift region, an N-type field stop region having a higher concentration is provided in the N− type drift region on the surface side of the defect residual region. Therefore, the depletion layer does not reach the defect residual region in the off state.

It is an interconnection diagram of IGBT and a diode pair which shows the usage form of the semiconductor device (IGBT and diode) of each embodiment of this application. FIG. 2 is a circuit diagram of a motor drive circuit in which the IGBT and the diode pair shown in FIG. 1 are applied to drive a three-phase motor. It is a top surface schematic layout figure of the cell region of IE type | mold trench gate IGBT device chip | tip for describing the outline of main embodiment of this application, and its periphery. FIG. 4 is a device schematic cross-sectional view corresponding to the A-A ′ cross section of the cell region end cutout region R1 of FIG. FIG. 9 is an enlarged top view of the linear unit cell region of FIG. 3 and its periphery R5 regarding one embodiment of the present application (one-dimensional active cell thinning structure: corresponding to FIGS. 6 to 8). FIG. 6 is an overall top view of the IE-type trench gate IGBT device chip of the one embodiment of the present application (common to other embodiments) (almost corresponding to FIG. 3 but close to a more specific shape). FIG. 7 is an enlarged top view of the cell region internal cutout region R3 of FIG. 6. It is device sectional drawing corresponding to the D-D 'cross section of FIG. FIG. 9 is a device sectional view in the manufacturing process (hole barrier region introducing step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (P-type floating region introduction step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (trench processing hard mask film forming step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application; FIG. 9 is a device sectional view in the manufacturing process (trench hard mask processing step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (trench hard mask processing resist removal step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application; FIG. 9 is a device sectional view in the manufacturing process (trench processing step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (trench processing hard mask removal step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application; FIG. 9 is a device cross-sectional view in the manufacturing process (stretch diffusion and gate oxidation step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (gate polysilicon film forming step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (gate polysilicon etchback step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (gate oxide film etchback step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application; FIG. 9 is a device sectional view in the manufacturing process (P-type body region and N + type emitter region introduction step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (interlayer insulating film forming step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. It is device sectional drawing in the manufacturing process (contact hole formation process) corresponding to FIG. 8 for demonstrating the manufacturing method corresponding to the device structure of the said one Embodiment of this application. FIG. 9 is a device cross-sectional view in the manufacturing process (substrate etching process) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (P + type body contact region and P + type latch-up prevention region introducing step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application; . FIG. 9 is a device sectional view in the manufacturing process (surface metal film forming step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (N-type field stop region introduction step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (back grinding process) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (N-type buffer region introduction step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (P + type collector region introduction step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 9 is a device sectional view in the manufacturing process (metal collector electrode formation step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 7 is an enlarged top view of the cell region internal cutout region R3 of FIG. 6 relating to a modification (full active cell region) of the IGBT cell structure according to the embodiment of the present application. FIG. 32 is a device cross-sectional view corresponding to the D-D ′ cross section of FIG. 31; It is local detailed sectional drawing of the device back surface for demonstrating the device structure of the modified example (aluminum dope contact) of the back surface detailed structure of IGBT of the said one Embodiment of this application, and its manufacturing method. FIG. 9 is a device sectional view in the manufacturing process (N-type field stop region introduction step) corresponding to FIG. 8 for describing the modification (epitaxial process) of the surface device formation process regarding the IGBT according to the embodiment of the present application; FIG. 9 is a device cross-sectional view in the manufacturing process (N-type silicon epitaxial region forming step) corresponding to FIG. 8 for describing a modification (epitaxial process) of the surface device forming process related to the IGBT according to the embodiment of the present invention; . FIG. 7 is an overall top view of a diode chip corresponding to FIG. 6 relating to a basic example (a PIN diode having a crystal defect region and an intermediate field stop region) of a power diode according to an embodiment of the present application. FIG. 37 is a device cross-sectional view of a main device region corresponding to the F-F ′ cross section of FIG. 36. FIG. 38 is a device cross-sectional view during the manufacturing process (P-type anode region introducing step) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. FIG. 38 is a device cross-sectional view during the manufacturing process (metal anode electrode formation step) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. FIG. 38 is a device cross-sectional view during the manufacturing process (N-type field stop region introduction step) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. FIG. 38 is a device cross-sectional view during the manufacturing process (back grinding process) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode according to the embodiment of the present application. FIG. 38 is a device cross-sectional view during the manufacturing process (N-type cathode region introduction step) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. FIG. 38 is a device cross-sectional view during the manufacturing process (metal cathode electrode forming step) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. FIG. 37 is a device cross-sectional view of a unit cell portion corresponding to the FF ′ cross section of FIG. 36 regarding Modification 1 (MPS diode having a crystal defect region and an intermediate field stop region) of the power diode according to the embodiment of the present application. . FIG. 37 is a device cross-sectional view of a unit cell portion corresponding to the F-F ′ cross section of FIG. 36 regarding Modification 1 (SSD having a crystal defect region and an intermediate field stop region) of the power diode according to the embodiment of the present application.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. IGBT including:
(A) a semiconductor substrate having a first main surface and a second main surface;
(B) a drift region of a first conductivity type occupying a main part of the semiconductor substrate;
(C) a channel region of a second conductivity type opposite to the first conductivity type provided in the first main surface side surface region of the drift region;
(D) the emitter region of the first conductivity type provided in the first principal surface side surface region of the channel region;
(E) the collector region of the second conductivity type provided in the surface region on the second main surface side of the drift region;
(F) the buffer region of the first conductivity type provided in the drift region inside thereof so as to be in contact with the collector region and having a higher concentration than this;
(G) a crystal defect region provided along the buffer region in a portion adjacent to the drift region from the vicinity of the boundary;
(H) A field stop region of the first conductivity type provided in the drift region closer to the first main surface along the crystal defect region and having a higher concentration than the drift region.

  2. In the IGBT of item 1, the semiconductor substrate is a single crystal silicon substrate.

  3. In the IGBT of item 2, the single crystal silicon substrate is formed by an FZ method.

  4). In the IGBT of item 3, the field stop region is formed by hydrogen ion or helium ion implantation.

  5. In the IGBT according to any one of Items 1 to 4, the IGBT is a trench gate type.

  6). In the IGBT according to any one of Items 1 to 5, the IGBT is an IE-type trench gate IGBT.

7). The IGBT according to any one of 1 to 6 further includes:
(I) a metal collector electrode provided on the second main surface of the semiconductor substrate;
(J) a high concentration collector contact region provided on the metal collector electrode side of the collector region, having the same conductivity type as the collector region, and having a higher impurity concentration;
Here, the high concentration collector contact region is a region doped with aluminum.

  8). In the IGBT of item 7, the portion of the metal collector electrode that contacts the high concentration collector contact region is a metal film containing aluminum as a main component.

9. Diode including:
(A) a semiconductor substrate having a first main surface and a second main surface;
(B) a drift region of a first conductivity type occupying a main part of the semiconductor substrate;
(C) an anode metal electrode provided on the first main surface of the semiconductor substrate;
(D) the cathode region of the first conductivity type provided in the surface region on the second main surface side of the drift region and having a concentration higher than that;
(E) a crystal defect region provided along the cathode region in a portion adjacent to the drift region from the vicinity of the boundary;
(F) The field stop region of the first conductivity type provided in the drift region on the first main surface side along the crystal defect region and having a higher concentration than the drift region.

  10. In the diode of item 9, the semiconductor substrate is a single crystal silicon substrate.

  11. In the diode described in 10 above, the single crystal silicon substrate is formed by an FZ method.

  12 12. In the diode of item 11, the field stop region is formed by hydrogen ion or helium ion implantation.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Further, in the present application, the term “semiconductor device” mainly refers to various types of transistors, diodes (active elements) alone, or resistors, capacitors, etc., such as semiconductor chips (for example, single crystal silicon substrates, circuit boards, etc.). ) Collected above. Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. At this time, typical examples of various single transistors include power MOSFETs and IGBTs (Insulated Gate Bipolar Transistors). These are categorized into power semiconductor devices, and include power MOSFETs, IGBTs, bipolar power transistors, thyristors, power diodes, and the like.

  A typical form of the power MOSFET is a double diffused vertical power MOSFET having a source electrode on the front surface and a drain electrode on the back surface. The double diffused vertical power MOSFET is a double diffused vertical power MOSFET. The first type is a planar gate type which will be mainly described in the embodiment, and the second type is a trench gate type such as a U-MOSFET.

  Other power MOSFETs include LD-MOSFETs (Lateral-Diffused MOSFETs).

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, “silicon oxide film”, “silicon oxide insulating film”, etc. are not only relatively pure undoped silicon oxide (FS), but also FSG (Fluorosilicate Glass), TEOS-based silicon oxide ( Thermal oxide films such as TEOS-based silicon oxide), SiOC (Silicon Oxicarbide) or Carbon-doped Silicon oxide or OSG (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass), CVD Oxide film, SOG (Spin ON Glass), nano-clustering silica (Nano-Clustering Silica: NCS) and other coating-type silicon oxide, silica-based low-k insulating film (porous insulating) Needless to say, a film) and a composite film with other silicon-based insulating films including these as main constituent elements are included.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like. Here, “silicon nitride” includes both SiN and SiNH unless otherwise specified. Similarly, “SiCN” includes both SiCN and SiCNH, unless otherwise specified.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5. "Wafer" usually refers to a single crystal silicon wafer or the like on which a semiconductor device (same as a semiconductor integrated circuit device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, or an LCD glass substrate. Needless to say, a composite wafer such as a semiconductor layer is also included. The wafer material is not limited to silicon, but may be SiGe, SiC, GaN, GaAs, InP, or the like.

  6). As described above for power MOSFETs, IGBTs are generally roughly classified into a planar gate type and a trench gate type. Although this trench gate type IGBT has a relatively low on-resistance, in order to further promote conductivity modulation and further lower the on-resistance, an “IE-type trench gate IGBT” using the IE (Injection Enhancement) effect (or "Active cell thinning-out type trench gate IGBT") has been developed. In the IE trench gate IGBT, an active cell (Active Cell) actually connected to the emitter electrode and an inactive cell (Inactive Cell) having a floating P body region are alternately or comb-shaped in the cell region. By arranging in a tooth shape, the structure is such that holes are easily accumulated on the device main surface side (emitter side) of the semiconductor substrate.

  In the present application, when it is necessary to distinguish a conventional trench gate IGBT that is not an IE trench gate IGBT, that is, an active cell thinning type, particularly from an IE trench gate IGBT, a “full active type” is described. This is referred to as “trench gate IGBT (or non-IE trench gate IGBT)”. Note that “full active” does not exclude peripheral dummy cells, inactive cells as peripheral structures, and the like.

  7). In the present application, among the IE-type trench gate IGBTs, a main active cell whose width is narrower than a main inactive cell is referred to as a “narrow active cell IE-type trench gate IGBT”.

  The direction crossing the trench gate is defined as “cell width direction”, and the extending direction (longitudinal direction) of the trench gate (linear gate portion) orthogonal thereto is defined as “cell length direction”.

  In this application, mainly “linear unit cell region” (consisting of a linear active cell region and a linear inactive cell region) is mainly handled, but this linear unit cell region is periodically repeated. Thus, they are arranged in the internal area of the semiconductor chip to constitute a “cell area”.

  A cell peripheral junction region is usually provided around the cell region, and a floating field ring or a field limiting ring is provided around the cell region. Make up structure. Here, the floating field ring or the field limiting ring is provided on the surface (device surface) of the drift region separately from the P-type body region (P-type well region) and has the same conductivity type as that of the floating field ring or field limiting ring. An impurity region or a group of impurity regions having a concentration (concentration that does not cause complete depletion when a reverse voltage is applied to the main junction) and surrounding the cell region in a ring shape in a single or multiple manner.

  These floating field rings may be provided with a field plate. This field plate is a conductor film pattern connected to the floating field ring, and extends above the surface (device surface) of the drift region via the insulating film, and the portion surrounding the cell region in a ring shape. say.

  Although it is reasonable to treat the linear unit cell area as a periodic element constituting the cell area as a set of linear inactive cell areas arranged on both sides centering on the linear active cell area, Specifically, when the linear inactive cell region is individually described, it is inconvenient because it is separated on both sides. In this case, a specific integral part is referred to as a linear inactive cell region.

  8). In this application, when describing a diode, the description regarding IGBT is used as needed. When the diode is viewed as a bipolar structure without the gate of the IGBT, the anode of the diode corresponds to the emitter of the IGBT and the cathode of the diode corresponds to the collector of the IGBT.

  Diodes used as fly-back diodes are classified into PIN diodes (Pin Diodes) and Schottky diodes (Schottky Diodes). Further, as a composite device, there are an MPS (Merged Pin-Schottky) diode, an SSD (Static-Shielding-Diode) and the like.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

1. Description of main application fields such as semiconductor device (IGBT, diode) of each embodiment of the present application (mainly FIG. 1 and FIG. 2)
Hereinafter, the motor drive circuit will be specifically described as an application example, but it is needless to say that the application field of the semiconductor device (IGBT, diode) and the like of each embodiment of the present application is not limited to this.

  FIG. 1 is an interconnection diagram of an IGBT and a diode pair showing how the semiconductor device (IGBT and diode) of each embodiment of the present application is used. FIG. 2 is a circuit diagram of a motor drive circuit in which the IGBT and the diode pair shown in FIG. 1 are applied to drive a three-phase motor. Based on these, main application fields such as the semiconductor device (IGBT, diode) of each embodiment of the present application will be described.

  The IGBT and the diode constituting the embodiment of the present application are used in a pair connection state (for example, as a pair module) as shown in FIG. That is, the collector terminal C of the IGBT (Q) and the cathode terminal K of the flyback diode D are connected, and the emitter terminal E of the IGBT (Q) and the anode terminal A of the flyback diode D are connected. When viewed from the outside, there are three terminals including the gate terminal G.

  Next, FIG. 2 shows an example of a specific application circuit (three-phase motor drive circuit) of the IGBT & diode pair Pa, Pb, Pc, Pd, Pe, Pf. As shown in FIG. 2, this three-phase motor drive circuit uses the IGBT & diode pairs Pa, Pb, Pc, Pd, Pe, and Pf to switch the output from the DC power supply 31 at high speed, thereby making the three-phase motor 30 Is driving. Each IGBT & diode pair Pa, Pb, Pc, Pd, Pe, Pf is composed of a combination of IGBT elements Qa, Qb, Qc, Qd, Qe, Qf and power diode elements Da, Db, Dc, Dd, De, Df. ing.

  The power diode element according to the present invention is not limited to the IGBT, but may be used as a switching element such as a MOS transistor or a bipolar transistor. The power diode element is not limited to a three-phase motor, and is a circuit such as a two-phase motor or a solenoid drive. Can be widely used.

2. Description of the overall structure of the IGBT device chip according to an embodiment of the present application (mainly FIGS. 3 to 5)
In this section, specific examples are shown, the above definitions are supplemented, representative specific examples of the present application are extracted, their outlines are explained, and overall preliminary explanations are given.

  In the following description, the IE type trench gate IGBT will be specifically described as an example. However, as will be described later, it goes without saying that the present invention can also be applied to a full active type trench gate IGBT as it is.

  FIG. 3 is a schematic layout diagram of the upper surface of the cell region of the IE trench gate IGBT device chip and its periphery for explaining the outline of the main embodiment of the present application. FIG. 4 is a device schematic cross-sectional view corresponding to the A-A ′ cross section of the cell region end cutout region R <b> 1 of FIG. 3. FIG. 5 is an enlarged top view of the linear unit cell region of FIG. 3 and its periphery R5 relating to the one embodiment of the present application (one-dimensional active cell thinning structure: corresponding to FIGS. 6 to 8). Based on these, the entire structure and the like of the IGBT device chip according to the embodiment of the present application will be described.

(1) Description of the planar structure of the cell region and its periphery (mainly FIG. 3):
First, the upper surface of the inner region of the device chip 2 of the IE-type trench gate IGBT, which is the main object of the description in this section (the inner part of the guard ring or the like that is the outermost part of the termination structure, that is, the main part of the chip 2). The figure is shown in FIG. As shown in FIG. 3, the main part of the internal region of the chip 2 (semiconductor substrate) is occupied by the cell region 10. In the cell region 10, a P-type cell peripheral junction region 35 is provided on the outer periphery so as to surround the cell region 10. Outside the cell peripheral junction region 35, a P-type floating field ring 36 (that is, a field limiting ring) is provided with an interval and presenting one or a plurality of rings, and the cell peripheral junction region 35, Together with the guard ring 4 (see FIG. 6) and the like, a termination structure for the cell region 10 is configured.

  In this example, a large number of linear unit cell regions 40 are laid in the cell region 10, and a pair of or more dummy cells (about one or several columns in one case) are provided in these end regions. A region 34 (linear dummy cell region) is arranged.

(2) Description of intermediate field stop region, narrow active cell type unit cells and alternate arrangement method (mainly FIG. 4):
Next, FIG. 4 shows an AA ′ cross section of the cell region end cutout region R1 of FIG. As shown in FIG. 4, a P + type collector region 18 is provided in a semiconductor region (in this example, a silicon single crystal region) on the back surface 1 b (the back main surface or the second main surface of the semiconductor substrate) of the chip 2. The metal collector electrode 17 is provided on the surface. Between the N − type drift region 20 (first conductivity type drift region) and the P + type collector region 18 (second conductivity type collector region) constituting the main part of the semiconductor substrate 2, there is an N − type drift region. An N-type buffer region 19 (first conductivity type buffer region) having a concentration higher than 20 is provided. That is, the N-type buffer region 19 is provided in the N− type drift region 20 inside so as to be in contact with the P + type collector region 18. A crystal defect region 41 is provided along the N-type buffer region 19 in the vicinity of the boundary (the boundary between the N-type buffer region 19 and the N-type drift region 20) and in the vicinity of the N-type drift region 20. Further, an N-type field stop region having a higher concentration than the N-type drift region 20 is formed in the N-type drift region 20 on the first main surface side so as to extend along the crystal defect region 41. 42 is provided.

  Here, the crystal defect region 41 is for improving the switching characteristics by limiting the lifetime of the holes. For example, the activation defect after the introduction of the N-type buffer region 19 and the P + type collector region 18 is performed. The crystal defects that remain are used. The N-type field stop region 42 (intermediate field stop region) has an effect of preventing the depletion layer from reaching the crystal defect region 41 and preventing an increase in leakage current in the off state. Further, since there is an N-type field stop region 42 (intermediate field stop region) with the N-type drift region 20 sandwiched between the N-type buffer region 19 and the P + type collector region that determines the hole injection efficiency. There is an advantage that the concentration relationship of the PN junction between the N-type buffer region 19 and the concentration of the N-type field stop region 42 can be set independently.

  On the other hand, a large number of trenches 21 are provided in the semiconductor region on the surface side 1a (the front-side main surface or the first main surface of the semiconductor substrate) of the N − type drift region 20, and a gate insulating film is included therein. A trench gate electrode 14 is embedded via 22. These trench gate electrodes 14 are connected to the metal gate electrode 5.

  Further, these trenches 21 function to partition each region. For example, the dummy cell region 34 is partitioned from both sides by a pair of trenches 21, and the cell region 10 is formed by one of the trenches 21. The cell peripheral junction region 35 is partitioned. The cell peripheral junction region 35 is connected to the metal emitter electrode 8 through the P + type body contact region 25p. In the present application, unless otherwise specified, the thickness of the gate insulating film 22 in any part of the trench is substantially the same (however, if necessary, the thickness of a part is different from that of the other part and is different. Is not to eliminate). As described above, by making emitter contact in the cell peripheral junction region 35 and the dummy cell region 34, it is possible to prevent the breakdown voltage from being lowered even when the width of the dummy cell region 34 or the like is changed in a process. it can.

  A P-type floating field ring 36 is provided in the semiconductor region on the surface side 1a of the N − type drift region 20 outside the cell peripheral junction region 35, and the field plate 4 is provided on the surface 1a. The P + type body contact region 25r is connected to the floating field ring 36.

  Next, the cell region 10 will be further described. The dummy cell region 34 is basically the same in structure and size as the linear active cell region 40a except that it does not have the N + type emitter region 12, and is a P + type body provided on the surface of the P type body region 15. Contact region 25 d is connected to metal emitter electrode 8. Most of the inner region of the cell region 10 basically has a repetitive structure to be translated with the linear unit cell region 40 as a unit cell (note that the objectivity in a strict sense is not required. The same applies hereinafter. ) The linear unit cell region 40 as a unit lattice is composed of a linear active cell region 40a and half-width linear inactive cell regions 40i on both sides thereof, specifically, adjacent linear active cell regions 40i. It can be seen that a linear inactive cell region 40i having a full width is disposed between the layers 40a (see FIG. 5).

  A P-type body region 15 (second-conductivity-type channel region) is provided in a semiconductor surface region on the front-side main surface 1a (first main surface) side of the semiconductor substrate of the linear active cell region 40a. Are provided with an N + type emitter region 12 (first conductivity type emitter region) and a P + type body contact region 25. The P + type body contact region 25 is connected to the metal emitter electrode 8. In the linear active cell region 40 a, an N-type hole barrier region 24 is provided in the N − -type drift region 20 below the P-type body region 15.

  On the other hand, a P-type body region 15 is similarly provided in the semiconductor surface region on the front-side main surface 1a (first main surface) side of the semiconductor substrate in the linear inactive cell region 40i, and the N− The type drift region 20 is provided with a P-type floating region 16 (second conductivity type floating region) that covers the lower ends of the trenches 21 on both sides and is deeper than that. By providing such a P-type floating region 16, the width Wi of the linear inactive cell region can be increased without causing a sharp drop in breakdown voltage. This makes it possible to effectively enhance the hole accumulation effect. In the IE type trench gate IGBT, the P type floating region 16 accumulates holes therein, thereby reducing the hole concentration of the N − type drift region 20 (N base region) below the linear active cell region 40a. As a result, the on-resistance is reduced by increasing the concentration of electrons injected from the MOSFET in the IGBT into the N base region.

  In this example, the width Wa of the linear active cell region 40a is narrower than the width Wi of the linear inactive cell region 40i. In the present application, this is referred to as a “narrow active cell unit cell”. Hereinafter, the device having the narrow active cell type unit cell will be specifically described below. However, the invention of the present application is not limited thereto, and the device having the “non-narrow active cell type unit cell”. Needless to say, it can also be applied.

  In the example of FIG. 4, the linear unit cell region 40 is configured by alternately arranging the linear active cell regions 40a and the linear inactive cell regions 40i. This is called an “arrangement method”. In the following description, the description will be made on the premise of the alternating arrangement method unless otherwise specified. Needless to say, the “non-alternating arrangement method” may be used.

  In FIG. 4, the main part that illustratively includes each part of various embodiments of the present application has been described. However, in the following description, these are constituent elements such as a cell part (cross section, planar structure), a cell peripheral part, and the like. Although these are described separately, they are not individually separated, but as shown in FIG. 4, various modified examples are replaced with the respective constituent elements to constitute the main part.

(3) Description of active cell one-dimensional thinning structure (mainly FIG. 5)
An example of the detailed planar structure of the main part of the linear unit cell region of FIG. 3 and the surrounding cutout region R5 is shown in FIG. As shown in FIG. 5, the N + type emitter region 12 is provided in the entire length direction of the linear active cell region 40a. That is, the entire area of the linear active cell region 40a in the length direction is an active section 40aa. Here, the active section 40aa refers to a section in the length direction of the linear active cell region 40a in which the N + -type emitter region 12 is provided.

  In the present application, this structure is referred to as an “active cell one-dimensional thinning structure”.

3. Description of the cell structure of the IGBT according to the embodiment of the present application (mainly FIGS. 6 to 8)
In this section, based on the description of sections 1 and 2, an example of a specific chip top surface layout and unit cell structure corresponding to the above embodiment (one-dimensional thinning of active cells corresponding to FIGS. 3 to 5 in section 2). Taking the structure as an example). The cell structure described in this section is an alternating array type narrow active cell unit cell.

  In general, when the IGBT element 2 having a withstand voltage of 600 volts is taken as an example, the average chip size is 3 to 6 mm square. Here, for convenience of explanation, a chip having a length of 4 mm and a width of 5.2 mm will be described as an example. Here, description will be made assuming that the breakdown voltage of the device is about 600 volts, for example.

  FIG. 6 is an overall top view (almost corresponding to FIG. 3 but close to a more specific shape) of the IE-type trench gate IGBT device chip according to the one embodiment of the present application (common to other embodiments). is there. FIG. 7 is an enlarged top view (P-type deep floating & hole barrier linear unit cell structure) of the cell region internal cutout region R3 of FIG. FIG. 8 is a device cross-sectional view corresponding to the D-D ′ cross section of FIG. 7. Based on these, the device structure of the IE-type trench gate IGBT in the one embodiment of the present application will be described.

  As shown in FIG. 6, an annular guard ring 3 made of, for example, an aluminum-based wiring layer is provided on the outer peripheral portion of the upper surface 1a of the IGBT device chip 2, and an annular floating ring is provided on the inner side thereof. Several (single or plural) annular field plates 4 (for example, composed of the same aluminum-based wiring layer as the above) connected to a field ring or the like are provided. A cell region 10 is provided inside the field plate 4 (floating field ring 36) and in the main part of the inner region of the upper surface 1a of the chip 2, and the cell region 10 extends to the vicinity of the outside, for example, The metal emitter electrode 8 is made of the same aluminum-based wiring layer as before. A central portion of the metal emitter electrode 8 serves as a metal emitter pad 9 for connecting a bonding wire or the like. Between the metal emitter electrode 8 and the field plate 4, for example, the same aluminum-based wiring layer as above. A configured metal gate wiring 7 is arranged. The metal gate wiring 7 is connected to, for example, a metal gate electrode 5 composed of the same aluminum-based wiring layer or the like, and the central portion of the metal gate electrode 5 is a gate pad for connecting a bonding wire or the like. 6

  Next, an enlarged top view of the cell region internal cutout region R3 of FIG. 6 is shown in FIG. As shown in FIG. 7, the cell region 10 is composed of linear active cell regions 40a and linear inactive cell regions 40i arranged alternately in the horizontal direction. A trench gate electrode 14 is disposed between the linear active cell region 40a and the linear inactive cell region 40i, and a linear contact groove 11 (or contact) is formed at the center of the linear active cell region 40a. Hall) is arranged. A linear N + type emitter region 12 is provided in the linear active cell region 40 a on both sides of the contact groove 11. On the other hand, in the linear inactive cell region 40i, a P-type body region 15 and a P-type floating region 16 are provided on the upper and lower sides (see FIG. 4 or FIG. 8) on almost the entire surface.

  Next, FIG. 8 shows a D-D ′ cross section of FIG. 7. As shown in FIG. 8, a P + type collector region 18 and an N type buffer region 19 are formed in the semiconductor region of the back surface 1 b of the semiconductor chip 2 so as to be in contact with the top and bottom, and on the back surface 1 b of the semiconductor chip 2. The metal collector electrode 17 is formed. That is, as described above, the N-type buffer region 19 is provided in the N-type drift region 20 inside thereof so as to be in contact with the P + type collector region 18. A crystal defect region 41 is provided along the N-type buffer region 19 in the vicinity of the boundary (the boundary between the N-type buffer region 19 and the N-type drift region 20) and in the vicinity of the N-type drift region 20. Further, an N-type field stop region 42 having a higher concentration is provided in the N − -type drift region 20 on the first main surface side so as to extend along the crystal defect region 41. Yes.

  An N-type hole barrier region 24 is arranged in this order from the bottom in the N − type drift region 20 (surface side semiconductor region of the semiconductor substrate) on the surface 1a (first main surface) side of the semiconductor chip 2 in the linear active cell region 40a. (First conductivity type hole barrier region), P type body region 15 and N + type emitter region 12 are provided. An interlayer insulating film 26 is formed on the surface 1a of the semiconductor chip 2, and a contact trench 11 (or contact hole) extending inside the semiconductor substrate is formed in the interlayer insulating film 26 portion in the linear active cell region 40a. A P + type body contact region 25 and a P + type latch-up prevention region 23 are provided from the top in the bottom semiconductor region such as the contact groove 11. The P-type body region 15 and the N + -type emitter region 12 are connected to the metal emitter electrode 8 provided on the interlayer insulating film 26 via the contact groove 11 and the like.

  Here, the N-type hole barrier region 24 is a barrier region for preventing holes from flowing into the passage from the N− type drift region 20 to the N + type emitter region 12, and the impurity concentration thereof is N + type emitter region. It is lower than 12 and higher than the N − type drift region 20. Due to the presence of the N-type hole barrier region 24, holes accumulated in the linear inactive cell region 40i are directed to the emitter passage (from the N− type drift region 20 to the P + type body contact region 25) of the linear active cell region 40a. It is possible to effectively prevent entry into the passage.

  In contrast, in the linear inactive cell region 40i, the N − type drift region 20 (the surface side semiconductor region of the semiconductor substrate) on the surface 1a (first main surface) side of the semiconductor chip 2 is sequentially arranged from the bottom. A P-type floating region 16 and a P-type body region 15 are provided, and the depth of the P-type floating region 16 is deeper than the depth of the trench 21 and is distributed so as to cover the lower end portion of the trench 21. ing.

  Here, in order to illustrate the device structure more specifically, an example of main dimensions of each part of the device (see FIGS. 8 and 4) is shown. That is, the width Wa of the linear active cell region is about 2.3 micrometers, and the width Wi of the linear inactive cell region is about 6 micrometers (the width Wa of the linear active cell region is the linear inactive cell). It is desirable that the width is smaller than the width Wi of the region, and the value of Wi / Wa is particularly preferably in the range of 2 to 3, for example.) The contact width is about 0.5 micrometers, and the trench width is 0.7 micrometers. The depth of the trench is about 3 micrometers, the depth of the N + -type emitter region 12 is about 250 nm, and the depth of the P-type body region 15 (channel region). The depth of the P + type latch-up prevention area 23 is about 1.4 micrometers, and the P type floating area is about 0.8 micrometers. The depth of the region 16 is about 4.5 micrometers, the thickness of the N-type buffer region 19 is about 1.5 micrometers, the thickness of the P + type collector region is about 0.5 micrometers, and the N-type field. The thickness of the stop region 42 is about 10 micrometers, its position is about 50 micrometers from the substrate surface, and the thickness of the semiconductor substrate 2 is about 70 micrometers (here, an example with a breakdown voltage of about 600 volts is shown). It is. Note that the thickness of the semiconductor substrate 2 strongly depends on the required breakdown voltage. Therefore, for a withstand voltage of 1200 volts, it is about 120 micrometers, for example, and for a withstand voltage of 400 volts, it is about 40 micrometers, for example.

  In the following example and the example in section 2, the dimensions of the corresponding parts are substantially the same as those shown here, and therefore the description will not be repeated.

4). Description of surface device formation process and the like related to the IGBT according to the embodiment of the present application (mainly FIGS. 9 to 25)
In this section, an example of a manufacturing method for the device structure described in Section 3 is shown. In the following description, the cell region 10 will be mainly described. For the peripheral portion and the like, reference is made to FIGS. 3 to 5 as necessary.

  FIG. 9 is a device sectional view in the manufacturing process (hole barrier region introducing step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 10 is a device sectional view in the manufacturing process (P-type floating region introduction step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 11 is a device sectional view in the manufacturing process (trench processing hard mask film forming step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 12 is a device sectional view in the manufacturing process (trench hard mask processing step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 13 is a device sectional view in the manufacturing process (trench hard mask processing resist removal step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the embodiment of the present application. FIG. 14 is a device sectional view in the manufacturing process (trench processing step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 15 is a device sectional view in the manufacturing process (trench processing hard mask removal step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 16 is a device sectional view in the manufacturing process (stretch diffusion and gate oxidation step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 17 is a device sectional view in the manufacturing process (gate polysilicon film forming step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 18 is a device sectional view in the manufacturing process (gate polysilicon etch-back step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 19 is a device sectional view in the manufacturing process (gate oxide film etchback step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 20 is a device sectional view in the manufacturing process (P-type body region and N + type emitter region introducing step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the embodiment of the present application. . 21 is a device sectional view in the manufacturing process (interlayer insulating film forming step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 22 is a device sectional view in the manufacturing process (contact hole forming step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 23 is a device sectional view in the manufacturing process (substrate etching step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 24 is a device cross section during the manufacturing process (P + type body contact region and P + type latch-up prevention region introducing step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. FIG. 25 is a device sectional view in the manufacturing process (surface metal film forming step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. Based on these, the surface device formation process and the like related to the IGBT according to the embodiment of the present application will be described.

First, an N− type silicon single crystal (for example, wafers of various diameters such as 150φ, 100φ, 300φ, 450φ, etc.) with a phosphorus concentration of about 2 × 10 ¹⁴ / cm ³ and a resistivity of 22 Ωcm to 30 Ωcm may be prepared. Here, for example, a wafer by FZ (Floating Zone) method is most suitable, but a wafer by CZ (Czochralski) method may be used.

Next, as shown in FIG. 9, an N-type hole barrier region introduction resist film 31 is formed on the entire surface 1a (first main surface) of the semiconductor wafer 1 by coating or the like, and is performed by normal lithography. Patterning. Using the patterned N-type hole barrier region introducing resist film 31 as a mask, for example, by ion implantation, the semiconductor substrate 1s (N− type single crystal silicon substrate) on the surface 1a (first main surface) side of the semiconductor wafer 1 is used. An N-type hole barrier region 24 is formed by introducing N-type impurities therein. As ion implantation conditions at this time, for example, ion species: phosphorus, dose amount: about 6 × 10 ¹² / cm ² , and implantation energy: about 80 KeV can be exemplified as preferable ones. Thereafter, the resist film 31 that has become unnecessary is removed by ashing or the like.

Next, as shown in FIG. 10, a P-type floating region introducing resist film 37 is formed on almost the entire surface 1a of the semiconductor wafer 1 by coating or the like and patterned by ordinary lithography. Using the patterned P-type floating region introducing resist film 37 as a mask, P-type impurities are introduced into the semiconductor substrate 1s on the surface 1a (first main surface) side of the semiconductor wafer 1, for example, by ion implantation. Thus, the P-type floating region 16 is formed. As ion implantation conditions at this time, for example, ion species: boron, dose amount: about 3.5 × 10 ¹³ / cm ² , and implantation energy: about 75 KeV can be exemplified as preferable ones. Thereafter, the resist film 37 that has become unnecessary is removed by ashing or the like. When the P-type floating region 16 is introduced, the cell peripheral junction region 35 and the floating field ring 36 shown in FIG.

  Next, as shown in FIG. 11, a hard mask film 32 for trench formation such as a silicon oxide insulating film (for example, by CVD (Chemical Vapor Deposition) or the like is formed on almost the entire surface 1a of the semiconductor wafer 1 by, for example, CVD. A thickness of about 450 nm) is formed.

  Next, as shown in FIG. 12, a resist film 33 for trench hard mask film processing is formed on almost the entire surface 1a of the semiconductor wafer 1 by coating or the like, and is patterned by ordinary lithography. Using the patterned trench hard mask film processing resist film 33 as a mask, the trench forming hard mask film 32 is patterned by, for example, dry etching.

  Thereafter, as shown in FIG. 13, the resist film 33 that has become unnecessary is removed by ashing or the like.

Next, as shown in FIG. 14, the trench 21 is formed by anisotropic dry etching, for example, using the patterned trench forming hard mask film 32. As a gas system for this anisotropic dry etching, for example, a Cl ₂ / O ₂ system gas can be exemplified as a suitable one.

  After that, as shown in FIG. 15, the trench forming hard mask film 32 that has become unnecessary is removed by wet etching using, for example, a hydrofluoric acid based silicon oxide film etching solution.

  Next, as shown in FIG. 16, extended diffusion (for example, about 1200 degrees Celsius and about 30 minutes) is performed on the P-type floating region 16 and the N-type hole barrier region 24. Subsequently, a gate insulating film 22 (for example, a thickness of about 120 nm) is formed on the surface 1a of the semiconductor wafer 1 and almost the entire inner surface of the trench 21 by, for example, thermal oxidation.

  Next, as shown in FIG. 17, phosphorus is doped on the surface 1a of the semiconductor wafer 1 on the gate insulating film 22 and almost the entire inner surface of the trench 21 by, for example, CVD so as to fill the trench 21. A doped polysilicon (Doped Poly-Silicon) film 27 is formed (for example, a thickness of about 600 nm).

Next, as shown in FIG. 18, the trench gate electrode 14 is formed in the trench 21 by etching back the polysilicon film 27 by dry etching or the like (for example, gas system is SF ₆ or the like).

  Next, as shown in FIG. 19, the gate insulating film 22 outside the trench 21 is removed, for example, by wet etching using a hydrofluoric acid silicon oxide film etchant or the like.

Next, as shown in FIG. 20, a relatively thin silicon oxide film (for example, the same as the gate insulating film) for subsequent ion implantation is formed on almost the entire surface 1a of the semiconductor wafer 1 by, for example, thermal oxidation or CVD. Degree). Subsequently, a resist film for introducing a P-type body region is formed on the surface 1a of the semiconductor wafer 1 by ordinary lithography. Using this P-type body region introduction resist film as a mask, P-type body region 15 is formed by introducing P-type impurities into almost the entire surface of cell region 10 and other necessary portions by, for example, ion implantation. As ion implantation conditions at this time, for example, ion species: boron, dose amount: about 3 × 10 ¹³ / cm ² , and implantation energy: about 75 KeV can be exemplified as preferable ones. Thereafter, the unnecessary P-type body region introduction resist film is removed by ashing or the like.

Further, an N + type emitter region introduction resist film is formed on the surface 1a of the semiconductor wafer 1 by ordinary lithography. Using this N + type emitter region introduction resist film as a mask, N + type impurities are introduced into almost the entire upper surface of the P type body region 15 of the linear active cell region 40a by, for example, ion implantation, thereby forming an N + type impurity. An emitter region 12 is formed. As ion implantation conditions at this time, for example, ion species: arsenic, dose amount: about 5 × 10 ¹⁵ / cm ² , and implantation energy: about 80 KeV can be exemplified as preferable ones. Thereafter, the resist film for introducing an N + type emitter region that has become unnecessary is removed by ashing or the like.

  Next, as shown in FIG. 21, a PSG (Phosphosilicate Glass) film, for example, is formed as the interlayer insulating film 26 on the almost entire surface 1a of the semiconductor wafer 1 by, for example, CVD (thickness is). For example, about 600 nm). As the material of the interlayer insulating film 26, in addition to the PSG film, a BPSG (Borophosphosilicate Glass) film, an NSG (Non-doped Silicate Glass) film, an SOG (Spin-On-Glass) film, or a composite film thereof is preferable. Can be exemplified.

Next, as shown in FIG. 22, a contact groove forming resist film 28 is formed on the surface 1a of the semiconductor wafer 1 on the interlayer insulating film 26 by ordinary lithography. Subsequently, the contact groove 11 (or contact hole) is formed by, for example, anisotropic dry etching or the like (gas system is, for example, Ar / CHF ₃ / CF ₄ or the like).

Thereafter, as shown in FIG. 23, the resist film 28 that has become unnecessary is removed by ashing or the like. Subsequently, the contact groove 11 (or contact hole) is extended into the semiconductor substrate by, for example, anisotropic dry etching. As a gas system at this time, for example, a Cl ₂ / O ₂ system gas can be exemplified as a suitable one.

Next, as shown in FIG. 24, for example, a P + type body contact region 25 is formed by ion implantation of a P type impurity through the contact groove 11. Here, as ion implantation conditions, for example, ion species: BF ₂ , dose amount: about 5 × 10 ¹⁵ / cm ² , and implantation energy: about 80 KeV can be exemplified as preferable examples.

Similarly, for example, a P + type latch-up prevention region 23 is formed by ion implantation of a P type impurity through the contact groove 11. Here, as ion implantation conditions, for example, ion species: boron, dose: about 5 × 10 ¹⁵ / cm ² , and implantation energy: about 80 KeV can be exemplified as preferable examples.

  Next, as shown in FIG. 25, for example, an aluminum-based electrode film 8 (which becomes the metal emitter electrode 8) is formed by sputtering or the like. Specifically, for example, the following procedure is executed. First, a TiW film (for example, a thickness of about 200 nm) is formed as a barrier metal film on almost the entire surface 1a of the semiconductor wafer 1 by, for example, sputtering film formation (many portions of titanium in the TiW film are Subsequent heat treatment moves to the silicon interface to form silicide and contributes to improvement of contact characteristics, but these processes are complicated and are not shown in the drawing).

Subsequently, for example, silicide annealing is performed for about 10 minutes in a nitrogen atmosphere at about 600 degrees Celsius. Subsequently, aluminum is used as a main component (for example, several percent of silicon is added, and the rest is aluminum) by sputtering, for example, so as to fill the contact groove 11 almost over the entire surface of the barrier metal film. For example, a thickness of about 5 micrometers is formed. Subsequently, the metal emitter electrode 8 made of an aluminum metal film and a barrier metal film is patterned by normal lithography (for example, Cl ₂ / BCl ₃ as a dry etching gas system). Furthermore, as a final passivation film, for example, an organic film (for example, a thickness of about 2.5 micrometers) or the like containing polyimide as a main component is applied to almost the entire device surface 1a of the wafer 1, and by normal lithography, The emitter pad 9 and the gate pad 6 shown in FIG. 6 are opened.

  As a result, the front surface device forming process ends, and the process proceeds to the back surface process or the like.

5. Description of backside device formation process and the like related to the IGBT of the embodiment of the present application (mainly FIGS. 26 to 30)
In this section, following the section 4, a back surface device formation process and the like related to the IGBT according to the embodiment of the present application will be described.

  FIG. 26 is a device sectional view in the manufacturing process (N-type field stop region introduction step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 27 is a device sectional view in the manufacturing process (back grinding step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 28 is a device sectional view in the manufacturing process (N-type buffer region introduction step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. FIG. 29 is a device sectional view in the manufacturing process (P + type collector region introduction step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. 30 is a device sectional view in the manufacturing process (metal collector electrode formation step) corresponding to FIG. 8 for describing the manufacturing method corresponding to the device structure of the one embodiment of the present application. Based on these, the back surface device formation process regarding the IGBT of the one embodiment of the present application will be described.

As shown in FIG. 26, for example, by implanting protons (hydrogen ions) from the surface 1a side of the wafer 1, for example, 10 μm over almost the entire surface of the N − -type drift region 20 at a position of about 50 μm from the substrate surface. An N-type field stop region 42 having a certain thickness is introduced. Here, as irradiation conditions, for example, ion species (implanted particles): proton (hydrogen ions), implantation method: almost vertical implantation, implantation energy: about 4.3 MeV, single dose amount: about 1 × 10 ¹³ / cm ² The number of times of implantation: about 2 times can be exemplified as a suitable one. For example, an industrial cyclotron can be used as the driving device. The implanted particles may be helium ions or the like in addition to hydrogen ions.

  Subsequently, for example, proton activation annealing is performed at about 400 to 500 degrees Celsius.

  Next, as shown in FIG. 27, a back grinding process (chemical etching or the like for removing damage on the back surface is also performed if necessary) is performed on the back surface 1b of the wafer 1 in the drawing. The film is thinned by grinding or the like to the back grinding position 43 indicated by the broken line. Here, the final thickness of the wafer 1 is, for example, an original wafer thickness of about 800 micrometers (preferably about 1000 to 450 micrometers), for example, 200 to 30 micrometers. Thin film to the extent. For example, if the withstand voltage is about 600 volts, the final thickness is about 70 micrometers (the lower limit is defined by the required withstand voltage).

Next, as shown in FIG. 28, for example, ion implantation is performed on almost the entire surface of the thinned wafer 1 from the back surface 1b side, so that the surface region of the back surface 1b of the wafer 1 (before introduction) The N-type buffer region 19 is introduced into the N-type drift region 20). Here, as ion implantation conditions, for example, ion species: phosphorus, implantation method: almost vertical implantation, implantation energy: about 350 KeV, single dose: about 7 × 10 ¹² / cm ² , number of implantation: one time is preferable It can be illustrated as a thing.

Next, as shown in FIG. 29, for example, ion implantation is performed on the substantially entire surface from the back surface 1b side of the wafer 1 to thereby introduce the surface region of the back surface 1b of the wafer 1 (introduction of the N-type buffer region 19). Previously, a P + collector region 18 is introduced into the N− drift region 20). Here, as ion implantation conditions, for example, ion species: boron, implantation method: almost vertical implantation, implantation energy: about 40 KeV, single dose: about 3 × 10 ¹³ / cm ² , implantation number: one time is preferable It can be illustrated as a thing.

Subsequently, activation annealing is performed on the P + type collector region 18 on almost the entire back surface 1b of the wafer 1 (the activation rate is, for example, about 40%, and a preferable range is about 30% to 64%). Here, as annealing conditions (laser irradiation conditions), for example, annealing method: laser irradiation from the back surface 1b side of the wafer 1, wavelength: 527 nm, pulse width: about 100 ns, energy density: about 1.8 J / cm ² , Illumination method: two-pulse method, delay time of both pulses: about 500 ns, pulse overlap ratio: about 50% can be exemplified as preferable examples.

  By these processes, N between the N-type field stop region 42 and the N-type buffer region 19 from the vicinity of the boundary (the boundary between the N-type buffer region 19 and the N− type drift region 20) along the N-type buffer region 19. The crystal defect due to the back surface ion implantation remains in the portion of the − type drift region 20 adjacent to the boundary, and the crystal defect region 41 is formed.

  Next, as shown in FIG. 30, the metal collector electrode 17 is formed on almost the entire back surface 1b of the semiconductor wafer 1 by, for example, sputtering film formation (see FIG. 33 and its description for specific details). ). Thereafter, it is divided into chip regions of the semiconductor wafer 1 by dicing or the like, and sealed in a package as necessary, thereby completing the device.

6). Description of Modification (Full Active Cell Region) of IGBT Cell Structure of One Embodiment of the Present Application (Mainly FIGS. 31 and 32)
In the description of the sections 2 to 5, the IE type trench gate IGBT is mainly described as an example. However, each embodiment of the present application has other unit cell structures, for example, a unit of a full active type trench gate IGBT. Needless to say, the present invention can also be applied to a cell structure. Therefore, in this section, the unit cell structure of the fully active trench gate IGBT will be described.

  FIG. 31 is an enlarged top view (corresponding to FIG. 7 in section 3) of the cell region internal cutout region R3 of FIG. 6 regarding a modification (full active cell region) of the IGBT cell structure of the one embodiment of the present application. . 32 is a device cross-sectional view (corresponding to FIG. 8 of section 3) corresponding to the D-D ′ cross section of FIG. 31. Based on these, a modified example (full active cell region) of the cell structure of the IGBT according to the embodiment of the present application will be described.

  As shown in FIG. 31, the cell region 10 is mainly composed of linear active cell regions 40a repeatedly arranged in the horizontal direction (the entire region of the linear unit cell region 40 is a linear active cell region 40a). . A trench gate electrode 14 is disposed between the linear unit cell regions 40, and a linear contact groove 11 (or contact hole) is disposed in the center of the linear unit cell region 40. Linear N + type emitter regions 12 are provided in the linear unit cell regions 40 on both sides of the contact groove 11.

  Next, FIG. 32 shows a D-D ′ cross section of FIG. 31. As shown in FIG. 32, in the semiconductor region of the back surface 1b of the semiconductor chip 2, a P + type collector region 18 and an N type buffer region 19 are formed so as to be in contact with the top and bottom, and on the back surface 1b of the semiconductor chip 2. The metal collector electrode 17 is formed. That is, as described above, the N-type buffer region 19 is provided in the N-type drift region 20 inside thereof so as to be in contact with the P + type collector region 18. Further, a crystal defect region 41 is provided along the N-type buffer region 19 and over the N − -type drift region 20 in the vicinity of the outside, and further along the crystal defect region 41, Also, the N-type drift region 20 on the first main surface side is provided with an N-type field stop region 42 having a higher concentration than this.

  In the linear unit cell region 40, an N-type hole barrier region 24 is formed in order from the bottom on the N − type drift region 20 (surface side semiconductor region of the semiconductor substrate) on the surface 1 a (first main surface) side of the semiconductor chip 2. , A P-type body region 15 and an N + -type emitter region 12 are provided. An interlayer insulating film 26 is formed on the surface 1a of the semiconductor chip 2, and a contact trench 11 (or contact hole) extending inside the semiconductor substrate is formed in the interlayer insulating film 26 portion in the linear unit cell region 40. A P + type body contact region 25 and a P + type latch-up prevention region 23 are provided from the top in the bottom semiconductor region such as the contact groove 11. The P-type body region 15 and the N + -type emitter region 12 are connected to the metal emitter electrode 8 provided on the interlayer insulating film 26 via the contact groove 11 and the like.

  Here, the N-type hole barrier region 24 is a barrier region for preventing holes from flowing into the passage from the N− type drift region 20 to the N + type emitter region 12, and the impurity concentration thereof is N + type emitter region. It is lower than 12 and higher than the N − type drift region 20. The existence of the N-type hole barrier region 24 effectively allows holes accumulated in the N− type drift region 20 to enter the emitter passage (passage from the N− type drift region 20 to the P + type body contact region 25). Can be blocked. Needless to say, the N-type hole barrier region 24 is not essential.

  As described above, the full active cell region 10 has a structure without the linear inactive cell region 40i in FIG. 4, and the entire linear unit cell region 40 in FIG. 3 is the linear active cell region. 40a.

7). Description of Modified Example (Aluminum Doped Contact) of Backside Detailed Structure of IGBT of One Embodiment of the Present Application (Mainly FIG. 33)
The examples in this section are applicable to all other examples except this section. Needless to say, the present invention can also be applied to IGBTs having other general surface-side structures.

  In this section, for convenience of explanation, the device structure will be described according to the example in Section 3, and the process will be briefly described with reference to Section 5.

  In the following, the IE-type trench gate IGBT will be described in detail. However, the back surface structure is not limited to the IE-type IGBT or the trench gate IGBT (full active trench gate IGBT), but other forms. Needless to say, the present invention can also be applied to other IGBTs (for example, planar IGBTs).

  FIG. 33 is a local detailed cross-sectional view of a device back surface for explaining a device structure of a modified example (aluminum doped contact) of the back surface detailed structure of the IGBT according to the embodiment of the present application and a manufacturing method thereof.

FIG. 33 shows an enlarged cross-sectional view of the back side and its vicinity of the semiconductor chip 2 in FIG. As shown in FIG. 33, a relatively thin P-type semiconductor region (for example, a thickness of about 0.04 to 0.1 micrometers) is formed in the semiconductor region at the lower end of the P + type collector region 18 on the back surface side of the semiconductor substrate 2. That is, an aluminum doped region 30 (second conductivity type high concentration collector contact region) is provided, and this impurity concentration (for example, about 1 × 10 ¹⁹ / cm ³ ) is higher than the impurity concentration of the P + type collector region 18. A metal collector electrode 17 is formed on the back surface 1 b of the semiconductor substrate 2 in contact with the aluminum doped region 30. For example, the metal collector electrode 17 has the following configuration from the side closer to the semiconductor substrate 2. That is, an aluminum back metal film 17a (for example, about 600 nm thick), a titanium back metal film 17b (for example, about 100 nm thick), and a nickel back metal film 17c (for example, 600 nm thick) that are impurity sources of the aluminum doped region 30. And a gold back metal film 17d (for example, a thickness of about 100 nm).

  Next, the production method will be briefly described. In the process of FIG. 30 in section 5, that is, during the sputtering film formation, the aluminum back metal film 17a, the titanium back metal film 17b, the nickel back metal film 17c, and the gold back metal film 17d are sequentially formed by sputtering. The heat generated at this time introduces aluminum into the silicon substrate, and the aluminum doped region 30 is formed. After that, when divided into chip regions of the semiconductor wafer 1 by dicing or the like, it becomes as shown in FIG. 8 (the detailed structure is not clearly shown in FIG. 8).

  In each of the embodiments of the present application, holes are accumulated on the emitter side in the on state to promote electron injection. On the other hand, the PN diode on the back collector side is a diode having low injection efficiency to reduce switching loss. Here, in order to form a backside diode with low injection efficiency, the ratio of the carrier concentration Qp of the P + type collector region 18 to the carrier concentration Qn of the N type field stop region 19 (hereinafter referred to as “carrier concentration ratio”), that is, ( It is effective to reduce Qp / Qn). However, for this reason, if the carrier concentration Qp of the P + type collector region 18 is lowered too much, the characteristics of the back surface metal contact deteriorate. Therefore, in this example, an aluminum doped region 30 having a higher impurity concentration than the P + type collector region 18 introduced from the aluminum film on the back surface is provided. As a carrier concentration ratio, for example, about 1.5 (as a range, for example, about 1.1 to 4) can be exemplified as a suitable one.

  In this section, the back surface metal structure and the like (including the contact region) suitable for the case where the PN diode on the back surface collector side is particularly desired to have a low injection efficiency are exemplified. However, as the back surface metal structure and the like, the aluminum doped region 30 and the like Needless to say, even if the aluminum back surface metal film 17a is not provided, it may be formed of a combination of other metal films.

8). Description of Modification (Epitaxial Process) of Surface Device Formation Process Related to IGBT of One Embodiment of the Present Application (Mainly FIGS. 34 and 35)
While sections 4 and 5 described non-epitaxy processes that do not use an epitaxy process, the various devices described herein can also be fabricated by various epitaxy processes that use an epitaxy process. In this section, an example of an epitaxy process corresponding to sections 4 and 5 is described.

  FIG. 34 is a device sectional view in the manufacturing process (N-type field stop region introduction step) corresponding to FIG. 8 for describing the modification (epitaxial process) of the surface device formation process related to the IGBT according to the embodiment of the present invention. It is. FIG. 35 is a device cross section in the manufacturing process (N-type silicon epitaxial region forming step) corresponding to FIG. 8 for describing the modification (epitaxial process) of the surface device forming process related to the IGBT according to the embodiment of the present invention. FIG. Based on these, a modification (epitaxial process) of the surface device formation process related to the IGBT of the one embodiment of the present application will be described.

First, an N− type silicon single crystal (for example, wafers of various diameters such as 150φ, 100φ, 300φ, 450φ, etc.) with a phosphorus concentration of about 2 × 10 ¹⁴ / cm ³ and a resistivity of 22 Ωcm to 30 Ωcm may be prepared. Here, for example, a wafer by the CZ (Czochralski) method is most suitable, but a wafer by the FZ (Floating Zone) method may be used.

Next, as shown in FIG. 34, for example, ion implantation is performed on almost the entire surface from the surface 1a side of the wafer 1 to thereby form a semiconductor surface region (N− type drift region 20 on the surface 1a of the wafer 1). An N-type field stop region 42 is introduced into the N-type single crystal silicon substrate 1s to be formed. Here, as ion implantation conditions, for example, ion species: phosphorus, implantation method: almost vertical implantation, implantation energy: about 75 KeV, one dose amount: about 5 × 10 ¹¹ / cm ² , implantation number: one time is preferable It can be illustrated as a thing.

  Subsequently, activation annealing (for example, 1200 degrees Celsius, about 30 minutes) is performed on the N-type field stop region 42 as necessary.

  Next, as shown in FIG. 35, by epitaxial growth on the surface 1a side of the wafer 1, assuming that the N-type silicon epitaxial region 1e (withstand voltage of about 600 volts) has a thickness of, for example, about 50 micrometers and a resistivity of For example, about 22 Ωcm.

  Thereafter, the processes of FIGS. 9 to 25 described in the section 4 are executed, and the processes of FIGS. 27 to 30 described in the section 5 are further executed.

9. Description of a basic example of a power diode according to an embodiment of the present application (a PIN diode having a crystal defect region and an intermediate field stop region) (mainly FIG. 36 and FIG. 37)
In sections 2 to 8, the basic concept of the present invention was applied to the IGBT, but in sections 9 to 13, the case where it was applied to a diode will be mainly described. .

  In this section, the overall structure of a PIN diode chip having a crystal defect region and an intermediate field stop region and the structure of a main device region are described. This is because the PIN diode does not have a repetitive structure, and the main PN junction has only a main part (center part) and an end part. Therefore, here, a description will be given by extracting a portion that is a main portion of the main PN junction and corresponds to a unit cell portion of the cell region in the case of the cell structure. In the device structure described in sections 11 and 12, since the surrounding structure exists in the same manner as the IGBT, the unit cell portion is extracted and described in the same manner as the IGBT.

  The peripheral structure is almost the same as that described in FIGS. 3 and 4 except that there is no dummy cell as described in FIG.

  36 is an overall top view of the diode chip corresponding to FIG. 6 (corresponding to FIG. 6 in section 3) relating to a basic example (a PIN diode having a crystal defect region and an intermediate field stop region) of a power diode according to an embodiment of the present application. ). FIG. 37 is a device sectional view of the main device region corresponding to the F-F ′ section of FIG. 36 (corresponding to FIG. 8 of section 3). Based on these, a basic example of a power diode according to an embodiment of the present application (a PIN diode having a crystal defect region and an intermediate field stop region) will be described.

  As shown in FIG. 36, an annular guard ring 3 made of, for example, an aluminum wiring layer is provided on the outer peripheral portion of the upper surface 1a of the PIN diode device chip 2, and an annular guard ring 3 is provided on the inner side thereof. Several (single or plural) annular field plates 4 (for example, composed of the same aluminum-based wiring layer as before) connected to a floating field ring or the like are provided. Inside the field plate 4 (floating field ring 36 in FIG. 4), a main PN junction region 10 is provided in the main part of the inner region of the upper surface 1a of the chip 2, and the main PN junction region 10 is For example, the metal anode electrode 44 composed of the same aluminum-based wiring layer as before is covered up to the vicinity of the outside. A central portion of the metal anode electrode 44 is an anode pad 45 for connecting a bonding wire or the like.

  Next, FIG. 37 shows an F-F ′ cross section of the cell region internal cutout region R <b> 3 of FIG. 36. As shown in FIG. 37, an N-type cathode region 47 having a concentration higher than that of the N − -type drift region 20 is formed in the semiconductor region (N − -type drift region 20) of the back surface 1b of the semiconductor chip 2. A metal cathode electrode 17 is formed on the back surface 1 b of the chip 2. A crystal defect region 41 is provided along the N-type cathode region 47 and over the N − type drift region 20 in the vicinity of the outside, and further along the crystal defect region 41, Also, the N-type drift region 20 on the first main surface side is provided with an N-type field stop region 42 having a higher concentration than this.

  In the main PN junction region 10, a P-type anode region 46 is provided in the N − -type drift region 20 (surface-side semiconductor region of the semiconductor substrate) on the surface 1 a (first main surface) side of the semiconductor chip 2. An anode metal electrode 44 is formed on the surface 1a of the semiconductor chip 2, and the anode metal electrode 44 is connected to a P-type anode region 46 (ohmic contact).

10. Description of a basic manufacturing process regarding a basic example (a PIN diode having a crystal defect region and an intermediate field stop region) of the power diode of the embodiment of the present application (mainly FIGS. 38 to 43)
This section describes a diode manufacturing process (non-epitaxy process) that corresponds to that described in sections 4 and 5 for the IGBT manufacturing method.

  FIG. 38 is a device sectional view in the manufacturing process (P-type anode region introduction step) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. FIG. 39 is a device sectional view in the manufacturing process (metal anode electrode formation step) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. FIG. 40 is a device sectional view in the manufacturing process (N-type field stop region introduction step) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. FIG. 41 is a device cross-sectional view during the manufacturing process (back grinding process) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. FIG. 42 is a device sectional view in the manufacturing process (N-type cathode region introduction step) corresponding to FIG. 37 for describing the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. FIG. 43 is a device sectional view in the manufacturing process (metal cathode electrode formation step) corresponding to FIG. 37 for illustrating the manufacturing process regarding the basic example of the power diode of the one embodiment of the present application. Based on these, a basic manufacturing process relating to a basic example (a PIN diode having a crystal defect region and an intermediate field stop region) of the power diode of the one embodiment of the present application will be described.

First, an N-type silicon single crystal (for example, a wafer having various diameters such as 150φ, 100φ, 300φ, 450φ, etc.) having a phosphor concentration of about 2 × 10 ¹⁴ / cm ³ and having a resistivity of 22 Ωcm to 30 Ωcm is prepared. Here, for example, a wafer by FZ (Floating Zone) method is most suitable, but a wafer by CZ (Czochralski) method may be used.

  Next, as shown in FIG. 38, the semiconductor on the surface 1a of the wafer 1 is ion-implanted from the surface 1a side of the wafer 1 into the entire surface of the main PN junction region 10 by, for example, P-type impurities such as boron. A P-type anode region 46 is introduced into the surface region (inside the N-type single crystal silicon substrate 1s to be the N-type drift region 20).

  Next, as shown in FIG. 39, the anode metal electrode 44 is formed on the surface 1 a of the wafer 1 on the P-type anode region 46 in the same manner as the metal emitter electrode 8 of the previous section 4.

  Next, as shown in FIG. 40, an N-type field stop region 42 is formed in the N−-type drift region 20 as in FIG.

  Next, as shown in FIG. 41, as in FIG. 27 in the previous section 5, back grinding is performed to thin the wafer.

Next, as shown in FIG. 42, an N-type cathode region 47 is formed on the second main surface side surface region of the N − -type drift region 20 in the same manner as the N-type buffer region 19 of FIG. Form. Here, as ion implantation conditions, for example, ion species: phosphorus, implantation method: almost vertical implantation, implantation energy: about 125 KeV, one dose amount: about 1 × 10 ¹⁵ / cm ² , implantation number: one time is preferable. It can be illustrated as a thing.

Here, as the activation annealing conditions (laser irradiation conditions), for example, annealing method: laser irradiation from the back surface 1b side of the wafer 1, wavelength: 527 nm, pulse width: about 100 ns, energy density: 1.8 J / Suitable examples include about cm ² , irradiation method: two-pulse method, delay time of both pulses: about 500 ns, and pulse overlap ratio: about 50% to 66%.

  Next, as shown in FIG. 43, the metal cathode electrode 17 and the like are formed on the back surface 1b of the wafer 1 in the same manner as in FIG. The metal cathode electrode 17 and the like may be as shown in FIG.

  Thereafter, it is divided into chip regions of the semiconductor wafer 1 by dicing or the like, and sealed in a package as necessary, thereby completing the device.

11. Description of Modification 1 (MPS Diode Having a Crystal Defect Region and an Intermediate Field Stop Region) of the Power System Diode According to the One Embodiment of the Present Application (Mainly FIG. 44)
In this section, Modification 1 to the diode structure described in Section 9 will be described. Since there is no essential difference with respect to the manufacturing method as described in Section 10, the description will not be repeated here in principle.

  44 is a device cross section of a unit cell portion corresponding to the FF ′ cross section of FIG. 36 relating to Modification 1 (MPS diode having a crystal defect region and an intermediate field stop region) of the power diode of the one embodiment of the present application. FIG. Based on this, Modification 1 (MPS diode having a crystal defect region and an intermediate field stop region) of the power diode according to the embodiment of the present invention will be described.

  The unit cell region of the cell region 10 (FIG. 36) in this example generally has a circular P-type anode region 46 on the surface 1a of the semiconductor substrate 2 in the N − -type drift region 20 unlike the IGBT. The two-dimensional hexagonal close-packed lattice is distributed. Therefore, the P-type anode region 46 and the anode metal electrode 44 are in ohmic contact, but the portion without the P-type anode region 46 is a Schottky junction. The other structure is exactly the same as FIG.

12 Description of Modification 1 (SSD having a crystal defect region and an intermediate field stop region) of the power diode according to the embodiment of the present invention (mainly FIG. 45)
In this section, Modification 2 to the diode structure described in Section 9 will be described. Since there is no essential difference with respect to the manufacturing method as described in Section 10, the description will not be repeated here in principle.

  FIG. 45 is a device cross-sectional view of a unit cell portion corresponding to the FF ′ cross section of FIG. 36 regarding Modification 1 (SSD having a crystal defect region and an intermediate field stop region) of the power diode according to the embodiment of the present application. It is. Based on this, Modification 1 (SSD having a crystal defect region and an intermediate field stop region) of the power diode according to the embodiment of the present invention will be described.

  This example is a shallower and thinner impurity region compared to the P-type anode region 46 for relaxing the electric field concentration in the vicinity of the Schottky junction of the MPS diode described in section 11 (for example, P In this case, aluminum or the like is doped as a type impurity), that is, a P− type surface region 48 is added.

13. Description of modification of diode manufacturing process (refer mainly to FIG. 34 and FIG. 35)
In this section, the epitaxy process for the diode is described with reference to the manufacturing process for the IGBT (Section 8).

As in section 8, first, it may be a wafer of various diameters such as an N-type silicon single crystal (for example, a phosphorus concentration of about 2 × 10 ¹⁴ / cm ³ and a resistivity of 22 Ωcm to 30 Ωcm) such as 150φ, 100φ, 300φ, and 450φ. Prepare). Here, for example, a wafer by the CZ (Czochralski) method is most suitable, but a wafer by the FZ (Floating Zone) method may be used.

Next, as shown in FIG. 34, for example, ion implantation is performed on almost the entire surface from the surface 1a side of the wafer 1 to thereby form a semiconductor surface region (N− type drift region 20 on the surface 1a of the wafer 1). An N-type field stop region 42 is introduced into the N-type single crystal silicon substrate 1s to be formed. Here, as ion implantation conditions, for example, ion species: phosphorus, implantation method: almost vertical implantation, implantation energy: about 75 KeV, one dose amount: about 5 × 10 ¹¹ / cm ² , implantation number: one time is preferable It can be illustrated as a thing.

  Subsequently, activation annealing (for example, 1200 degrees Celsius, about 30 minutes) is performed on the N-type field stop region 42 as necessary.

  Next, as shown in FIG. 35, by epitaxial growth on the surface 1a side of the wafer 1, assuming that the N-type silicon epitaxial region 1e (withstand voltage of about 600 volts) has a thickness of, for example, about 50 micrometers and a resistivity of For example, about 22 Ωcm.

  Thereafter, the processes of FIGS. 38 and 39 described in the section 10 are executed, and further, the processes of FIGS. 41 to 43 described in the same section are executed.

14 General Considerations of the Present Application and Supplementary Explanations for Each Embodiment In this section, the general considerations of the present application and supplementary explanations for the embodiments of the present application (including modifications) are provided. Although the specific description will be given mainly by taking the IGBT as an example here, what is described here also applies to the diode as it is.

  As described in the beginning, an IGBT or the like having a higher concentration N-type buffer (Buffer) region than the N-type drift region (or N-type base region) in contact with the P-type collector region on the back side (diode of the diode). (In some cases, also referred to as an N-type high concentration region or an N-type contact region), defects due to ion implantation or the like for introducing a P-type collector region or an N-type buffer region into an N-type drift region near the N-type buffer region There is known a device configuration method for improving the switching speed by remaining the signal. Such an “ion implantation defect residual IGBT” improves the switching speed at the time of off by the residual crystal defect acting as a recombination center, while the depletion layer contacts the crystal defect at the time of off, There is a possibility of causing a side effect that leakage current increases.

  Therefore, in each of the embodiments described above, an independent N-type field stop region 42 is provided separately from the N-type buffer region 19 that forms the back-side PN junction that determines the hole injection efficiency. For this reason, in the off state, the depletion layer is at most a portion above the crystal defect region 41 of the N − type drift region 20 between the N type buffer region 19 and the N type field stop region 42 (N type field stop region). 42), the leakage current does not increase. This is because the crystal defect region 41 has an N distribution from the vicinity of the bottom of the N type buffer region 19 on the N type field stop region 42 side (that is, the vicinity of the boundary between the N type buffer region 19 and the N − type drift region 20). This is because the N− type drift region 20 between the type field stop region 42 and the N type buffer region 19 is distributed in a portion close to the boundary.

  The above also applies to diodes. That is, in the diode, the impurity structure on the back surface side is obtained by removing the P + type collector region 18 from the IGBT. Here, in the diode, the N-type cathode region 47 corresponds to the N-type buffer region 19 of the IGBT.

15. Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, a device using mainly an aluminum-based surface electrode has been described. However, the present invention is not limited thereto, and it goes without saying that the present invention can also be applied to devices using other metals.

  In the above-described embodiment, the IGBT and the diode mainly using the silicon substrate have been specifically described. However, the present invention is not limited thereto, and the SiC substrate, the GaN substrate, the GaAs substrate, and the InP substrate. Needless to say, the present invention can also be applied to those using the above.

  In the above-described embodiment, the device mainly having an N-type drift region has been specifically described. However, the present invention is not limited thereto, and it goes without saying that the device can also be applied to a device having a drift region of P-type. Yes.

  In the above-described embodiment, the flyback diode is specifically described mainly for the diode. However, the present invention is not limited thereto, and it goes without saying that the diode can be applied to other purposes.

  In the above-described embodiment, the defect caused by the ion implantation remains in the crystal defect region during the annealing process, but the present invention is not limited to this, and the ions of hydrogen ions, helium ions, other ions and particles are not limited thereto. It goes without saying that a new one may be formed by driving.

1 Semiconductor wafer 1a Wafer or chip surface (first main surface)
1b Back surface of wafer or chip (second main surface)
1e N-type silicon epitaxial region 1s N-type single crystal silicon substrate 2 Semiconductor chip (semiconductor substrate)
3 Guard ring 4 Field plate 5 Metal gate electrode 6 Gate pad 7 Metal gate wiring 8 Metal emitter electrode 9 Metal emitter pad 10 Cell region (main PN junction region of diode)
11 Contact groove (or contact hole)
12 N + type emitter region 14 Trench gate electrode 15 P type body region (P type channel region)
16 P-type floating region 17 Metal collector electrode (or metal cathode electrode)
17a Aluminum back surface metal film 17b Titanium back surface metal film 17c Nickel back surface metal film 17d Gold back surface metal film 18 P + type collector region 19 N type buffer region 20 N− type drift region 21 Trench 22 Gate insulating film 23 P + type latch-up prevention region 24 N-type hole barrier region 25 P + type body contact region 25d P + type body contact region of dummy cell 25p P + type body contact region of cell peripheral junction region 25r P + type body contact region of floating field ring 26 Interlayer insulating film 27 Polysilicon film 28 Contact Groove forming resist film 30 Aluminum doped region (high concentration collector contact region or high concentration back contact region)
31 Resist film for introducing N-type hole barrier region 32 Hard mask film for forming trench 33 Resist film for processing trench hard mask film 34 Dummy cell region (linear dummy cell region)
35 Cell peripheral junction area 36 Floating field ring (field limiting ring)
38 Thin silicon oxide film for ion implantation 40 Linear unit cell region 40a Linear active cell region 40aa Active section 40i Linear inactive cell region 41 Crystal defect region 42 N-type field stop region 43 Back grind position 44 Anode metal electrode 45 Anode opening 46 P-type anode region 47 N-type cathode region 48 P-type surface region A Anode terminal C Collector terminal D, Da, Db, Dc, Dd, De, Df Flyback diode E Emitter terminal G Gate terminal K Cathode terminal M Motor Pa, Pb, Pc, Pd, Pe, Pf IGBT and diode pair Q, Qa, Qb, Qc, Qd, Qe, Qf IGBT
R1 Cell region edge cutout region R3 Cell region internal cutout region R5 Linear unit cell region main part and its peripheral cutout region Vs DC power supply Wa Width of linear active cell region Wi Width of linear inactive cell region

Claims (12)

(A) a semiconductor substrate having a first main surface, a second main surface, and having a first conductivity type drift region therein;
(B) a channel region of a second conductivity type on the first main surface side and opposite to the first conductivity type provided in the drift region;
(C) on the first main surface side, the first conductivity type emitter region provided in the channel region;
(D) on the second main surface side, the second conductivity type collector region provided in the drift region;
(E) a buffer region of the first conductivity type located on the first main surface side with respect to the collector region and provided in the drift region;
(F) a crystal defect region located on the first main surface side with respect to the buffer region and provided in the drift region;
(G) a field stop region of the first conductivity type located in the first main surface side with respect to the crystal defect region and provided in the drift region;
(H) a metal collector electrode provided on the second main surface of the semiconductor substrate and connected to the collector region;
Have
The field stop region has a higher concentration than the first region located in the drift region and between the field stop region and the channel region,
The buffer area has a higher concentration than the first area,
The buffer device is a semiconductor device having a concentration higher than that of the field stop region. The semiconductor device according to claim 1,
The semiconductor device, wherein a carrier concentration in the collector region is higher than a carrier concentration in the buffer region. The semiconductor device according to claim 1,
The semiconductor device, wherein a carrier concentration ratio between the collector region and the buffer region is 1.1 to 4. The semiconductor device according to claim 1,
The field stop region is a semiconductor device having a film thickness larger than that of the buffer region. The semiconductor device according to claim 1,
A semiconductor device, wherein the field stop region contains hydrogen or helium. The semiconductor device according to claim 1, further comprising:
(I) A semiconductor device having a high concentration collector contact region which is provided on the metal collector electrode side of the collector region, has the same conductivity type as the collector region, and has a higher impurity concentration. The semiconductor device according to claim 6, wherein the high concentration collector contact region is a region doped with aluminum. The semiconductor device according to claim 6,
A portion of the metal collector electrode that is in contact with the high-concentration collector contact region is a semiconductor device that is a metal film containing aluminum as a main component. The semiconductor device according to claim 1,
The semiconductor device is a single crystal silicon substrate by an FZ method. The semiconductor device according to claim 1, further comprising:
(J) a first groove in the semiconductor substrate from the first main surface toward the second main surface;
(K) a gate oxide film on the first groove;
(L) a gate electrode on the gate oxide film;
Have
The emitter region is in contact with the first groove;
The semiconductor device, wherein the channel region is in contact with the first groove. The semiconductor device according to claim 1,
A semiconductor device which is an IE-type trench gate IGBT. The semiconductor device according to claim 1,
The semiconductor device, wherein the first region is a hole barrier region.

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