JP5532754B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an insulated gate bipolar transistor (hereinafter referred to as IGBT) which is highly effective when a large-diameter FZ type semiconductor substrate (hereinafter referred to as wafer) having a diameter of 8 inches or more is used. .

  With the development of technical fields such as electric vehicles, solar power generation, and wind power generation, it is assumed that the demand for IGBTs is likely to increase significantly in the near future. Therefore, the silicon substrate (silicon wafer) has been increased in diameter (from 6 inch diameter to 8 inch diameter) for the purpose of cost reduction by increasing the efficiency of the production line and increasing the number of chips per wafer.

  When manufacturing power semiconductor devices, it is more expensive as a raw material for silicon wafers than the CZ (Czochralski) method, but it is easy to obtain high purity and high resistivity, and high breakdown voltage characteristics are high. A silicon single crystal ingot crystal-grown by the obtained FZ (floating zone) method is used. However, since the silicon crystal growth by the FZ method is a method in which the production efficiency becomes worse as the diameter is increased, the FZ silicon single crystal having an 8-inch diameter is considerably larger than the 6-inch diameter, which is currently widely used. It becomes expensive.

  On the other hand, when the well-known FS (Field Stop) -IGBT is manufactured by the conventional manufacturing method of manufacturing the IGBT using the FZ-wafer sliced from the single crystal ingot by the FZ method, the final finishing is performed. The required thickness of the wafer is about 180 μm at a withstand voltage of 1800 V, about 120 μm at a withstand voltage of 1200 V, and about 60 μm at a withstand voltage of 600 V. However, in order to prevent wafer cracking and chipping in the manufacturing process, the initial thickness of the wafer to be introduced into the wafer process for manufacturing the semiconductor device requires 600 μm or more in the case of a 6-inch diameter, and is actually about 625 μm. Thickness is preferred.

  In the case of an 8-inch diameter, at least 700 μm or more is required, and generally a thickness of about 725 μm is preferable. That is, most of the difference between the thickness of the input wafer and the thickness of the finished wafer is discarded due to grinding chips, loss due to polishing and lapping, and dissolution due to etching. Of course, when a 6-inch diameter wafer is used, there is a difference between the thickness of the input wafer and the thickness of the finished wafer, and most of them are discarded.

The structural feature of the FS-IGBT is that an n-type FS layer and a p-type collector layer whose impurity concentration and width are controlled are provided particularly on the back surface side of the n ⁻ drift layer. The characteristic feature of the FS-IGBT obtained by such a structure is that the thickness of the high resistance n ⁻ drift layer for obtaining the required breakdown voltage can be reduced, and the on-voltage is reduced. is there. In the FS-IGBT, the impurity concentration and thickness of the p-type collector layer and the n-type FS layer are adjusted so that the device characteristics are determined by the carrier injection efficiency from the collector side. Therefore, there is a feature that it is not particularly necessary to further reduce the turn-off time (or switching loss) by introducing a lifetime killer. On the other hand, a PT (punch-through) IGBT manufactured by depositing an n ⁺ layer and a high resistance n ⁻ drift layer by epitaxial growth on a low-resistance p-type semiconductor substrate has a low on-voltage but introduces a lifetime killer. Usually, it is required to reduce the turn-off time. In addition, in an NPT-IGBT that requires a p collector layer whose injection efficiency is controlled and an n ⁻ drift layer that is thicker than the maximum depletion layer width that extends at the off voltage, it is necessary to introduce a lifetime killer as in the case of the FS-IGBT. Although it is not necessary, since the n ⁻ drift layer is thick, the on-voltage tends to increase. That is, it can be said that FS-IGBT is an IGBT incorporating the advantages of both PT-IGBT and NPT-IGBT.

  On the other hand, in order to form a semiconductor integrated circuit element provided with a high breakdown voltage element integrally, a low impurity concentration FZ silicon substrate is bonded to a 6 inch diameter CZ silicon substrate having a thickness of 600 μm with a thermal oxide film interposed therebetween. There is a description relating to a method of manufacturing a semiconductor device in which an FZ silicon substrate is polished and thinned to form an SOI substrate, and a semiconductor region is formed on the FZ silicon substrate (Patent Document 1).

In addition, an IGBT semiconductor substrate that requires a thick high resistivity layer for high withstand voltage is made a manufacturing method that does not use a method in which defects easily occur on the surface portion of the IGBT structure, such as an epitaxial method or a thermal diffusion method. . Specifically, a semiconductor substrate bonding technique is used. For example, there is a description of a method for manufacturing a high voltage IGBT using a semiconductor substrate in which an n ⁻ silicon wafer is bonded onto an n ⁺ layer of a p ⁺ silicon wafer on which an n ⁺ epitaxial layer is grown (Patent Document 2). .

  After performing ion implantation for forming the FS layer on the back surface of the silicon wafer, attaching an insulating support substrate to the back surface, forming the surface structure of the semiconductor device on the front surface side, and then removing the support substrate, substrate There is a description relating to reducing the wafer cracking and increasing the yield rate by using a method for manufacturing a semiconductor device having a step of forming a p-type collector layer on the surface from which P is removed (Patent Documents 3 and 4).

  After forming the impurity diffusion layer on the surface of the semiconductor substrate, it has a step of thinning the back surface, and before performing the diffusion layer forming step requiring heat treatment in the range of at least 700 ° C. to 950 ° C. on the back surface side, There is a description relating to the formation of oxide films on both surfaces of the semiconductor substrate having a thickness that does not allow impurities to penetrate due to wrap-around diffusion from the surface side (Patent Document 5).

JP 11-251562 A (summary) JP-A-6-177390 Japanese Patent No. 3969256 Japanese Patent Laid-Open No. 2002-261281 JP 2008-103562 A

  However, as described above, if a thin silicon wafer required for the withstand voltage of the FS-IGBT is used as the initial wafer thickness in the wafer process, the wafer is frequently cracked and chipped, resulting in an extremely low yield rate. To do. Therefore, the thickness of a wafer to be put into an actual production line is required to be 600 μm or more for a 6-inch diameter wafer and 700 μm or more for an 8-inch diameter wafer to prevent cracking. Moreover, when cutting a wafer by slicing from a crystal ingot, for example, in order to cut a wafer having a thickness of 725 μm, as shown in FIG. There is also 330 μm. As described above, since the final wafer thickness required for the IGBT having a withstand voltage of 1200 V is 120 μm, a difference of 605 μm between 725 μm and 120 μm is a loss. Therefore, when the wafer thickness of the 1200V IGBT is 120 μm, the total thickness loss is 935 μm from the sum of 330 μm and 605 μm.

  The present invention has been made in view of the above points, and an object of the present invention is to reduce the thickness of an FZ wafer out of the conventional wafers to be used in a production line using an FZ wafer. Another object of the present invention is to provide a method for manufacturing a semiconductor device capable of suppressing the frequency of cracking and chipping of a wafer to the same level as in the past.

According to the present invention, an FZ wafer cutting step of cutting an FZ wafer having a thickness greater than the required thickness for the design withstand voltage of a semiconductor device from a silicon crystal ingot formed by a floating zone method, and silicon formed by a Czochralski method After a CZ wafer cutting step for cutting a CZ wafer from a crystal ingot, a wrapping step for wrapping both the main surface and the other main surface of each of the cut FZ wafer and CZ wafer, and after the wrapping step, Etching process for removing damage due to lapping on both of the one main surface and the other main surface of the CZ wafer, and the etching for removing damage due to the lapping after the lapping process The FZ wafer is formed without performing a process. After the first mirror-finishing step, in which the main surface of the CZ wafer is mirror-finished by polishing, and the etching step for removing damage caused by the lapping, the one main surface of the CZ wafer is polished to become a mirror-surface. And a bonding step in which the one main surface that is the mirror surface of the FZ wafer and the one main surface that is the mirror surface of the CZ wafer are bonded together to form a bonded wafer. , A third mirror surface process in which the other surface of the FZ wafer of the bonded wafer is ground to a predetermined thickness and mirror processed, and the other of the FZ wafer mirrored in the third mirror surface process A semiconductor region forming step for forming a required semiconductor region on the surface, and a grinding step for grinding the CZ wafer from the other surface and exposing the one main surface of the FZ wafer to a predetermined thickness When, A method of manufacturing a semiconductor device, which comprises.

The required semiconductor region is preferably a MOS surface structure.
It is desirable to add a step of forming a collector layer by ion implantation on the exposed FZ wafer surface after the step of scraping off the CZ wafer from the other surface.

More preferably, the additional step is a step of forming a field stop layer and a collector layer on the exposed FZ wafer surface by ion implantation .

  According to the present invention, even if the thickness of the FZ wafer among the wafers to be input is made thinner than the conventional one in the production line using the FZ wafer, the frequency of cracking of the wafer can be suppressed to the same level as the conventional one. A method of manufacturing a semiconductor device that can be provided can be provided.

It is a perspective view of a silicon crystal block showing a process from cutting out and slicing a crystal block to forming a wafer from a silicon single crystal ingot. It is sectional drawing which shows the chamfering and lapping process of the circumferential edge of the cut-out wafer. FIG. 6 is a cross-sectional view showing mechanical chemical polishing, surface treatment of FZ wafer and CZ wafer, bonding, and chamfering process of FZ wafer. It is sectional drawing which shows the formation process of the scraping of the back side CZ wafer, the back side FS layer, and the collector layer from the surface etching of the FZ wafer. It is an expanded principal part sectional view of FS-IGBT. It is sectional drawing which shows the thickness of the FZ wafer before a wafer process input, and the cutting allowance of the wafer surface. FIG. 5 is a cross-sectional view showing mechanical chemical polishing, surface treatment of a CZ wafer coated with an FZ wafer and an insulating film, bonding, and a chamfering process of the FZ wafer. It is sectional drawing which shows the formation process of scraping of the CZ wafer coat | covered with the insulating film of the back surface side from the surface etching of an FZ wafer, and a back surface side FS layer and a collector layer.

  Embodiments of a method for manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.

  In a silicon single crystal used as a material for a silicon semiconductor substrate (hereinafter simply referred to as a wafer) used in a silicon semiconductor device, a silicon seed crystal is immersed in a silicon melt in a crucible, and the seed crystal is gradually pulled to grow the single crystal. The CZ (Czochralski) method and a high-frequency coil provided around a round bar-shaped silicon polycrystal are sequentially moved downward while heating and melting the polycrystal into a disk shape, thereby forming a single crystal FZ ( The floating zone method is known.

  The silicon single crystal ingot by the above-mentioned FZ method formed by crystal growth for an 8-inch wafer having a high resistivity of 400 Ωcm or less is cut off at its end and cut into a round bar block 100 (FIG. 1 (a)). Measure the conductivity type, resistivity, etc., respectively. The circumferential portion of the round bar block 100 is ground and shaped into an 8-inch diameter, and a notch 101 or an orientation flat is formed in order to make the crystal orientation clear (FIG. 1 (b)).

  Slice with a wire saw 102 or ID blade saw. For example, as shown in FIG. 6, the sliced thickness is 280 + 100, and the FZ wafer is 380 μm (FIG. 1C). In the case of an 8-inch wafer, a wafer whose thickness after lapping is less than 300 μm has a risk of jumping out of the template during processing and being damaged. Therefore, the thickness was reduced to 300 μm by lapping each side by 40 μm by lapping. For example, at the stage of this lapping process, it cannot be suddenly processed to a thin thickness as 180 μm necessary for an FS-IGBT with a 1800 V breakdown voltage.

In the conventional method, the wafer thickness after this slicing is 725 + 160, which is 885 μm.
The circumferential portion of the sliced FZ wafer 103 is chamfered (FIG. 2D). The wafer is placed on the lapping board 104 and both sides are lapped, and as described above, the thickness of each side is reduced by 40 μm (FIG. 2E). When one surface of the FZ wafer 103 is polished to 20 [mu] m by the mechanical chemical polishing apparatus 105 to be a mirror surface, the thickness of the FZ wafer 103 is reduced by 100 [mu] m by wrapping and mechanical chemical polishing from the above-mentioned 380 [mu] m after slicing, to 280 [mu] m. ((FIG. 3 (f)).

  As shown in FIG. 6, the conventional method includes an etching process for removing damage due to lapping after the lapping process until a mechanically polished 725 μm FZ wafer is obtained. In the method according to the invention, it may be deleted. The reason is that in the conventional method, after the lapping process, the side where the MOS structure is formed as a semiconductor region has a process of polishing and polishing to make a mirror surface, but the back surface is only etched after the lapping process. It is. Etching here may be mixed acid or alkaline. In a mixed acid etchant, a mixed solution of hydrofluoric acid, nitric acid and acetic acid is generally used. In addition, in an alkaline etchant, an aqueous potassium hydroxide solution is used. In either case, it is often used by heating to about 50 to 60 ° C. When a mixed acid etchant is used, even if there is a local lapping mark on the surface, the etching is generally uniform and it is difficult to leave a mark. When an alkaline etchant is used, the flatness is generally good, but local defects such as lap marks are likely to be selectively etched. Therefore, when using an alkaline etchant, grinding is often applied subsequently. What is necessary is just to select a mixed acid type and an alkaline type etchant according to required flatness suitably.

  When etching is not performed, the lapped surface is exposed, and in the element formation process, abrasive grains are likely to remain in the damaged layer formed on the processed surface, and may be detached during the process, causing contamination, or processing. There is a problem that the damaged layer itself falls off and becomes a pollution source.

  On the other hand, in the method according to the present invention, since the CZ wafer is attached to the back surface of the wafer having a thickness of 280 μm, it is necessary to make a mirror surface by mechanical chemical polishing, but the above-mentioned problem is caused even if damage formed by lapping remains. Does not occur. Since the MOS surface structure is formed after the wafer side is ground and the thickness of the wafer is adjusted by applying a mechanical and chemical polishing process after the CZ wafer is attached, even if it is wrapped before the CZ wafer attachment process Well, there is no need for grinding and mechanochemical polishing processes as in the prior art. In addition, since the thickness is reduced from 280 μm after being bonded to the CZ wafer, the thickness of the slice wafer from the silicon single crystal ingot can be reduced by that amount.

  Next, etching for removing damage by slicing, lapping, and lapping is performed, and then one surface is ground as necessary, and one surface is mirror-polished by mechanical chemical polishing to a thickness of 505 μm and 8 inches. A CZ wafer 106 having a diameter is prepared. This CZ wafer is cheaper and easier to obtain than FZ wafers. The well-known SC-1 and SC-2 cleaning processes are performed on the above-described FZ wafer having a thickness of 280 μm and CZ wafer having a thickness of 505 μm in order to obtain hydrophilic and clean surfaces (FIG. 3 ( g)).

  SC-1 and SC-2 treatments consist of SC-1 (Standard Clean-1) consisting of ammonia water and hydrogen peroxide for the purpose of particle removal, and hydrochloric acid and hydrogen peroxide for the purpose of removing metal impurities. This is a cleaning method in combination with SC-2 (Standard Clean-2). Here, as shown in FIGS. 7 and 8, an oxide film 107 having a film thickness of about 4 μm is formed on the CZ wafer, so that the FZ wafer and the CZ wafer can be bonded and bonded more easily and reliably. It is also preferable. In this case, since the present invention is not intended to produce an SOI substrate, after the MOS structure is formed on the surface side, the thick oxide film and the CZ wafer sandwiched between the interfaces of the CZ wafer and the FZ wafer are all removed. It is desirable to form the collector layer and the FS layer after dropping and reliably exposing the back surface of the FZ wafer.

After the cleaning, the FZ wafer and the CZ wafer are bonded together so that the mirror surfaces thereof face each other. Heat treatment and annealing treatment at 1100 ° C. for about 2 hours are added in an O 2 atmosphere to promote the siloxane bond at the bonding interface of the bonding, thereby integrating the two wafers of FZ and CZ (FIG. 3 (h)). The thickness of the bonded wafer is 785 μm. Among the bonded wafers, the circumferential portion of only the FZ wafer 103 is chamfered in a mesa shape (in a trapezoidal shape) so as not to reduce the diameter of the CZ wafer 106 serving as a support for the FZ wafer 103. The cut width of the chamfer is preferably about 0.5 mm to 5 mm (FIG. 3 (i)). Subsequently, the entire surface of the wafer is etched by about 10 μm with a potassium hydroxide aqueous solution, TMAH (tetramethylammonium hydroxide aqueous solution) or the like to remove the strain (FIG. 4 (j)).

  The exposed surface side of the FZ wafer 103 is ground by 30 μm, then polished by 20 μm by mechanical chemical polishing, and mirror-finished to obtain a bonded wafer of 725 μm (FIG. 4 (k)). Here, grinding may be performed as necessary, and may not be performed. When grinding is not performed, the thickness of the CZ wafer may be increased accordingly. The thickness of the bonded wafer is desirably 700 μm or more and about 725 μm in the case of an 8-inch diameter wafer. In the case of a wafer having a diameter of 5 inches or 6 inches, it is desirable that the wafer be 600 μm or more and about 625 μm.

  Next, the bonded wafer is put into a wafer process, and a well-known IGBT surface side MOS structure (not shown in FIG. 4) is formed on the mirror-finished FZ wafer 103 (FIG. 4L). ). The IGBT structure is omitted because it is difficult to clarify in FIG. 4, but FIG. 5 shows a cross-sectional view of the main part of the IGBT. In FIG. 5, the surface side MOS structure of the IGBT is shown by a p-type base layer 2, an n-type emitter region 3, a gate insulating film 4, a gate electrode 5, a trench 6, an interlayer insulating film 7, and an emitter electrode 10. Next, the CZ wafer 106 on the back side of the bonded wafer is appropriately ground, polished, and etched away to expose the back side of the FZ wafer 103 (FIG. 4 (m)). The grinding, polishing, and etching here are thinned to a wafer thickness necessary for the design withstand voltage of the semiconductor device. The final required thickness of the FZ wafer 103 is about 120 μm with a withstand voltage of 1200 V and about 60 μm with a thickness of 600 V.

  An FS layer (FS layer 8 in FIG. 5) having a depth of about 5 μm is obtained by using phosphorus as an n-type impurity and boron as a p-type impurity, ion implantation from the back surface of the FZ wafer 103, and thermal diffusion as necessary. A p-type collector layer (p-type collector layer 9 in FIG. 5) having a depth of about 0.5 μm is formed on the surface of the FS layer. Furthermore, when a well-known collector electrode (collector electrode 11 in FIG. 5) having a four-layer structure is formed on the surface of this p-type collector layer in the order of aluminum, titanium, nickel, and gold by an ordinary method such as sputtering, the FS-IGBT The wafer is completed (FIG. 4 (n)).

  In the above description, the FS-IGBT is used, but an NPT-IGBT having no FS layer on the back surface side may be used. In that case, the thickness of the FZ wafer needs to be a thickness including a drift layer thickness of at least the maximum width in which the depletion layer extends from the main junction at the time of design withstand voltage. Also, the p-type collector layer can be formed by ion implantation after the CZ wafer on the back side is scraped off as described above, but when the p-type CZ wafer is used and the CZ wafer is scraped off as described above. In addition, the p-type collector layer may be formed by leaving it as thin as about 0.5 μm without being scraped off. In this case, before forming the surface side MOS structure, it is necessary to cut the wafer thickness to a required design breakdown voltage.

  As described above, in the embodiment described above, in order to manufacture the FS-IGBT, in the wafer process manufactured using the 8-inch FZ wafer, the initial thickness of the FZ wafer to be put into the wafer process is cracked and chipped. Even if the thickness is 280 μm, which is thinner than 725 μm, which is usually required to prevent it, the frequency of wafer cracking can be suppressed to the same level as before by attaching an inexpensive CZ wafer to the FZ wafer.

  In addition, the number of wafers taken from the FZ crystal can be increased.

2 p-type base layer 3 n-type emitter region 4 gate insulating film 5 gate electrode 6 trench 7 interlayer insulating film 8 FS layer 9 p-type collector layer 10 emitter electrode 11 collector electrode 100 round bar block 101 notch 102 wire saw 103 FZ wafer 104 wrapping Panel 105 Mechanical chemical polishing device 106 CZ wafer 107 Oxide film

Claims (4)

An FZ wafer cutting step of cutting an FZ wafer having a thickness greater than that required for the design withstand voltage of the semiconductor device from a silicon crystal ingot formed by the floating zone method;
A CZ wafer cutting step for cutting a CZ wafer from a silicon crystal ingot formed by the Czochralski method, and wrapping for wrapping both one main surface and the other main surface of the cut FZ wafer and CZ wafer. Process,
After the lapping step, an etching step of performing etching for removing damage due to the lapping on both the one main surface and the other main surface of the CZ wafer;
After the lapping step, a first mirroring step in which the one main surface of the FZ wafer is made into a mirror surface by polishing without performing the etching step for removing damage due to the lapping;
After the etching step for removing damage due to the lapping, a second mirroring step for polishing the one main surface of the CZ wafer to be a mirror surface;
A bonding step in which the one main surface that is the mirror surface of the FZ wafer and the one main surface that is the mirror surface of the CZ wafer are bonded together to form a bonded wafer;
A third mirror surface step of mirror-grinding the other surface of the FZ wafer of the bonded wafer to a predetermined thickness;
A semiconductor region forming step of forming a required semiconductor region on the other surface of the FZ wafer mirror-finished in the third mirror surface step;
Grinding the CZ wafer from the other surface and exposing the one main surface of the FZ wafer to a predetermined thickness;
A method for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the required semiconductor region has a MOS surface structure. Wherein in the grinding step, the exposed method according to claim 2, wherein adding a step of forming a collector layer by ion implantation on the one main surface of the FZ wafer. Wherein in the grinding step, the exposed the FZ method according to claim 2, wherein said one surface of the wafer, characterized in that it comprises a step of forming a field stop layer and the collector layer by ion implantation.