JPH11251562A - Semiconductor substrate and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a substrate which is hard to break, even if it is made into a large aperture shape as a semiconductor substrate for forming an integrated circuit integrated with high breakdown voltage elements and moreover element-forming regions lightly doped can be obtd. at a low concn. of O. SOLUTION: A thermal oxide film 3 is formed on a 6-inch CZ Si substrate 2 600 μm thick formed through the CZ method, and an FZ Si substrate formed by a floating zone(FZ) method is clad to and integrated with it. The FZ Si substrate has an O concn. of about 0.8×10<17> cm<-3> and impurity concn. of about 0.5×10<14> cm<-3> and is ground and polished into a film of 50 μm or less, e.g., about 10 μm, thus obtaining a silicon-on-insulator(SOI) substrate 1. Using the SOI substrate 1, an increased breakdown voltage is realized, by the use of a lightly doped layer, when a high breakdown voltage element is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor substrate having a structure in which a semiconductor layer having a predetermined thickness is provided on a semiconductor support substrate.

[0002]

Conventionally, as a semiconductor substrate for forming a semiconductor integrated circuit, for example, C
It is common to use a single crystal silicon substrate formed by the Z (Czochralsky) method. This is CZ
The semiconductor substrate formed by the method is hard to crack in strength,
In addition, the fact that the diameter can be easily increased greatly contributes to mass production.

On the other hand, a semiconductor substrate formed by the CZ method has an oxygen concentration of 1 × 10 ¹⁸ c due to the principle of the manufacturing method.
m- ³ , which can be reduced only to about m ⁻³ , thereby generating an oxygen-induced OSF (Oxidation-induce).
d Stacking Fault (oxygen-induced stacking fault) is difficult to reduce, and there is a problem that the product yield is deteriorated. Further, regarding the impurity concentration, it is not possible at present to form an impurity concentration of phosphorus (n-type) or boron (p-type) at 1 × 10 ¹⁴ cm ⁻³ or less in a semiconductor substrate formed by the CZ method. However, there is a limit in increasing the resistance of the substrate, and as a result, it is not suitable for forming a high breakdown voltage element.

In recent years, as a semiconductor integrated circuit device, a power IC has been developed in which a high-voltage element or the like is integrally provided in addition to circuit components such as a logic circuit so that a load can be directly driven. However, such a power type high withstand voltage element has a CZ as described above.
It is difficult to form an element using a semiconductor substrate formed by a method, and a semiconductor substrate formed by an FZ (Floating Zone) method may be used as a semiconductor substrate suitable for a high voltage element of a power system.

However, since a semiconductor substrate formed by the FZ method is generally fragile and it is difficult to increase the diameter, a semiconductor substrate having a thickness of about 600 μm used in a normal semiconductor manufacturing process is assumed. In such a case, it is expected that the number of cracks accompanying the increase in the diameter is increased, and it is difficult to enhance the productivity of the power IC.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has an object to manufacture a power IC chip in which a high voltage element and the like are integrally provided together with a logic circuit element. It is an object of the present invention to provide a semiconductor substrate that is difficult to break and to provide a method of manufacturing the semiconductor substrate.

[0007]

According to the first aspect of the present invention, a semiconductor substrate (26) is formed on a semiconductor support substrate (2) formed by the CZ method and used for forming an element formed by the FZ method. Since the semiconductor layer (4) is formed to have a predetermined thickness, the semiconductor layer (4) in a portion where an element is to be formed is formed by FZ.
By using a substrate formed by the CZ method, the substrate can be made suitable for forming a high withstand voltage element, and the supporting substrate can be in a state in which the mechanical strength is increased by using a semiconductor supporting substrate (2) formed by the CZ method. The electrical characteristics are excellent and the diameter can be increased.

According to the invention of claim 2, the semiconductor substrate (2
6) A semiconductor layer (4) for forming an element having an oxygen concentration of about 1 × 10 ¹⁷ cm ⁻³ or less is provided with a predetermined thickness on a semiconductor supporting substrate (2) formed by the CZ method. In this case, the semiconductor layer (4) where the element is to be formed can have a low oxygen concentration to provide a high yield IC with few crystal defects, and the semiconductor support substrate (2) in which the support substrate is formed by the CZ method. Can be used to increase the mechanical strength, thereby improving the electrical characteristics and increasing the diameter.

According to the third aspect of the present invention, the semiconductor layer (4)
In the case where the high withstand voltage elements (8, 9) are formed, the semiconductor layer (4) having a low impurity concentration is used because the impurity concentration is set to about 1 × 10 ¹⁴ cm ⁻³ or less. Elements (8, 9) with a high withstand voltage can be provided, so that the electrical characteristics are excellent and the diameter can be increased.

According to the invention of claim 4, as the semiconductor substrate (1), the semiconductor support substrate (2) and the semiconductor layer (4)
Since the insulating film (3) is provided between the semiconductor substrate (2) and the circuit element formed on the semiconductor layer (4), the semiconductor device can be insulated from the semiconductor support substrate (2), and thus the electrical characteristics are excellent. The semiconductor integrated circuit having the above configuration can be formed.

According to the fifth aspect of the present invention, in the bonding step (S2), the semiconductor layer substrate (5) for forming the semiconductor layer (4) is bonded to the semiconductor support substrate (2). In the polishing step (S3), the semiconductor substrate (26) can be obtained by polishing the bonded semiconductor layer substrates (2, 5) to a predetermined thickness.

According to the invention of claim 6, in the insulating film forming step (S1), the semiconductor supporting substrate (2) and the semiconductor layer substrate (5) for forming the semiconductor layer (4) are bonded together. A semiconductor substrate (1) can be obtained by forming an insulating film (3) on at least one of the surfaces to be bonded and then performing a bonding step (S2) and a polishing step (S3).

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows an SOI which is a semiconductor substrate according to the present invention.
(Silicon On Insulator) This schematically shows a cross section of a substrate 1, and a single layer as a semiconductor layer for element formation is formed on a CZ silicon substrate 2 as a semiconductor support substrate via a thermal oxide film 3 as an insulating film. The crystalline silicon thin film 4 is formed by lamination.

The SOI substrate 1 has a thickness of, for example, about 500 μm or more, and preferably about 600 μm, and has a diameter of 6 inches. As the CZ silicon substrate 2, a silicon single crystal substrate formed by a CZ method is used.
The impurity concentration is about 0 ¹⁸ cm ⁻³ , and the value of the specific resistance corresponding to the impurity concentration is about 1 to 10 Ωcm.

The single-crystal silicon thin film 4 as a laminated semiconductor layer is formed by polishing the bonded FZ silicon substrate 5 as described later. The single crystal silicon thin film 4 has an oxygen concentration of 1.0
× 10 ¹⁷ cm ⁻³ or less, for example, 0.8 × 10 ¹⁷ cm
^-3 , and the impurity concentration is 1.0 × 1
0 ¹⁴ cm ⁻³ or less, for example, 0.5 × 10 ¹⁴ cm ⁻³
About 50 μm or less, for example, 10 μm.
m.

With such a structure, even when an integrated circuit element is formed in the single-crystal silicon thin film 4 or a high-voltage element is integrally formed, the formed high-voltage element has electrical characteristics. The generation of leakage current and the like due to crystal defects can be reduced as much as possible, a high breakdown voltage transistor can be obtained, and a CZ silicon substrate 2 serving as a base is formed as a semiconductor substrate 1 by a CZ method. Therefore, it is possible to sufficiently withstand the manufacturing process without reducing the mechanical strength.

Next, a method of manufacturing such an SOI substrate 1 will be briefly described. First, in the oxide film forming step S1, the thermal oxide film 4 is formed on one or both of the CZ silicon substrate 2 as the semiconductor support substrate and the FZ silicon substrate 5 to be bonded. The insulating film is not limited to the thermal oxide film 4, but may be a silicon oxide film formed by a CVD method or the like.

Next, in a bonding step S2, both the CZ silicon substrate 2 and the FZ silicon substrate 5
As a pre-treatment, after performing a predetermined treatment so as to increase the adhesion due to hydrogen bonding when performing the hydrophilization treatment and bonding, the two are bonded and adhered under predetermined conditions. Thereafter, a heat treatment is performed to further enhance the adhesion between the substrates 2 and 5.

Subsequently, in the polishing step S3, the exposed side of the bonded FZ silicon substrate 5 is ground and polished, so that the above-mentioned single-crystal silicon thin film 4 has a film thickness to be left. Here, for example, the single-crystal silicon thin film 4 is removed to a film thickness of about 5 μm with a margin. After this, CM as a finish
The surface is finished using a P (Chemical Mechanical Polish) method or the like, and the polishing step S3 ends.

As described above, the SOI substrate 1 can be manufactured. SOI substrate 1 manufactured in this manner
Can be used not only for semiconductor integrated circuits and discrete elements, but also excellent characteristics can be obtained for power ICs or the like in which a power element such as an integrated circuit and a high breakdown voltage element are integrated. For example, electroluminescence (E) used for flat panel displays and the like
L) It can also be used for a driving IC having a high voltage and a plurality of output stages, such as a display and a plasma display.

Next, the case where a driving IC 6 as a power IC is formed using the SOI substrate 1 will be briefly described with reference to FIGS. This driving IC 6
As shown, for example, a CMO as a logic circuit element
The S circuit element 7 is formed and L as a power element
DMOS (Lateral Double-diffused MOS) transistors 8 and 9 are formed.

In FIG. 2, the single-crystal silicon thin film 4 of the SOI substrate 1 has a trench formed so as to reach the oxide film 3 from the surface so as to divide each formation region of the CMOS circuit element 7 and the LDMOS transistors 8 and 9. An insulating film 10 is formed inside to be insulated and separated. Also, the insulating film 1
0, the peripheral area of the region where the CMOS circuit element 7 and the LDMOS transistors 8 and 9 are formed is LOCO.
It is insulated and separated by the S oxide film 11. Also, this L
The OCOS oxide film 11 is composed of LDMOS transistors 8 and 9
Are also formed on the surface between each drain and source.

As described above, the single-crystal silicon thin film 4 has a phosphorus concentration of 0.5 × 10 ¹⁴ cm as an n-type impurity.
^Since it is about ⁻³ , it can function as an i-layer which is almost an intrinsic semiconductor.
, Functions as an electric field relaxation layer as described later. Each of the formation regions of the LDMOS transistors 8 and 9 is provided with an n-type drift layer 12a and a p-type drift layer 12b in which impurities are introduced at a low concentration to a predetermined depth.

The LDMOS transistors 8 and 9 are formed in an n-channel type and a p-channel type, respectively. Hereinafter, the LDMOS transistor 8 will be described as a representative, but the LDMOS transistor 9 has a subscript “a”. Instead, it is shown as b, and the description is omitted.

The LDMOS transistor 8 is provided as a high-breakdown-voltage power element that allows an output current to flow in the lateral direction. The source region is arranged in a ring around the drain contact region 13a in consideration of the breakdown voltage structure. . Therefore, in the illustrated state, the channel region and the source region are shown to be formed on the left and right sides with the drain contact region 13a as the center, but when viewed in plan, they are connected in a ring in the plane. Is formed.

As a channel region, a p-type well region 14a is formed so as to reach a region functioning as an i-layer of the single crystal silicon thin film 4, and a low impurity is formed so as to partially overlap the p-type well region 14a. A p-type channel region 15a having a concentration is formed. An n-type source region 16a with a high impurity concentration and a p-type channel contact region 17a with a high impurity concentration are formed in the p-type channel region 15a.

On the surface of the channel region 15a between the source region 16a and the drain drift region 12a, a gate electrode 18a made of polysilicon is formed in a predetermined pattern via a gate oxide film (not shown). The entire surface is covered with a protective film (not shown), and a source, drain, and gate electrode film 19 formed by patterning an aluminum film by opening a part thereof is formed. The electrode film 19 forms a drive circuit by connecting to the wiring pattern of the CMOS circuit element 7 or another circuit element (not shown).

In the CMOS circuit element 7, impurities are introduced at a high concentration into the p-type well 20 and the n-type well 21 formed to a predetermined depth by introducing impurities at a low concentration into the single crystal silicon thin film 4. Source and drain regions 2
2 and 23 are formed, and the p-type well 20 and the n-type well 21 each function as a channel region. A gate oxide film (not shown) is formed corresponding to this channel region, and a gate electrode 24 made of polysilicon is patterned on the surface thereof. An electrode film 25 formed by patterning an aluminum film is formed in each of the source and drain regions, and is electrically connected to other circuit elements.

Since the SOI substrate 1 on which the single-crystal silicon thin film 4 having a low impurity concentration is used as described above, especially in the LDMOS transistors 8 and 9,
The following effects can be obtained. That is, since the single crystal silicon thin film 4 can be used as an i-layer, it can be used as a layer having a lower impurity concentration than the drift layers 12a and 12b.

As a result, the electric field generated inside by the voltage applied between the source and the drain can be reduced, and the withstand voltage can be increased. At this time, the breakdown voltage can be ensured by the i-layer of the single-crystal silicon thin film 4, so that the impurity concentration of the drift layers 12a and 12b can be increased to some extent. The resistance can be kept low, so that the current driving capability can be increased.

FIG. 3 shows that the inventor uses a p-channel type LDMO.
The equipotential lines when a voltage is applied between the source and the drain of the S transistor 9 are obtained by simulation. In the configuration of FIG. 2, the region P surrounded by a two-dot chain line is taken as an example. (In this case, the calculation is performed when the thickness of the single-crystal silicon thin film 4 is set to 5 μm).

From this result, it can be recognized that the function of alleviating the electric field can be provided. In addition,
FIG. 4 shows a case where the single-crystal silicon thin film 4 as the i-layer is not provided, that is, a case where the portion of the i-layer is also provided as the drift layer 12b in order to compare and show the effect of the electric field relaxation of the present embodiment. Shows the distribution of equipotential lines,
Since the equipotential lines at the portions indicated by the circles in the figure become dense, it is understood that the electric field is concentrated.

According to this embodiment, as the SOI substrate 1, the FZ silicon substrate 5 is bonded and polished with the CZ silicon substrate 2 as the semiconductor support substrate with the thermal oxide film 3 interposed therebetween, and is polished. Since the silicon thin film 4 is provided, the single crystal silicon thin film 4 as a semiconductor layer for forming an element can be formed at a low oxygen concentration while increasing the diameter while reducing the occurrence of cracks while increasing the mechanical strength. In addition, a low impurity concentration can be obtained.

In addition, a driving IC 6 integrally provided with high withstand voltage elements such as LDMOS transistors 8 and 9
Is formed, it is possible to provide the SOI substrate 1 capable of improving the driving capability while improving the breakdown voltage characteristics of the LDMOS transistors 8 and 9.

(Second Embodiment) FIG. 5 shows a second embodiment of the present invention.
This embodiment is different from the first embodiment in that the semiconductor substrate 26 has a configuration in which the insulating film 3 is not interposed. That is, in this case, the FZ silicon substrate 5 is directly bonded and integrated on the CZ silicon substrate 2, and thereafter, the surface of the FZ silicon substrate 5 is ground and polished to have a predetermined thickness.

Thus, a single-crystal silicon thin film 4 having a low oxygen concentration and a low impurity concentration is formed as a semiconductor layer for element formation while improving mechanical strength using the CZ silicon substrate 2 as a semiconductor support substrate. Therefore, even when a high breakdown voltage element or the like is integrally formed, a device having excellent withstand voltage characteristics can be formed.

Further, since the layer of the single-crystal silicon thin film 4 is formed by bonding, even when the thickness of the single-crystal silicon thin film 4 is set to be thicker than when an epitaxial layer or the like is formed, time constraints are imposed. The structure can be formed without receiving any adverse effects such as the characteristics of the underlying support substrate or crystal defects, and thus has the advantage that the degree of freedom in design can be increased.

The present invention is not limited to the above embodiment, but can be modified or expanded as follows. The substrate for the semiconductor layer is not limited to the bulk FZ silicon substrate 5, and a semiconductor substrate having desired characteristics can be obtained by laminating an epitaxial layer on the FZ silicon substrate 5. It is possible to integrally provide a layer including a plurality of layers having different target characteristics.

Although the FZ silicon substrate 5 is polished so as to have a predetermined film thickness in the polishing step, the method is not limited to the polishing, but may be a method of removing by etching, or a method of implanting hydrogen ions or the like by ion implantation. It is also possible to use a method of introducing a hydrogen ion layer at a high concentration in the depth dimension, performing heat treatment, and separating the hydrogen ion layer as a separation surface.

The present invention can be applied not only to LDMOS transistors but also to power devices such as ordinary DMOS transistors, VMOS transistors, bipolar power transistors, and IGBTs.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view when applied to a power IC element.

FIG. 3 is an operation explanatory diagram showing a comparison of potential distributions (part 1);

FIG. 4 is an operation explanatory view showing a comparison of potential distributions (part 2);

FIG. 5 is a view corresponding to FIG. 1, showing a second embodiment of the present invention;

[Explanation of symbols]

1 is an SOI substrate (semiconductor substrate), 2 is a CZ silicon substrate (semiconductor support substrate), 3 is a thermal oxide film (insulating film), 4 is a single crystal silicon thin film (semiconductor layer), 5 is an FZ silicon substrate, and 6 is driving IC, 7 is a CMOS circuit element, 8 is an n-channel LDMOS transistor (high breakdown voltage element), 9
Is a p-channel LDMOS transistor (high breakdown voltage element), 10 is an insulating film, 11 is a LOCOS oxide film, 12
a and 12b are drift layers; 13a and 13b are drain contact regions; 15a and 15b are channel regions;
a and 16b are source regions, 17a and 17b are channel contact regions, 18a and 18b are gate electrodes, 19 is an electrode film, 20 is a p-well region, 21 is an n-well region, 2
2, 23 are source and drain regions, 24 is a gate electrode,
25 is an electrode film, 26 is a semiconductor substrate.

Claims (6)

[Claims] 1. A semiconductor layer (4) for element formation formed by an FZ (Floating Zone) method with a predetermined thickness is provided on a semiconductor support substrate (2) formed by a CZ (Czochralsky) method. Characteristic semiconductor substrate. 2. An oxygen concentration of 1 × 10 ¹⁷ c on a semiconductor supporting substrate (2) formed by a CZ (Czochralsky) method.
A semiconductor substrate, wherein a semiconductor layer (4) for forming an element formed to a thickness of about m- ³ or less is provided with a predetermined thickness. 3. The semiconductor substrate according to claim 2, wherein said semiconductor layer has an impurity concentration of 1 × 10 ¹⁴ cm.
A semiconductor substrate characterized by being formed to about ^-3 or less. 4. The semiconductor substrate according to claim 1, further comprising an insulating film (3) provided between said semiconductor support substrate (2) and said semiconductor layer (4). A semiconductor substrate characterized by the above-mentioned. 5. The method for manufacturing a semiconductor substrate (26) according to claim 1, wherein the semiconductor layer (4) is formed on the semiconductor support substrate (2). (5) a bonding step (S2); and a polishing step (S3) of polishing the bonded semiconductor layer substrates (2, 5) to a predetermined thickness. Production method. 6. The method for manufacturing a semiconductor substrate (1) according to claim 4, wherein the semiconductor support substrate (2) and a semiconductor layer substrate (5) for forming the semiconductor layer (4) are attached. An insulating film forming step (S1) of forming an insulating film (4) on at least one of the surfaces to be bonded when bonding, and the semiconductor layer substrate (5) on the semiconductor support substrate (2).
A bonding step (S2) and a polishing step (S3) of polishing the bonded semiconductor layer substrates (2, 5) to a predetermined film thickness (S3).