JP2006344666A - Semiconductor device, its manufacturing method, and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-performance semiconductor device, its manufacturing method, and a display device. <P>SOLUTION: The semiconductor device 1 has an insulating substrate 4, and a longitudinal bipolar structure single-crystal silicon thin film transistor 5 provided on the same. The single-crystal silicon thin film transistor 5 includes an element 10, constituted by a laminate structure comprising an uppermost layer collector 15, an intermediate layer base 16, and a lowermost layer emitter 17; a collector electrode 11 provided on the upper-layer side from the collector 15 of the element 10, and electrically connected with the collector 15; and an emitter electrode 13 provided on a lower layer side from the emitter 17, and electrically connected with the emitter 17. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a single-crystal silicon thin film transistor having a vertical bipolar structure, a manufacturing method thereof, and a display device.

  2. Description of the Related Art In recent years, semiconductor devices such as active matrix liquid crystal display devices and OLED (Organic Light Emitting Diode) display devices that have been improved are required to have higher information processing speed and higher performance high-frequency characteristics. Therefore, various structures of semiconductor devices have been studied for the purpose of improving the high speed characteristics and high frequency characteristics of the semiconductor devices.

  A semiconductor device having a bipolar transistor is known as such a semiconductor device. Here, the term “bipolar” is a generic term for devices called bipolar (bipolar) transistors. A bipolar transistor is a current operation type device in which p-type and n-type semiconductor elements are arranged in a line with npn or pnp. In addition, bipolar transistors are classified into a horizontal type and a vertical type. The latter has advantages such as higher performance such as high-frequency characteristics and higher speed operation.

  Here, as a semiconductor device in which a transistor having a vertical bipolar structure is formed, for example, Patent Document 1 discloses a trench isolation (STI) region formed between an element isolation region and a collector extraction region and a base layer. A semiconductor device in which a vertical bipolar transistor having a collector well formed by ion implantation, a p-well implantation layer, and a base layer is formed on a type silicon substrate, except for the portion immediately below the base layer in the collector well The lower and collector lead-out regions are provided with high-concentration implantation layers having a higher impurity concentration than the collector well. According to this, it is described that the collector resistance of a bipolar transistor manufactured in a CMOS fully compatible BiCMOS process using a p-type silicon substrate can be reduced.

Further, Patent Document 2 discloses a shallow trench isolation (STI) region formed in a substrate having an upper surface and having an inner end portion and an upper surface made of a dielectric material, and a pair of STI regions in the substrate. And a counter-doped intrinsic base region formed between the pair of STI regions on the upper surface of the substrate, the intrinsic base region and the pair of STI regions. And the intrinsic base region has an edge, and is formed in the margin between the STI region and the intrinsic base region on the intrinsic base region, the doped emitter region formed away from the edge. A shallow isolation extension region made of a dielectric material juxtaposed with the edge of the intrinsic base region, and covers the shallow isolation extension region, partially extending over the intrinsic base region and physically And a semiconductor device is disclosed that the transistors of the vertical bipolar structure and an external base region in electrical contact has been formed. According to this, it is described that the parasitic capacitance of a transistor having a vertical bipolar structure can be reduced.
JP2004-079719 JP2004-304190

  In the conventional semiconductor device as shown in Patent Documents 1 and 2, as shown in FIG. 13, the lowermost layer of the element portion (the layer constituting the base 101, the emitter 102, and the collector 110) of the transistor 100 having a vertical bipolar structure. A collector electrode 104 is formed which is electrically connected to the collector 110 located at a position via the collector formation layer 103. Since the collector electrode 104 is usually formed on the surface of the semiconductor substrate 105, the region of the collector 110 is extended in order to form the collector 110 from the lowermost layer of the element portion to the surface of the semiconductor substrate 105. Reach-through 106 is formed.

  However, if the area of the collector 110 is wide, the distance between the base 101 and the emitter 102 and the collector electrode 104 becomes long, so that the carrier travel time from the emitter 102 to the collector 110 becomes long, and the high-speed characteristics and high-frequency characteristics of the transistor. There is a problem that the performance is adversely affected.

  In addition, since a large number of manufacturing processes are required to form the reach-through 106, there is a problem that the manufacturing yield may be lowered accordingly.

  Furthermore, since a space for forming the reach through 106 is also required, there is a problem that the size of the semiconductor device is increased.

  The present invention has been made in view of these points, and an object of the present invention is to provide a high-performance semiconductor device, a manufacturing method thereof, and a display device.

  A semiconductor device according to the present invention includes an insulating substrate and a vertical bipolar single crystal silicon thin film transistor provided thereon, the single crystal silicon thin film transistor including an uppermost collector, an intermediate layer base, and an intermediate layer thin film transistor. An element part having a laminated structure composed of the lowermost emitter, a collector electrode provided on the upper layer side of the collector of the element part and electrically connected to the collector, and provided on a lower layer side of the emitter of the element part And an emitter electrode electrically connected to the emitter.

  For this reason, the distance between the emitter and the collector electrode is shortened, and the traveling time of carriers from the emitter to the collector is shortened. Therefore, the performance of the transistor such as high speed and high frequency characteristics is improved. Further, since it is not necessary to extend the collector region to form the reach through, the semiconductor device manufacturing process is simplified as compared with the conventional one, and further, the space of the semiconductor device can be saved.

  The semiconductor device according to the present invention may further include a single crystal silicon thin film transistor having a MOS structure on the insulating substrate.

  According to this, a single crystal silicon thin film transistor having a BiCMOS structure including a single crystal silicon thin film transistor having a bipolar structure and a single crystal silicon thin film transistor having a MOS structure can be formed on the same insulating substrate. At this time, since the MOS single crystal silicon thin film transistor is provided on the insulating substrate, an SOI (Silicon On Insulator) structure is formed. Here, the SOI structure is formed on an SOI substrate in which a device is provided with a silicon layer on an insulator layer, and the capacitance of the substrate can be ignored compared to the case of using a silicon wafer itself. Performance improvement is possible. Accordingly, when such a single crystal silicon thin film transistor having a MOS structure is provided on the same insulating substrate as the single crystal silicon thin film transistor having the above vertical bipolar structure, the single crystal silicon having a higher speed and higher performance than the conventional one is provided. A thin film transistor is obtained.

  The semiconductor device according to the present invention may further include a non-single-crystal silicon thin-film transistor on an insulating substrate on which the single-crystal silicon thin-film transistor having the vertical bipolar structure and the single-crystal silicon thin-film transistor having the MOS structure are formed.

  Therefore, in a semiconductor integrated circuit or the like, a single crystal silicon thin film transistor having the above-described MOS structure is used in a portion requiring high performance transistor characteristics, and a non-single crystal silicon thin film transistor is provided in a portion where the performance of the transistor does not have to be as high as a single crystal. Can be used as a high-performance semiconductor device.

  A display device according to the present invention includes an active matrix substrate including an insulating substrate and a single crystal silicon thin film transistor having a vertical bipolar structure provided thereon, and the single crystal silicon thin film transistor includes an uppermost layer. An element part having a stacked structure composed of a collector, a base of the intermediate layer and an emitter of the lowermost layer, a collector electrode provided above the collector of the element part and electrically connected to the collector, and an emitter of the element part An emitter electrode provided on a lower layer side and electrically connected to the emitter.

  When the above active matrix substrate is used in a device such as a timing controller of a display device, high speed characteristics and high frequency characteristics which are particularly necessary can be given to the part.

  A manufacturing method of a semiconductor device according to the present invention includes a vertical bipolar transistor element part in which a stacked structure is formed on a single crystal silicon substrate by a top layer collector, an intermediate layer base and a bottom layer emitter, a gate, An element part forming step for forming a MOS transistor element part composed of a source and a drain; A first planarization film forming step of forming a first planarization film so as to cover the single crystal silicon substrate on which the vertical bipolar structure transistor element portion and the MOS structure transistor element portion are formed; A release layer forming step of forming a release layer by implanting a release material as ions through the first planarizing film is provided. Further, a base electrode and an emitter electrode electrically connected to a base and an emitter of the vertical bipolar structure transistor element portion, respectively, and a gate of the MOS structure transistor element portion on the single crystal silicon substrate on which a release layer is formed. A first electrode forming step of forming a gate electrode, a source electrode and a drain electrode electrically connected to each of the source and drain, a base electrode and an emitter electrode, and a gate electrode, a source electrode and a drain electrode were formed; A second planarizing film forming step of forming a second planarizing film so as to cover the single crystal silicon substrate; A substrate bonding step for bonding the single crystal silicon substrate to the insulating substrate such that the surface of the second planarization film is a contact surface; and the single crystal silicon substrate provided on the insulating substrate is bonded to the release layer. A substrate removing step for removing a portion on the opposite side of the element portion forming side portion along the substrate, a thinning step for thinning from the element portion forming side portion of the single crystal silicon substrate, and the vertical exposure exposed by the thinning. And a second electrode forming step for forming a wiring for electrically connecting each transistor. The collector electrode is electrically connected to the collector of the bipolar transistor element portion.

  According to this, a single crystal silicon thin film transistor having a BiCMOS structure including a single crystal silicon thin film transistor having a vertical bipolar structure and a single crystal silicon thin film transistor having a MOS structure can be formed on the same insulating substrate. A crystalline silicon thin film transistor forms an SOI structure. Further, the single-crystal silicon thin film transistor having a vertical bipolar structure has a short distance between the emitter and the collector electrode, and a carrier traveling time from the emitter to the collector is shortened. Therefore, a single-crystal silicon thin film transistor having a BiCMOS structure with higher speed and higher performance than the conventional one can be obtained.

  In the method for manufacturing a semiconductor device according to the present invention, the stripping material may be a mixture of hydrogen and an inert material.

  Hydrogen is an effective stripping material, but may reduce the activity of the Si device acceptor. Therefore, if an inert substance is mixed, the proportion of hydrogen is further reduced, thereby obtaining an effect of reducing the decrease in acceptor activity caused by hydrogen.

  In the method for manufacturing a semiconductor device according to the present invention, the film thickness of the first planarization film in the formation portion of the vertical bipolar structure transistor element portion is formed after the first planarization film is formed and before the release layer is formed. The step portion may be formed in the first planarization film so that the thickness of the first planarization film is thinner than the thickness of the first planarization film in the formation portion of the MOS structure transistor element portion.

  When the stripping material is ionized and implanted into the single crystal silicon substrate through the first planarization film having the stepped portion as described above, the stripping has a shape corresponding to the surface shape formed by the thickness of the first planarization film. A layer is formed in the single crystal silicon substrate. That is, the release layer is formed deep below the vertical bipolar transistor element part and shallowly below the MOS transistor element part. Then, after the part of the single crystal silicon substrate is peeled off by this peeling layer, the single crystal silicon layer remaining on each transistor is removed by etching or the like at the same time. The film thickness can be reduced without changing the difference. Accordingly, it is possible to easily reduce the thickness of the single crystal silicon layer formed in the single crystal silicon thin film transistor having the thin MOS structure as compared with the single crystal silicon thin film transistor having the vertical bipolar structure.

  As described above, according to the present invention, a high-performance semiconductor device, a manufacturing method thereof, and a display device can be provided.

  Hereinafter, a semiconductor device 1 according to an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiment.

(Configuration of semiconductor device)
As shown in FIG. 11, the semiconductor device 1 according to the present embodiment includes a BiCMOS structure single crystal silicon thin film transistor 2 and a non-single crystal silicon thin film transistor 3 integrated in different regions on an insulating substrate 4. .

  A single crystal silicon thin film transistor 2 having a BiCMOS structure includes a single crystal silicon thin film transistor 5 having a vertical bipolar structure, a single crystal silicon thin film transistor 6 having a CMOS structure including single crystal silicon thin film transistors 7 and 8 having an n-type MOS structure and a p-type MOS structure. Are formed on the same insulating substrate 4.

  The single-crystal silicon thin film transistor 5 having a vertical bipolar structure is formed on the insulating substrate 4 via a first planarization film 30 and a second planarization film 31 described below. A single crystal silicon thin film transistor 5 having a vertical bipolar structure includes a vertical bipolar structure transistor element section 10, a collector electrode 11, a base electrode 12, and an emitter electrode 13.

  The vertical bipolar transistor element unit 10 includes a collector (active collector) 15, a base 16, and an emitter 17 that form a vertical stacked structure of three layers. The collector 15 is formed in the uppermost layer of the vertical bipolar transistor element section 10, the base 16 is formed in the intermediate layer, and the emitter 17 is formed in the lowermost layer. The collector 15 and the emitter 17 are made of n-type single crystal silicon, and the base 16 is made of p-type single crystal silicon. That is, the single crystal silicon thin film transistor 5 having the vertical bipolar structure constitutes an npn transistor. The collector (active collector) 15 is created with a concentration profile different from that of the external collector region. Further, the base 16 has external base regions 18 formed on both sides. The external base 18 is formed by diffusion from the high concentration p-type polysilicon region 20. The high-concentration p-type polysilicon region 20 has SiO2 films 21 formed on both sides and the lower surface thereof. The SiO 2 film 21 on the lower surface of the high-concentration p-type polysilicon region 20 has an opening 22 formed at the center thereof. Base electrode 12 is formed so as to fit into opening 22 and in contact with the lower surface of high-concentration p-type polysilicon region 20.

  The emitter 17 is formed by diffusion from the high concentration n-type polysilicon region 25. In the high-concentration n-type polysilicon region 25, the emitter electrode 13 is formed so as to be in contact with the lower surface and to be fitted into the groove.

  The collector electrode 11 is formed in contact with the upper surface of the collector 15.

  The collector electrodes 11 are each formed of Al or an Al alloy. The collector electrode may not be formed of metal.

  The base electrode 12 and the emitter electrode 13 are each formed of Ti or TiN. This is because after bonding the insulating substrate and the silicon substrate, it is necessary to select a metal that can withstand the temperature of the heat treatment performed to remove the substrate and improve the bonding strength. Each of these electrodes is provided with electrical wiring (not shown), thereby constituting a logic circuit of a transistor.

  The first planarization film 30 is formed below the single crystal silicon thin film transistor 5 having a vertical bipolar structure and the single crystal silicon thin film transistor 6 having a CMOS structure. The first planarizing film 30 has a stepped portion 32 formed on the lower surface thereof. The step portions 32 are formed so as to extend downward from both lower ends of the single crystal silicon thin film transistor 5 having a vertical bipolar structure.

  The second planarizing film 31 is formed over the entire lower side of the first planarizing film 30. The second planarizing film 31 is formed thick below the single-crystal silicon thin film transistor 5 having the vertical bipolar structure and thin below the single-crystal silicon thin film transistor 6 having the CMOS structure. The first planarizing film 30 and the second planarizing film 31 are made of an insulating material made of an inorganic insulating film such as SiO2 or an insulating material mainly composed of an inorganic component having an organic group (such as polysiloxane containing an organic group). It is formed of a film.

  The single crystal silicon thin film transistor 6 having a CMOS structure is composed of a single crystal silicon thin film transistor 7 having an n type MOS structure and a single crystal silicon thin film transistor 8 having a p type MOS structure.

  The single crystal silicon thin film transistor 7 having an n-type MOS structure includes a MOS structure transistor element portion 9 (n-type source 40, n-type drain 41 and gate 42), a source electrode 45, a drain electrode 46 and a gate electrode 47. Yes.

  The single crystal silicon thin film transistor 8 having a p-type MOS structure includes a MOS structure transistor element portion 9 ′ (p-type source 50, p-type drain 51 and gate 52), a source electrode 55, a drain electrode 56 and a gate electrode 57. ing.

  The sources 40 and 50 and the drains 41 and 51 are spaced apart from the upper surface of the gate oxide film (SiO 2 film) 70 formed over the entire upper surface of the first planarization film 30 by the same width as the gates 42 and 52, respectively. Are arranged side by side. An element isolation wall 71 formed of an oxide film (SiO 2 film) is provided on the outer side of each of the p-type source 50 and drain 51 and on the upper surface of the gate oxide film 70. In the gate oxide film 70, an opening 72 is formed in a portion located below the sources 40 and 50 and the drains 41 and 51. The source electrodes 45 and 55 and the drain electrodes 46 and 56 are fitted into the opening 72 of the gate oxide film 70 so as to be in contact with the lower surfaces of the sources 40 and 50 and the drains 41 and 51, respectively.

  The gates 42 and 52 are formed in contact with the lower surface of the gate oxide film 70 and at intermediate positions between the source electrodes 45 and 55 and the drain electrodes 46 and 56. The gates 42 and 52 are made of high-concentration polysilicon. The gate electrodes 47 and 57 are formed in contact with the lower surfaces of the gates 42 and 52.

  These electrodes 45 to 47 and 55 to 57 are made of Ti or TiN. This is because after bonding the insulating substrate and the silicon substrate, it is necessary to select a metal that can withstand the temperature of the heat treatment performed to remove the substrate and improve the bonding strength. Each of these electrodes is provided with an electrical wiring (not shown), thereby connecting a logic circuit composed of transistors.

  The non-single crystal silicon thin film transistor 3 is arranged on the insulating substrate 4 in parallel with the single crystal silicon thin film transistor 2 having a BiCMOS structure. The non-single crystal silicon thin film transistor 3 is a transistor having a CMOS structure, and includes a non-single crystal silicon thin film transistor having an n-type MOS structure including a source 120, a drain 121 and a gate 122, and a source electrode 125, a gate electrode 127, and a drain electrode 126. , A source 130, a drain 131 and a gate 132, and a p-type MOS structure non-single-crystal silicon thin film transistor comprising a source electrode 135, a gate electrode 137 and a drain electrode 136. The non-single-crystal silicon thin film transistor 3 includes gates 122 and 132 on the upper layer and gate electrodes 127 and 137 formed on the upper surface of the gate oxide film (SiO 2 film) 140, respectively, and sources 12 and 130 and a drain 121 on the lower layer. , 131 are formed with the silicon non-single crystal layer 81 interposed therebetween. Further, source electrodes 125 and 135 and drain electrodes 126 and 136 are formed above the sources 120 and 130 and the drains 121 and 131, respectively, with the gate oxide film 140 interposed therebetween. Further, an interlayer oxide film (SiO 2 film) 141 is formed between the electrodes 125 to 127 and 135 to 137.

  Insulating substrate 4 is barium-aluminoborosilicate glass, alkaline earth-aluminoborosilicate glass, borosilicate glass, alkaline earth-zinc-lead-aluminoborosilicate glass, alkaline earth-zinc, which are high strain point glasses. -It is made of aluminoborosilicate glass or the like.

  The semiconductor device 1 having the above configuration is integrated as a drive element on the active matrix substrate 95 of the display device 94 as shown in FIG. An integrated circuit of the non-single-crystal silicon thin film transistor 3 is provided on the screen 96 and the gate driver 97 of the display device 94 which does not require high performance of the transistor to a single crystal level. The source driver 98 is provided with an integrated circuit of the non-single crystal silicon thin film transistor 3 or the BiCMOS structure single crystal silicon thin film transistor 2, and these are selected in consideration of cost and performance. Further, the high added value peripheral circuit 99 in which high speed and high frequency characteristics are important is provided with an integrated circuit of the single crystal silicon thin film transistor 2 having a BiCMOS structure.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device 1 will be described.

(Element part formation step)
First, as shown in FIG. 1, by using an ordinary BiCMOS process on a single crystal silicon substrate 90, a process such as oxidation, diffusion, epitaxial growth, lithography, etching, etc. is repeated as appropriate in a pattern designed in advance, thereby obtaining each element. Vertical bipolar transistor device part 10 (collector 15, base 16 and emitter 17) insulated by separation wall 71, CMOS structure transistor element part 9 (source 40, drain 41 and gate 42) and element part 9 ′ (source 50) , A drain 51 and a gate 52) are formed.

  The single crystal silicon substrate 90 can be processed using LSI manufacturing equipment, and the gate width of the CMOS structure transistor can be easily finely processed to 0.5 μm or less.

  At this time, in the vertical bipolar transistor element section 10, the uppermost layer is the emitter 17, the intermediate layer is the base 16, and the lowermost layer is the collector 15.

(First planarization film forming step)
Next, as shown in FIG. 2, a SiO 2 film is formed over the entire surface of the single crystal silicon substrate 90 so as to cover these transistors, and is flattened by CMP (Chemical and Mechanical Polishing) or the like, whereby the first flattening is performed. A chemical film 30 is formed. Here, CMP is mechanical polishing between a wafer attached to a supporting head (carrier), a polishing cloth (pad) attached to a polishing surface plate, and a polishing liquid (slurry) supplied thereto. This is a technique for polishing the surface of the substrate by balancing the chemical action.

(Step formation step)
Subsequently, as shown in FIG. 3, a stepped portion 32 is formed by etching or the like so that the thickness of the first planarizing film 30 is reduced only in the upper portion of the vertical bipolar structure transistor element portion 10. To do. At this time, a step is formed by the depth of the vertical bipolar structure transistor element portion 10 in the single crystal silicon substrate 90 as compared with the depth of the MOS structure transistor element portions 9 and 9 ′. The shape of the stepped portion 32 is preferably formed so as to expand obliquely upward from below. When the shape of the stepped portion 32 is formed so as to extend vertically upward from below, when ion implantation is performed as described below, the peeling layer 91 formed in the single crystal silicon substrate 90 has a vertical direction in the stepped portion 32. A portion corresponding to the extending portion cannot be formed. Then, the peeling layer 91 becomes discontinuous, and a part of the single crystal silicon substrate 90 cannot be peeled off.

(Peeling layer forming step)
Next, as shown in FIG. 4, hydrogen is ionized and implanted as a release material from above the first planarization film 30 provided with the stepped portion 32. The ion implantation is performed at an acceleration voltage of about 100 to 150 keV and a dose of about 5 × 10 ¹⁶ / cm 2. The implanted ions penetrate to the lower side of each transistor to form a peeling layer 91. Here, the implanted ions penetrate deeper below the vertical bipolar structure transistor element portion 10 and correspond to the thickness of the first planarization film 30, and below the MOS structure transistor element portions 9 and 9 ′. In order to penetrate more shallowly, a release layer 91 having a shape similar to the surface shape of the first planarization film 30 is formed. Further, the ion implantation range passes through the vertical bipolar structure transistor element portion 10 and the MOS structure transistor element portions 9 and 9 ′ so that the peeling layer 91 is formed while reaching the bottom of the single crystal silicon substrate. It is set by controlling the ion implantation energy. Further, the implanted ions may be a mixture of hydrogen and helium. Moreover, the substance mixed with hydrogen may be an inert gas and may not be helium.

(First electrode forming step)
Next, as shown in FIG. 5, by forming the emitter electrode 13 on the emitter 17 and the base electrode 12 on the base 16 of the vertical bipolar transistor element section 10, the single-crystal silicon thin film transistor 5 having the vertical bipolar structure and A single crystal silicon thin film transistor 6 having a CMOS structure is formed. Further, source electrodes 45 and 55, drain electrodes 46 and 56, and gate electrodes 47 and 57 are formed on the sources 40 and 50, the drains 41 and 51, and the gates 42 and 52 of the MOS structure transistor element portions 9 and 9 ', respectively. These electrodes 45 to 47 and 55 to 57 (first electrodes) are formed by sputtering or the like in which discharge melting is performed using a metal having a high melting point as an electrode and the molten particles are sprayed at a high speed. Ti or TiN is used as the electrode material. This is because after bonding the insulating substrate and the silicon substrate, it is necessary to select a metal that can withstand the temperature of the heat treatment performed to remove the substrate and improve the bonding strength.

(Second planarization film forming step)
Subsequently, as shown in FIG. 6, an SiO 2 film is formed over the entire surface of the single crystal silicon substrate 90 so as to cover these transistors 5 and 6, and is flattened by CMP or the like, whereby a second flattening film is formed. 31 is formed.

(Board bonding step)
Next, as shown in FIG. 7, the single crystal silicon substrate 90 is aligned at a predetermined position so that the surface of the second planarization film 31 becomes a contact surface, and is bonded to the insulating substrate 4 in close contact at room temperature. To do. The surface of the insulating substrate 4 may be covered with an oxide film having a thickness of about 100 nm. In general, in order to join an insulating substrate and a single crystal silicon substrate (the surface of which has been oxidized) without an adhesive, the cleanliness and activity of their surface states are extremely important.

  Therefore, the single crystal silicon substrate 90 and the insulating substrate 4 are cleaned and dried before bonding with a liquid called SC1 liquid before bonding in order to improve surface cleanliness and activity.

  The SC1 solution is prepared by mixing commercially available ammonia water (NH4OH: 30%), hydrogen peroxide water (H2O2: 30%), and pure water (H20). As an example, the said chemical | medical solution is mixed in the ratio of NH4OH: H2O2: H20 = 5: 12: 60. The chemical solution is kept at room temperature, and the single crystal silicon substrate 90 and the insulating substrate 4 are immersed in the SC1 solution for 5 minutes for cleaning.

  Thereafter, the single crystal silicon substrate 90 and the insulating substrate 4 are washed with pure water (specific resistance value: 10 MΩcm or more) under running water for 10 minutes and quickly dried with a spin dryer or the like. Then, the surface of the single crystal silicon substrate 90 and the surface of the insulating substrate 4 are brought into contact with each other and pressed with a slight force. Thereby, the single crystal silicon substrate 90 and the insulating substrate 4 are spontaneously bonded. The single crystal silicon substrate 90 and the insulating substrate 4 can be joined by the contribution due to the van der Waals force and the contribution due to hydrogen bonding. In this bonding, the closer the balance of the above three contributions of the surfaces of both substrates 4 and 90, the better the bonding performance.

  Here, a non-single-crystal silicon thin film transistor may be formed on the insulating substrate 4 in advance. In this case, the region where the single crystal silicon substrate is bonded needs to be covered only with the surface of the insulating substrate or the oxide film.

  Note that the non-single-crystal silicon thin film transistor may be formed after bonding a single-crystal silicon substrate.

(Substrate removal step)
Next, as shown in FIG. 8, the single crystal silicon substrate 90 bonded to the insulating substrate 4 is subjected to heat treatment (annealing or lamp annealing in an electric furnace at 450 ° C. to 600 ° C. for 30 minutes). The temperature is raised above the temperature at which hydrogen desorbs from Si. Then, along the release layer 91, the part opposite to the element part forming side part is removed by peeling. At this time, since the stepped portion 32 is formed in the peeling layer 91, the single crystal silicon substrate is above the single crystal silicon thin film transistor 5 having the vertical bipolar structure and above the single crystal silicon thin film transistor 6 having the CMOS structure. 90 has a raised shape.

  In addition, due to the heat treatment at this time, the reaction of Si—OH + —Si—OH → Si—O—Si + H 2 O occurs at the interface between the single crystal silicon substrate 90 and the insulating substrate 4 bonded by Van der Waals force or hydrogen bonding. As a result, the junction between the substrates 4 and 90 can be changed to a strong bond between atoms.

(Thinning step)
Next, as shown in FIG. 9, the collector 15 of the single-crystal silicon thin film transistor 5 having the vertical bipolar structure is exposed, and the parasitics of the sources 40 and 50 and the drains 41 and 51 of the single-crystal silicon thin film transistor 6 having the CMOS structure are exposed. In order to reduce the capacity, the single crystal silicon substrate 90 is etched from the upper surface to thin the transistors 5 and 6. At this time, the vertical bipolar single crystal silicon thin film transistor 5 and the CMOS single crystal silicon thin film transistor 6 have different heights. However, the step portion 32 is formed on the single crystal silicon substrate 90, and the thickness of the single crystal layer above the transistors 5 and 6 is different. Therefore, the exposure can be easily performed by uniformly thinning the upper surface of the single crystal silicon substrate 90.

(Second electrode formation step)
Subsequently, as shown in FIG. 10, a collector electrode (second electrode) 11 is formed on the exposed upper surface of the collector 15 of the single crystal silicon thin film transistor 5 having a vertical bipolar structure by sputtering or the like. As the electrode material, Al or an Al alloy is used. This is because Al has excellent compatibility with Si devices such as contact with Si, adhesion to SiO2, and etching processability with a photoresist mask. Moreover, as an Al alloy, Al-Si, an Al-Si-Cu alloy, etc. are suitable. Moreover, this electrode may not be a metal. For example, polysilicon doped at a high concentration may be used.

  When a non-single-crystal silicon thin film transistor is formed on the insulating substrate 4 in advance, as shown in FIG. 11, the gate electrodes (127, 137), source electrodes (125, 135), The drain electrodes (126, 136) are formed simultaneously with the collector electrode. When the collector electrode is not made of metal, the collector electrode and the electrode of the non-single-crystal silicon thin film transistor do not have to be formed at the same time.

  The semiconductor device 1 is manufactured by the above operation.

  Here, in this embodiment, the npn type vertical bipolar single crystal silicon thin film transistor 5 is formed. However, each of the p type, n type, and p type single crystal silicon is used to form a pnp type vertical bipolar structure. A single crystal silicon thin film transistor may be formed.

  Moreover, although the bipolar transistor created in this embodiment has shown that the top layer is a collector, it is not restricted to this. That is, the uppermost layer may be an emitter and the lowermost layer may be a collector.

  The bipolar transistor shown in this embodiment uses a polysilicon emitter, but it may be a bipolar transistor in which the emitter is formed by diffusion or ion implantation and diffusion.

(Function and effect)
Next, operational effects will be described.

  The semiconductor device 1 according to the present embodiment includes an insulating substrate 4 and a single crystal silicon thin film transistor 5 having a vertical bipolar structure provided thereon, and the single crystal silicon thin film transistor 5 includes the uppermost collector 15. The element part 10 having a laminated structure composed of the base 16 of the intermediate layer and the emitter 17 of the lowermost layer, and the collector electrode 11 provided on the upper layer side of the collector 15 of the element part 10 and electrically connected to the collector 15 And an emitter electrode 13 provided on a lower layer side than the emitter 17 and electrically connected to the emitter 17.

  For this reason, the distance between the emitter 17 and the collector electrode 11 is shortened, and the traveling time of carriers from the emitter 17 to the collector 15 is shortened. Therefore, the performance of the transistor such as high speed and high frequency characteristics is improved. Further, since it is not necessary to extend the region of the collector 15 to form reach through, the semiconductor device manufacturing process is simplified as compared with the conventional one, and further, the space of the semiconductor device can be saved.

  The semiconductor device 1 may further include a single crystal silicon thin film transistor 6 having a MOS structure on the insulating substrate 4.

  According to this, the single crystal silicon thin film transistor 2 having the BiCMOS structure including the single crystal silicon thin film transistor 5 having the bipolar structure and the single crystal silicon thin film transistor 6 having the MOS structure can be formed on the same insulating substrate 4. At this time, since the single crystal silicon thin film transistor 6 having a CMOS structure has an SOI structure provided on an insulating substrate, the performance of the device can be improved. Accordingly, when such a single crystal silicon thin film transistor 6 having a CMOS structure is provided on the same insulating substrate 4 as the single crystal silicon thin film transistor 5 having the above vertical bipolar structure, a BiCMOS structure having a higher speed and higher performance than the conventional one can be obtained. A single crystal silicon thin film transistor is obtained.

  Furthermore, the semiconductor device 1 may further include a non-single-crystal silicon thin film transistor 3 on an insulating substrate on which the vertical bipolar single crystal silicon thin film transistor 5 and the CMOS single crystal silicon thin film transistor 6 are formed.

  Therefore, in a semiconductor integrated circuit or the like, a single crystal silicon thin film transistor 6 having a CMOS structure is used in a portion requiring high performance transistor characteristics, and a non-single crystal silicon thin film transistor 3 is provided in a portion where the transistor performance does not have to be as high as that of a single crystal. Can be used as a high-performance semiconductor device.

  A display device 90 according to the present embodiment includes an active matrix substrate 95 including an insulating substrate 4 and a single-crystal silicon thin film transistor 5 having a vertical bipolar structure provided thereon, and the single-crystal silicon thin film transistor 5 is an element portion 10 having a laminated structure constituted by the uppermost layer collector 15, the intermediate layer base 16 and the lowermost layer emitter 17, and is provided on the upper layer side of the collector 15 of the element portion 10. And the collector electrode 11 connected to the emitter 17 and the emitter electrode 13 provided on the lower layer side of the emitter 17 of the element portion 15 and electrically connected to the emitter 17.

  When the above active matrix substrate 95 is used in a device such as a timing controller of a display device, high speed and high frequency characteristics that are particularly necessary can be given to the part.

  The manufacturing method of the semiconductor device 1 according to the present embodiment is a vertical bipolar transistor in which a stacked structure is formed on a single crystal silicon substrate 90 by an uppermost collector 15, an intermediate base 16 and a lowermost emitter 17. There is provided an element portion forming step for forming the element portion 10 and CMOS structure transistor element portions 9 and 9 ′ composed of gates 42 and 52, sources 40 and 50 and drains 41 and 51. And a first planarization film forming step for forming the first planarization film 30 so as to cover the single crystal silicon substrate 90 on which the vertical bipolar structure transistor element section 10 and the CMOS structure transistor element sections 9 and 9 ′ are formed. A peeling layer forming step of forming a peeling layer 91 by implanting a peeling material into the single crystal silicon substrate 90 through the first planarization film 30 as ions is provided. Furthermore, the base electrode 12 and the emitter electrode 13 electrically connected to the base 16 and the emitter 17 of the vertical bipolar structure transistor element portion 10 respectively on the single crystal silicon substrate 90 on which the release layer 91 is formed, and the CMOS The gate electrodes 47 and 57, the source electrodes 45 and 55, and the drain electrodes 46 and 56 that are electrically connected to the gates 42 and 52, the sources 40 and 50, and the drains 41 and 51, respectively, of the structure transistor element portion 9 and 9 ′. The first electrode forming step to be formed and the base electrode 12 and the emitter electrode 13 as well as the single crystal silicon substrate 90 on which the gate electrodes 47 and 57, the source electrodes 45 and 55, and the drain electrodes 46 and 56 are formed are covered. A second planarization film forming step for forming the second planarization film 31; Further, a substrate bonding step for bonding the single crystal silicon substrate 90 to the insulating substrate 4 so that the surface of the second planarization film 31 is a contact surface, and a single crystal silicon substrate 90 provided on the insulating substrate 4 are provided. A substrate removing step for removing the portion opposite to the element portion forming side portion along the peeling layer 91, a thinning step for thinning from the element portion forming side portion of the single crystal silicon substrate 90, and exposure by the thinning described above. And a second electrode forming step for forming a collector electrode 11 electrically connected to the collector 15 of the vertical bipolar transistor element section 10.

  According to this, the BiCMOS-structure single crystal silicon thin film transistor 2 provided with the vertical bipolar structure single crystal silicon thin film transistor 5 and the CMOS structure single crystal silicon thin film transistor 6 on the same insulating substrate 4 can be formed. A single crystal silicon thin film transistor 6 having a CMOS structure forms an SOI structure. Further, in the single-crystal silicon thin film transistor 5 having the vertical bipolar structure, the distance between the emitter 17 and the collector electrode 11 is shortened, and the traveling time of carriers from the emitter 17 to the collector 15 is shortened. Therefore, a single-crystal silicon thin film transistor having a BiCMOS structure with higher speed and higher performance than the conventional one can be obtained.

  In the method for manufacturing the semiconductor device 1, the peeling material may be a mixture of hydrogen and an inert material.

  Hydrogen is an effective stripping material, but may reduce the activity of the Si device acceptor. Therefore, if an inert substance is mixed, the proportion of hydrogen is further reduced, thereby obtaining an effect of reducing the decrease in acceptor activity caused by hydrogen.

  Further, in the method of manufacturing the semiconductor device 1, after the first planarization film 30 is formed and before the release layer 91 is formed, the film of the first planarization film 30 in the portion where the vertical bipolar structure transistor element portion 10 is formed. Even if the stepped portion 32 is formed in the first planarizing film 30 such that the thickness is thinner than the thickness of the first planarizing film 30 in the formation part of the CMOS structure transistor element portions 9 and 9 ′. Good.

  When the release material is ionized and implanted into the single crystal silicon substrate 90 through the first planarization film 30 having the stepped portion 32 in this way, the surface shape that can be formed according to the thickness of the first planarization film 30 is accommodated. A release layer 91 having the above shape is formed in the single crystal silicon substrate 90. That is, the release layer 91 is formed deep below the vertical bipolar structure transistor element portion 10 and shallow below the CMOS structure transistor element portions 9 and 9 ′. Then, after the part of the single crystal silicon substrate 90 is peeled off by the peeling layer 91, the single crystal silicon layer remaining on each of the transistors 5 and 6 is simultaneously removed by etching or the like. Thin film formation can be performed without changing the difference between the thick and thin portions. Accordingly, it is possible to easily reduce the thickness of the single crystal silicon layer formed in the single crystal silicon thin film transistor 6 having the thin CMOS structure as compared with the single crystal silicon thin film transistor 5 having the vertical bipolar structure.

Industrial application fields

  As described above, the present invention is useful for a semiconductor device including a single-crystal Si thin film transistor having a vertical bipolar structure, a manufacturing method thereof, and a display device.

It is sectional drawing which shows the element part formation step in the manufacturing method of the single crystal silicon thin-film transistor 2 of a BiCMOS structure. It is sectional drawing which shows the 1st planarization film | membrane formation step in the manufacturing method of the single crystal silicon thin-film transistor 2 of a BiCMOS structure. It is sectional drawing which shows the level | step-difference part formation step in the manufacturing method of the single crystal silicon thin-film transistor 2 of a BiCMOS structure. It is sectional drawing which shows the peeling layer formation step in the manufacturing method of the single crystal silicon thin-film transistor 2 of a BiCMOS structure. It is sectional drawing which shows the 1st electrode formation step in the manufacturing method of the single crystal silicon thin-film transistor 2 of a BiCMOS structure. It is sectional drawing which shows the 2nd planarization film formation step in the manufacturing method of the single crystal silicon thin-film transistor 2 of a BiCMOS structure. It is sectional drawing which shows the board | substrate joining step in the manufacturing method of the single crystal silicon thin-film transistor 2 of a BiCMOS structure. It is sectional drawing which shows the board | substrate removal step in the manufacturing method of the single crystal silicon thin-film transistor 2 of a BiCMOS structure. It is sectional drawing which shows the thin film formation step in the manufacturing method of the single crystal silicon thin-film transistor 2 of a BiCMOS structure. It is sectional drawing which shows the 2nd electrode formation step in the manufacturing method of the single crystal silicon thin-film transistor 2 of a BiCMOS structure. 1 is a cross-sectional view of a semiconductor device 1 according to an embodiment of the present invention. It is a top view of the display apparatus 94 which concerns on embodiment of this invention. 1 is a cross-sectional view of a conventional transistor 100 having a vertical bipolar structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 BiCMOS structure single crystal silicon thin film transistor 3 Non-single crystal silicon thin film transistor 4 Insulating substrate 5 Vertical bipolar structure single crystal silicon thin film transistor 6 CMOS structure single crystal silicon thin film transistor 7 n type MOS structure single crystal silicon thin film transistor 8 p-type MOS structure single crystal silicon thin film transistor 9, 9 ′ CMOS structure transistor element section 10 vertical bipolar structure transistor element section 11, 104 collector electrode 12 base electrode 13 emitter electrode 15, 110 collector 16, 101 base 17, 102 emitter 30 First planarizing film 31 Second planarizing film 32 Stepped portion 40, 120 n-type source 41, 121 n-type drain 42, 122 n-type gate 45, 55, 125, 135 Source electrode 46, 56, 1 6, 136 Drain electrodes 47, 57, 127, 137 Gate electrodes 50, 130 p-type sources 51, 131 p-type drains 52, 132 p-type gates 71, 73, 111 Element isolation wall 81 Silicon non-single crystal layer 90 Single crystal silicon Substrate 91 Release layer 94 Display device 95 Active matrix substrate 105 Semiconductor substrate 106 Reach-through 107 External base 108 High-concentration p-type polysilicon region 109 High-concentration n-type polysilicon region 112 SiO 2 film

Claims (7)

An insulating substrate;
A single-crystal silicon thin film transistor having a vertical bipolar structure provided on the insulating substrate;
With
The single crystal silicon thin film transistor is
An element part in which a laminated structure is constituted by the collector of the uppermost layer, the base of the intermediate layer and the emitter of the lowermost layer;
A collector electrode provided on the upper layer side of the collector of the element portion and electrically connected to the collector;
An emitter electrode provided on a lower layer side than the emitter of the element portion and electrically connected to the emitter;
A semiconductor device comprising: The semiconductor device according to claim 1,
A semiconductor device comprising a single-crystal silicon thin film transistor having a MOS structure on the insulating substrate. The semiconductor device according to claim 2,
A semiconductor device, further comprising a non-single-crystal silicon thin film transistor on the insulating substrate. An insulating substrate;
A single-crystal silicon thin film transistor having a vertical bipolar structure provided on the insulating substrate;
A display device including an active matrix substrate composed of silicon thin film transistors,
The single crystal silicon thin film transistor is
An element part in which a laminated structure is constituted by the collector of the uppermost layer, the base of the intermediate layer and the emitter of the lowermost layer;
A collector electrode provided on the upper layer side of the collector of the element portion and electrically connected to the collector;
An emitter electrode provided on a lower layer side than the emitter of the element portion and electrically connected to the emitter;
A display device comprising: A vertical bipolar transistor element having a stacked structure composed of a collector on the uppermost layer, a base on the intermediate layer and an emitter on the lowermost layer on a single crystal silicon substrate, and a transistor having a MOS structure composed of a gate, a source and a drain An element portion forming step for forming an element portion;
A first planarizing film forming step of forming a first planarizing film so as to cover the single crystal silicon substrate on which the vertical bipolar transistor element and the MOS transistor element are formed;
A release layer forming step of forming a release layer by implanting ions of a release material into the single crystal silicon substrate through the first planarization film;
A base electrode and an emitter electrode that are electrically connected to a base and an emitter of the vertical bipolar structure transistor element portion, respectively, and a gate of the MOS structure transistor element portion; A first electrode forming step of forming a gate electrode, a source electrode and a drain electrode electrically connected to each of the source and the drain;
A second planarization film forming step of forming a second planarization film so as to cover the single crystal silicon substrate on which the base electrode and the emitter electrode, and the gate electrode, the source electrode, and the drain electrode are formed;
A substrate bonding step of bonding the single crystal silicon substrate to an insulating substrate such that the surface of the second planarization film becomes a contact surface;
A substrate removal step of removing the portion of the single crystal silicon substrate provided on the insulating substrate on the opposite side of the element portion formation side portion along the release layer;
A thinning step of thinning from the element part forming side portion of the single crystal silicon substrate;
A second electrode forming step of forming a collector electrode electrically connected to the collector of the vertical bipolar transistor element portion exposed by the thinning, and a wiring electrically connecting each transistor;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 5,
The method for manufacturing a semiconductor device, wherein the peeling material is a mixture of hydrogen and an inert gas. In the manufacturing method of the semiconductor device according to claim 6,
After the first planarization film forming step and before the release layer forming step, the thickness of the first planarization film in the formation part of the vertical bipolar structure transistor element portion is greater than the MOS structure. A semiconductor device further comprising a step portion forming step for forming a step portion in the first planarization film so that the thickness of the formation portion of the transistor element portion is thinner than the thickness of the first planarization film. Manufacturing method.

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