JPH0794741A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device having a MOSFET which employs a SOI structure in which a minority carrier draw-out layer is formed without enlarging the size of a device. CONSTITUTION:An SOI layer 15 is formed through separation by LOCOS on an insulating film 14 formed on the surface of a silicon substrate 11 via a polycrystal silicon layer 12. This SOI layer 15 forms a source region 152 and a drain region 153 by holding a channel region 151 in between to construct a MOSFET, at the bottom of which a low-resistance polycrystal silicon layer 13 is formed as a minority carrier draw-out layer. This polycrystal silicon layer 13 connects to the channel region of the SOI layer 15 and connects to another SOI layer 18 formed on the insulating film 14, thus being derived form a substrate electrode 19. A bird beak region with a higher concentration of impurity, as compared with a flat part in the center is formed in the periphery of the channel region 151.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention is particularly applicable to SOI (Silicon
The present invention relates to a semiconductor device that includes a MOSFET that adopts an on-insulator structure.

[0002]

2. Description of the Related Art Amid the progress of high speed and high integration of semiconductor devices, a single crystal silicon layer (S
Various studies have been conducted on MOSFETs formed in the OI layer). In particular, the thickness of the SOI layer is MOSFET
In the case where the SOI layer is completely depleted when the channel is formed and is thinner than the maximum depletion layer width of the channel region, the short channel effect can be suppressed as compared with the MOSFET formed on the bulk silicon substrate, and the channel It is known that since the vertical electric field in the inside is relaxed, effective mobility is improved, and excellent characteristics such as high speed operation due to low stray capacitance are exhibited. In addition, a plurality of MOSFETs formed by SOI on the same substrate,
It is designed to be completely separated by an insulator, so that the latch-up phenomenon which is a problem in the complementary MOS circuit on the bulk silicon substrate does not occur.

When a plurality of MOSFETs are completely electrically separated by the insulator in this way, the MOSF
The ET channel region is in an electrically floating state. When the channel region is in an electrically floating state, minority carriers (holes in the case of N-channel MOSFET) generated by impact ionization caused by a high electric field near the drain change the potential of the channel region and are parasitic. Causes bipolar operation.
Therefore, the drain current rapidly increases due to this parasitic bipolar operation, and the source / drain breakdown voltage becomes extremely low as compared with a MOSFET formed on a bulk silicon substrate having the same element size.

As means for solving such a problem, for example, a semiconductor device disclosed in Japanese Patent Laid-Open No. 3-129777 has been proposed. 15A to 15C show the structure, in which an insulating film 52 is formed on the surface of a silicon substrate 51 and a single crystal silicon layer 53 is formed on the insulating film 52. A source region 54 and a drain region 55 are formed in the single crystal silicon layer 53, and a channel region 56 is formed between the source region 54 and the drain region 55, so that an SOI MOSFET is formed.

A gate insulating film 57 is formed on the upper surface of the single crystal silicon layer 53, and a gate electrode 58 is formed on the channel region 56 via the gate insulating film 57. The gate insulating film 57 is formed also on the side surface of the single crystal silicon layer 53, and the polycrystalline silicon layer 59 is formed on the outer peripheral portion thereof. In the polycrystalline silicon layer 59, a part of the gate insulating film is formed. It is arranged to be connected to the side surface of the removed source region 54. Reference numeral 60 is a source electrode, and 61 is a drain electrode.

That is, in the semiconductor device having such a structure, in order to connect the source region 54 and the polycrystalline silicon layer 59 to the metal wiring, it is necessary to form a contact hole protruding from the element region. Considering the alignment margin of the metal wiring pattern, the element size inevitably increases. The minority carrier extraction electrode is the source electrode 60.
Can be placed only in the form of making common contact with.

Further, Japanese Patent Laid-Open No. 3-288471 proposes a semiconductor device having a structure as shown in FIG. Also in this semiconductor device, similarly to the example of FIG. 15, an insulating film 52 is formed on the surface of a silicon substrate 51, a single crystal silicon layer 53 is formed on the insulating film 52, and a source is formed on the single crystal silicon layer 53. A region 54, a drain region 55, and a channel region 56 are formed. Then, a conductor layer 65 for extracting minority carriers is formed under the transistor region of the single crystal silicon layer 53, and the conductor layer 65 is extracted by the lead electrode 66.

According to this structure, since the conductor layer 65 for extracting the minority carriers is buried under the single crystal silicon layer 53, it is necessary to form the conductor layer 65. There is no need to increase the element size. However, in reality, the impurities contained in the conductor layer 65 diffuse into the channel region 56 during the transistor forming process, which makes it difficult to control the impurity concentration of the channel region 56.
Therefore, it becomes difficult to control the threshold voltage of the formed transistor, and the number of steps for forming a through hole for making contact with the buried conductor layer 65 is increased.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and enables a MOSFET adopting an SOI structure to be formed without increasing the size of the element and forming the same. It is easy to control the threshold voltage of the
An object of the present invention is to provide a semiconductor device in which the element layout is easy and the number of transistor forming steps is not particularly increased.

[0010]

A semiconductor device according to the present invention is a MOSFE having a channel region and a drain region and a source region on opposite sides of the channel region.
T is constituted by a thin film single crystal semiconductor layer formed on the surface of a semiconductor substrate via an insulator layer, and a channel of the single crystal semiconductor layer constituting the MOSFET is formed under the insulator layer of the semiconductor substrate. A polycrystalline semiconductor layer having the same conductivity type as the channel region connected to the peripheral portion of the region is formed, and the polycrystalline semiconductor layer has the same conductivity type as the channel region formed on the surface of the semiconductor substrate. It was connected to another single crystal semiconductor layer.

[0011]

According to the semiconductor device having such a structure, minority carriers (holes in the case of N channel) generated by impact ions in the vicinity of the drain pass through the polycrystalline semiconductor layer from the peripheral portion of the channel region to the surface. It is drawn out to the substrate electrode portion in the same manner as a bulk-type normal MOSFET. Therefore, the parasitic bipolar operation is suppressed and the source / drain breakdown voltage is improved. Further, in the peripheral portion of the channel region, the impurity concentration becomes high in a portion where impurities are diffused from the polycrystalline semiconductor layer, but the film thickness of the SOI layer in the peripheral portion of the channel region is equal to that of the flat SOI layer region in the central portion. The threshold voltage in the peripheral portion tends to be lower than that in the central portion. Therefore, the leakage current flowing in the peripheral portion becomes a problem in this kind of thin film MOSFET, but it is possible to prevent the leakage current by increasing the impurity concentration in the peripheral portion without changing the normal threshold voltage in the central portion. You can

Further, the polycrystalline semiconductor layer for extracting minority carriers has a contact with the channel region, but these can be processed with a sufficiently small size, and MOSF having substantially no extraction electrode.
It can be configured with the same size as ET. Further, the polycrystalline semiconductor layer can be arranged in the same manner as the well region of a bulk-shaped normal MOS, and the extraction electrode can be arranged independently of the source electrode like the substrate electrode of a normal MOS. The structure is easy, and it is not necessary to increase the number of forming steps.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the structure. A buried insulating film 14 made of SiO ₂ is formed on the surface of a single crystal silicon substrate 11 via a polycrystalline silicon layer 12 and a low resistance polycrystalline silicon layer 13. It

A thin-film single crystal silicon layer (SOI layer) 15 is formed on the insulating film 14, and the P-type channel region 151 is formed by implanting ions into the SOI layer 15.
At the same time, an N ⁺ type source region 152 and a drain region 153 are formed on both sides of the channel region, and a polycrystalline silicon gate 16 is formed corresponding to the channel region 151 via a gate insulating film. The single crystal silicon layer 15 has an N-channel MOSFET element-isolated by the LOCOS method.

Here, the film thickness of the SOI layer 15 is
The thickness is smaller than the maximum depletion layer width of the channel region 151, and the thickness is such that the SOI layer 15 is completely depleted during channel formation. For example, the formed N-channel MOSFE
The impurity concentration of the channel region 151 in the central portion of T is “8 ×
In the case of about 10 ¹⁶ cm ⁻³ ″, the film thickness of the SOI layer 15 is 1
It is less than 00 nm.

In the channel region 151 of the SOI layer 15, the central portion is a flat portion as shown in FIG. 7C, and the thickness of the peripheral portion of this flat portion gradually increases toward the outside. The bird's beak area becomes thinner. The bird's beak region of the channel region 151 is connected to the polycrystalline silicon layer 13 which is doped with boron and has a low resistance, and a contact region indicated by A in FIG. .

With this structure, the impurity concentration in the bird's beak portion of the channel region 151 is higher than that in the central flat portion of the channel region 151 due to the impurity (boron) diffused from the polycrystalline silicon layer 13. Has become. Therefore, the threshold voltage of the bird's beak portion is almost the same as or higher than the threshold voltage of the central portion of the channel region 151. An oxide film 17 separates the polycrystalline silicon layer 13 and the polycrystalline silicon layer 12.

The polycrystalline silicon layer 13 is connected to an SOI layer 18 formed independently, and this SOI layer 18
A substrate electrode 19 is formed corresponding to. In addition, SOI
The source electrode 20 and the drain electrode 21 are formed corresponding to the source region 152 and the drain region 153 of the layer 15, respectively. Reference numeral 22 is an interlayer insulating film.

The manufacturing process of the semiconductor device having such a structure will be described with reference to FIGS. In each of these drawings, FIG. 1A is a cross section corresponding to line aa in FIG. 1A, and FIG. 1B is a cross section corresponding to line bb.

First, as shown in FIG. 2, a pad oxide film 31 is formed on the surface of a first semiconductor substrate 30 made of a silicon substrate, and a nitride film 32 is further formed thereon. This nitride film 32 is an SOI region of a device to be formed later.
Patterning is performed with the mirror inversion pattern 33, and the region 34 that will be the field portion is removed. And FIG.
As shown by (4), thermal oxidation is performed by the LOCOS method so that the film thickness of the oxide film 35 in the field region 34 is, for example, about 600 nm.

Next, as shown in FIG. 4, the nitride film 32 and the pad oxide film 31 are removed, and then the entire surface is thermally oxidized to make SOI.
An oxide film 36 having a thickness of about 300 nm is formed corresponding to the region 33. Then, the portions connecting the polycrystalline silicon layer 13 and the SOI layer 15 and the SOI layer 18 shown in FIG. 1 are patterned, and the oxide film 35 is etched by, for example, a reactive ion etching method.
Contact holes 37 and 38 are formed.

However, this etching is performed under the condition that the oxide film 35 is removed by a thickness of about 500 nm.
The contact hole 37 exposes the polycrystalline silicon layer 13 only in a part of the patterned region,
In the case of 38, the polycrystalline silicon layer 13 is exposed in the entire patterned region.

When the contact holes 37 and 38 are formed in the oxide film 35 in this manner, the reduced pressure CV is obtained as shown in FIG.
Polycrystalline silicon 39 is deposited by the D method, and a region to be an N-channel MOSFET is patterned later to implant boron, for example, and a region to be a P-channel MOSFET is patterned to implant phosphorus, for example.

The polycrystalline silicon layer 39 thus ion-implanted with a predetermined impurity is patterned and etched into a desired region corresponding to the element region as shown in FIG. 7, and then the surface of the polycrystalline silicon 39 is etched. Then, an oxide film 40 having a thickness of about 100 nm is formed by, for example, a thermal oxidation method. Then, as shown in FIG. 8, a thick film polycrystalline silicon 41 is formed on the substrate to a thickness of about 5 μm, and the surface of the thick film polycrystalline silicon 41 is flattened and polished as shown in FIG. A mirror-like polished surface 411 is formed. As shown in FIG.
The mirror surface 42 of the second semiconductor substrate 42 separately prepared as shown in
1 are brought into contact with each other, and heat treatment is performed at 1100 ° C. for 1 hour in a nitrogen atmosphere, for example, and both are directly bonded and integrated.

FIG. 11 shows the state of FIG. 10 upside down, and shows the second surface on the polishing surface 411 of the polycrystalline silicon 41.
The first semiconductor substrate 42 with the semiconductor substrate 42 of
The side 30 is selectively polished so that the field oxide film 35 functions as a stopper to form SOI regions 15 and 18. Then, after adjusting the film thickness of the SOI layers 15 and 18, the source and drain regions as well as the channel region are formed in the SOI layer 15 by the normal MOS IC manufacturing process as shown in FIG. A metal wiring is formed and a predetermined semiconductor device is completed.

In this embodiment, in particular (A) of FIG.
As shown in the figure, the contact regions A of the polycrystalline silicon layer 13 and the channel region 151 of the SOI layer 15 are set within the entire width of the channel region 151. However, as shown in FIG. 12, the contact region B may be set in the half of the channel region of the SOI layer 15 on the source electrode side.

In the first embodiment shown in FIG. 1, when a high voltage is applied to the drain electrode 21, the SOI layer 15
Since the impurity concentration in the bird's beak portion of the channel region 151, which becomes thin in the peripheral portion of the
The width of the depletion layer formed in the PN junction between the channel region 151 and the channel region 151 is narrower in the thin bird's beak region around the central portion of the channel region 151 than in the flat portion, and the source / drain breakdown voltage may be reduced. There is.

However, in the second embodiment shown in FIG. 12, the polycrystalline silicon layer 13 for extracting minority carriers is used.
Since the contact region B between the channel region 151 and the channel region 151 is set to a half region on the source electrode side, the impurity concentration of the drain region side peripheral portion of the channel region 151 is flat in the central portion of the channel region 151. Of the SOI layer, and therefore the drain region 153 and the channel region 15
The width of the depletion layer formed in the PN junction between 1 does not change and the source / drain breakdown voltage does not decrease.

In the above-described embodiments, the case of the N ⁺ -type gate N-channel MOSFET has been described. However, the present invention is not limited to this, and the N ⁺ -type gate P-channel MOSFET, P
^{The same} can be applied to the case where the conductivity types of the impurities are opposite, such as an N channel MOSFET having a ⁺ type gate and a P channel MOSFET having a P ⁺ type gate.

FIG. 13 shows an example in which the second embodiment shown in FIG. 12 is applied to an inverter of a complementary MOSFET, and an N channel MOSFET 45 and a P channel MO are provided.
SFET46 is formed side by side. Then, a P-type polycrystalline silicon layer 131 is formed below the N-channel MOSFET 45 for extracting minority carriers, and an N-type polycrystalline silicon layer 132 is formed below the P-channel MOSFET 46.
Are arranged.

The polycrystalline silicon layers 131 and 132 for extracting minority carriers are SOI layers 451 and 461 which form MOSFETs 45 and 46, and substrate electrodes 191 and 192 which form electrodes for extracting minority carriers, respectively.
It may be configured in any pattern as long as it is connected to. Therefore, this polycrystalline silicon layer
131 and 132 have the same function as that of a bulk MOS well, but can occupy a smaller area than the well, and thus high integration is possible.

FIG. 14 shows a case where the SOI layer 15 is formed to be long in the semiconductor device shown in the second embodiment. In this case, the channel region 151 of the SOI layer 15 is set along the gate electrode 16, and the polycrystalline silicon layer 13 for extracting minority carriers is formed corresponding to both ends of the long channel region 151. The contact area B to be connected is set. This contact area B is S
It is formed corresponding to only the half of the peripheral portion of the OI region 15.

Thus, only the contact region B connected to the half region of the SOI layer 15 has a long SOI structure.
Due to the resistance of the channel region 151 of the layer 15, a sufficient effect of extracting minority carriers cannot be obtained. Therefore, in such a case, the SOI layer is located between the contact regions B.
The contact region A corresponding to the channel region 151 inside the layer 15 may be set. However, in this case, impurities are diffused from the polycrystalline silicon layer 13 into the channel region 151 and the impurity concentration of the channel region 151 near the contact region A is increased, so that the effective channel width is reduced and the current driving capability is reduced. Although it decreases, there is no problem in practical use.

[0034]

As described above, in the semiconductor device having the MOSFET adopting the SOI structure according to the present invention,
The parasitic bipolar operation is suppressed without sacrificing the degree of integration, and the breakdown voltage between the source and train is improved, and further, the leak current flowing in the bird's beak portion around the SOI layer of the MOSFET is reduced.

[Brief description of drawings]

FIG. 1A is a configuration diagram viewed from a plane for explaining a semiconductor device according to an embodiment of the present invention, and FIGS. 1B and 1C are lines aa and b- in FIG. 1A, respectively. Sectional drawing corresponding to line b.

FIG. 2 is a view for explaining the first step of the method for manufacturing a semiconductor device of the above embodiment, in which (A) is a- line in (A) of FIG.
The figure which shows the cross section of the part corresponding to the a line, (B) is also b
-The figure which shows the cross section of the part corresponding to a b line.

FIG. 3 is also a diagram for explaining the second step,
1A is a diagram showing a cross section of a portion corresponding to line aa in FIG. 1A, and FIG. 1B is a diagram showing a cross section of a portion corresponding to line bb.

FIG. 4 is also a diagram for explaining the third step,
1A is a diagram showing a cross section of a portion corresponding to line aa in FIG. 1A, and FIG. 1B is a diagram showing a cross section of a portion corresponding to line bb.

FIG. 5 is also a diagram for explaining the fourth step,
1A is a diagram showing a cross section of a portion corresponding to line aa in FIG. 1A, and FIG. 1B is a diagram showing a cross section of a portion corresponding to line bb.

FIG. 6 is also a diagram for explaining the fifth step,
1A is a diagram showing a cross section of a portion corresponding to line aa in FIG. 1A, and FIG. 1B is a diagram showing a cross section of a portion corresponding to line bb.

FIG. 7 is also a diagram for explaining the sixth step,
1A is a diagram showing a cross section of a portion corresponding to line aa in FIG. 1A, and FIG. 1B is a diagram showing a cross section of a portion corresponding to line bb.

FIG. 8 is also a diagram for explaining the seventh step,
1A is a diagram showing a cross section of a portion corresponding to line aa in FIG. 1A, and FIG. 1B is a diagram showing a cross section of a portion corresponding to line bb.

FIG. 9 is also a diagram for explaining the eighth step,
1A is a diagram showing a cross section of a portion corresponding to line aa in FIG. 1A, and FIG. 1B is a diagram showing a cross section of a portion corresponding to line bb.

FIG. 10 is also a diagram for explaining the ninth step,
1A is a diagram showing a cross section of a portion corresponding to line aa in FIG. 1A, and FIG. 1B is a diagram showing a cross section of a portion corresponding to line bb.

FIG. 11 is also a diagram for explaining the tenth step,
1A is a diagram showing a cross section of a portion corresponding to line aa in FIG. 1A, and FIG. 1B is a diagram showing a cross section of a portion corresponding to line bb.

FIG. 12 is a configuration diagram viewed from a plane for explaining a second embodiment of the present invention.

13A and 13B show a third embodiment to which the second embodiment is applied, in which FIG. 13A is a configuration diagram viewed from above, and FIG. 13B is a sectional view taken along the line bb of FIG. 13A.

14A and 14B also show a fourth embodiment to which the second embodiment is applied, in which FIG. 14A is a configuration diagram viewed from a plane, and FIG.
The bb sectional view taken on the line of FIG.

15A is a plan view of a conventional semiconductor device, FIG. 15B is a cross-sectional view corresponding to line bb in FIG. 15A,
Similarly, (C) is a sectional view taken along the line cc.

FIG. 16 is a cross-sectional configuration diagram illustrating an example of another conventional semiconductor device.

[Explanation of symbols]

11 ... Silicon substrate, 12 ... Polycrystalline silicon layer, 13 ... Polycrystalline silicon layer (low resistance), 14 ... Insulating film, 15 ... SOI
Layer, 151 ... channel region, 152 ... source region, 153 ... drain region, 16 ... gate, 17 ... oxide film, 18 ... SOI layer,
19 ... Substrate electrode, 20 ... Source electrode, 21 ... Drain electrode, 22
... Interlayer insulating film.

Claims (2)

[Claims] 1. A MOSFET comprising a thin film single crystal semiconductor layer formed on a surface of a semiconductor substrate with an insulator layer interposed between the channel region and a drain region and a source region on both sides of the channel region. Formed under the insulator layer of the semiconductor substrate,
A polycrystalline semiconductor layer of the same conductivity type as the channel region, which is connected to the peripheral portion of the channel region of the single crystal semiconductor layer forming the SFET, is formed on the surface of the semiconductor substrate. The semiconductor device is configured to be connected to another single crystal semiconductor layer of the same conductivity type as the channel region. 2. The peripheral portion of the channel region of the MOSFET is formed thinner than the film thickness of the central flat portion region, and the impurity concentration of the peripheral portion is set higher than the impurity concentration of the flat portion. The semiconductor device according to claim 1, wherein