JPH08111423A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PURPOSE: To enhance the performance of a semiconductor device employing a polycrystalline semiconductor while reducing the cost by forming a first polycrystalline semiconductor layer of first conductivity type for insulating a major surface of a substrate, forming a second polycrystalline semiconductor layer of second conductivity type thereon, and then forming a third polycrystalline semiconductor layer of first conductivity type further thereon. CONSTITUTION: A silicon oxide 2 is deposited on a substrate 1 and an amorphous silicon layer is formed thereon thus forming an isolation film 4. Amorphous silicon is then polycrystallized and implanted with ions thus forming an n type collector region, i.e., an n type polysilicon layer 3. An opening is made in the silicon oxide 5 and a p type silicon germanium layer is patterned to form a p type base region, i.e., a p type polysilicon germanium layer 6. Subsequently, an opening is made in a silicon oxide 7 and the n type polysilicon layer, formed on the entire surface, is patterned to form an n type emitter region, i.e., an n type polysilicon layer 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a polycrystalline semiconductor and a manufacturing method thereof.

[0002]

BACKGROUND OF THE INVENTION Conventionally, integrated circuits have been made using crystalline silicon. As the device miniaturization technology has developed, large-scale integration has become possible, and the integration of various circuits, and eventually the system integration on one chip, has become clear. In such a situation, integration of different types of circuits such as high breakdown voltage elements, power elements, analog circuits and digital circuits is required. Conventionally, dielectric isolation and SOI (Silicon On Insulator) have been used to meet such requirements.
Substrates have been used but have the drawback of high cost.

For example, it is preferable to integrally form a circuit for controlling the vertical power element with the element in order to improve the characteristics of the element and improve the usability for the user. However, if the control circuit is mounted on the high withstand voltage large current element, the control circuit may malfunction due to noise generated by the large current element. In order to avoid this, it is preferable to completely separate the control circuit from the power element with an oxide film or the like.

An SOI isolation technique is generally used as a technique for electrically and sufficiently isolating a power element and its associated circuit. This dielectric isolation technique involves a step of bonding two substrates and a step of forming a buried isolation region, and is considerably expensive. However, there has never been a low-cost alternative to this.

On the other hand, in order to reduce the cost of a transistor, which is a basic element of an integrated circuit, a MOS transistor is formed by using polycrystalline silicon formed on an insulating film instead of conventional expensive single crystal silicon. Attempts are being made to make it. In particular, since a MOS transistor using amorphous silicon can be formed at a relatively low temperature, in a liquid crystal display device using a glass substrate or the like, a TFT (Thin F
ilm Transistor) is becoming widely used. However, the polycrystalline silicon MOS transistor has a problem that the characteristics are essentially non-uniform.

An example of using a polycrystalline silicon bipolar transistor has been reported by, for example, K. Throngnumchai ("An Intelligent Discrete Power MOS.
FETWith Shorted Load Protection Using Thin-film Bi
olar Transistor ", Proceedings of 1992 Internationa
l Symposium on Power Semiconductor Devices & ICs,
Tokyo.pp.144-149). In this paper, a lateral thin film bipolar transistor of polycrystalline silicon formed by a double diffusion self-alignment technique on an insulating film of polycrystalline silicon is reported.

The above-mentioned paper is an example of using a lateral bipolar transistor in a protection circuit. However, in order to apply it to a high-precision analog circuit, it is desired to realize a high-performance polycrystalline silicon bipolar transistor comparable to a single crystal. It was rare. In particular, if a vertical polycrystalline bipolar transistor is realized, it can be expected to realize a highly accurate BiCMOS circuit in combination with a polycrystalline silicon CMOS circuit, and an intelligent power device can be manufactured at low cost.

If it becomes possible to manufacture a low-cost and high-performance MOS or bipolar transistor using such polycrystalline silicon, a polycrystalline layer is formed on a power element such as a vertical MOSFET, and a CMOS or bipolar is formed there. -It is possible to build in a transistor, etc. According to this method, the cost can be significantly reduced as compared with the method of forming an element by using dielectric isolation or SOI. The advantage of this method is that the active layer of the transistor forming the accessory circuit can be formed by using polycrystalline silicon for the gate of the vertical MOSFET.

However, in order to reduce the gate resistance of the MOSFET, it is considered desirable that the thickness of the polycrystalline silicon for gate is 0.5 μm or more. On the other hand, when a transistor is made of polycrystalline silicon, the thinner the polycrystalline layer is, the better the device characteristics are. Therefore, it is preferable to make the thickness as thin as possible. Therefore, vertical MOSF
When the polycrystalline silicon gate and the polycrystalline silicon transistor of ET were made at the same time, it was difficult to improve the characteristics of both, and an integrated circuit in which the accessory circuit was integrated with the vertical MOSFET was not realized.

[0010]

As described above, a semiconductor device using a polycrystalline semiconductor with good performance and low cost has not been realized. Therefore, it is an object of the present invention to provide a semiconductor device that uses a polycrystalline semiconductor layer and can be reduced in cost. More specifically, (1)
To realize a high-performance bipolar transistor made of polycrystalline silicon and to combine it with a CMOS circuit to realize a BiCMOS circuit made of polycrystalline silicon. (2)
High breakdown voltage MOS was developed and high breakdown voltage I made of polycrystalline silicon
To realize C, and (3) to realize an intelligent power device by combining these with a power element.

[0011]

In order to achieve the above object, a semiconductor device of the present invention (claim 1) is formed with a base plate having a main surface, and selectively and insulatively formed on the main surface. A first conductive type first polycrystalline semiconductor layer, a second conductive type second polycrystalline semiconductor layer selectively formed on the first polycrystalline semiconductor layer, and the second polycrystalline type semiconductor layer. It is characterized in that a transistor is provided by including a third polycrystalline semiconductor layer of the first conductivity type selectively formed on the crystalline semiconductor layer.

The first, second and third polycrystalline semiconductor layers are respectively used as an emitter region, a base region and a collector region, or vice versa to form a laminated bipolar transistor.

The energy band gap of the second polycrystalline semiconductor layer is preferably smaller than the energy band gap of the third polycrystalline semiconductor layer. The first to third polycrystalline semiconductor layers are preferably deposited polycrystalline silicon layers, and the second polycrystalline semiconductor layer is preferably deposited polycrystalline silicon germanium.

A fourth polycrystalline semiconductor layer formed insulatively is further formed in a region other than the region where the first semiconductor layer is formed on the main surface, and the fourth polycrystalline semiconductor layer is formed. A MOS transistor may be formed in the semiconductor layer.

The fourth polycrystalline semiconductor layer can be formed simultaneously with one of the first to third polycrystalline semiconductor layers. According to the research conducted by the present inventors, the pn junction formed by the p-type polycrystalline semiconductor and the n-type polycrystalline semiconductor has relatively good reproducibility. Therefore, in the case of a semiconductor device having a pn junction, the polycrystalline semiconductor is used. However, it has been found that variations in device characteristics can be suppressed to the extent that there is no practical problem.

If the material of the polycrystalline semiconductor layer is selected so that the energy band gap of the polycrystalline semiconductor layer of the base region is smaller than that of the polycrystalline semiconductor layer of the emitter region, the current amplification factor Hfe is increased. As a result, a more practical bipolar transistor can be realized.

A method of manufacturing a semiconductor device according to the present invention (claim 1)
3), a step of preparing a base plate whose surface is insulated, a step of depositing a first amorphous semiconductor layer on the surface of the base plate, and a heat treatment of the first amorphous semiconductor layer. Forming a first conductive type first polycrystalline semiconductor layer, terminating the surface of the first semiconductor layer with hydrogen, and forming a second conductive layer on the surface of the first polycrystalline semiconductor layer. A second polycrystalline semiconductor layer of a second conductivity type, a step of terminating the surface of the second semiconductor layer with hydrogen, and a third conductivity type third layer on the surface of the second polycrystalline semiconductor layer. And a step of depositing the amorphous semiconductor layer. The step of forming the first polycrystalline semiconductor layer of the first conductivity type is accomplished by implanting impurities of the first conductivity type.

A semiconductor device according to the present invention (claim 7).
Is a base plate having a main surface, a polycrystalline silicon layer having a thickness of 150 nm or less and 5 nm or more, which is formed insulatively on the main surface, and the polycrystalline silicon layer in a lateral direction so that ends thereof face each other. And a second region formed between the first and second regions of the first conductivity type and the first and second regions and connected to the first and second regions. And a third region of conductivity type to form a lateral bipolar transistor.

All semiconductor devices of the present invention have a thickness of 150 nm.
The invention was made by paying attention to the excellent crystallinity of the following polycrystalline silicon, and is preferably 100 nm or less, more preferably 50 nm or less and 5 nm or more. Further, the base plate may also be made of polycrystalline silicon.

A method of manufacturing a lateral bipolar transistor according to the present invention (claim 14) comprises a step of preparing a base plate whose surface is insulated, and forming a first conductivity type polycrystalline silicon layer on the surface of the base plate. Process,
A step of selectively and insulatingly forming a conductive layer on the first conductive type polycrystalline silicon layer; and using the conductive layer as a mask on the polycrystalline silicon layer on one side of the conductive layer. Selectively diffusing impurities of the second conductivity type to form a first region of the second conductivity type; and a step of forming the first region of the second conductivity type on the polycrystalline silicon layer on the other side of the conductive layer. Impurities of the first conductivity type are selectively diffused using the conductive layer as a mask, and the first conductivity type second region included in the first region and the first region are sandwiched between the first region and the first region. And a step of forming the opposing third regions, respectively.

A semiconductor device according to the present invention (claim 8) has a base plate made of polycrystalline silicon and a thickness of 15 formed selectively and insulatively on the main surface of the base plate.
A first polycrystalline silicon layer having a thickness of 0 nm or less and 5 nm or more, a gate electrode formed of a second polycrystalline silicon layer selectively and insulatingly formed on the first polycrystalline silicon layer, and the gate A first conductivity type first diffusion layer formed on the first polycrystalline silicon layer on one side surface of the electrode, and a first polycrystalline silicon layer on a side surface opposite to the side surface of the gate electrode. The second diffusion layer is formed and has a resistance value higher than that of the first diffusion layer and has a second diffusion layer of the same conductivity type as the first diffusion layer.

The present invention is also a high breakdown voltage MO invented by paying attention to the fact that the thin polycrystalline silicon layer has excellent crystallinity.
In the S-transistor, another semiconductor element made of polycrystalline silicon is provided in a region other than the region where the first polycrystalline silicon layer is formed on the base plate, and a high-quality semiconductor layer made of only polycrystalline silicon is provided. A breakdown voltage integrated circuit can be formed.

A semiconductor device according to the present invention (claim 9) comprises a first semiconductor layer of a first conductivity type made of a single crystal, and a second conductivity type selectively formed on the surface of the first semiconductor layer. Well, a second semiconductor layer of the first conductivity type selectively formed on the surface of the well of the second conductivity type, the first semiconductor layer, the well, and the second semiconductor layer. A first polycrystalline semiconductor layer formed so as to partially and insulatingly face each other, and the first polycrystalline semiconductor layer formed with the first polycrystalline semiconductor layer
A second polycrystalline semiconductor layer formed in a region different from the surface region of the semiconductor layer, the second polycrystalline semiconductor layer having a thickness different from that of the first polycrystalline semiconductor layer, and the second polycrystalline semiconductor layer is It is characterized in that it is divided into a plurality of electrically different areas, and the plurality of areas are components of at least one transistor.

The thickness of the second polycrystalline layer is preferably 150 nm or less and 5 nm or more. The plurality of areas may form a lateral bipolar transistor or a MOS transistor.

At this time, the gate electrode of the MOS transistor can be formed separately from the first polycrystalline layer or can be formed at the same time. A method of manufacturing a semiconductor device according to the present invention (claim 15) includes a step of selectively forming a second conductivity type base layer on the surface of a first conductivity type first semiconductor layer made of single crystal, A step of selectively forming a second semiconductor layer of a first conductivity type on the surface of a base layer of a second conductivity type, and at least a part of the first semiconductor layer, the base layer, and the second semiconductor layer. Forming a first polycrystalline semiconductor layer such that the first polycrystalline semiconductor layer and the first polycrystalline semiconductor layer have different thicknesses in regions different from the first polycrystalline semiconductor layer on the surface of the first semiconductor layer. And a step of insulatingly forming the second polycrystalline semiconductor layer, and a step of dividing the second polycrystalline semiconductor layer into a plurality of electrically different areas to form a transistor.

According to the present invention, since each region of the transistor is formed by the polycrystalline semiconductor layer, the cost can be significantly reduced as compared with the case of using the single crystal semiconductor layer. Further, even when the control circuit including the transistor is formed on the power element, it can be separated from the power element by an inexpensive element isolation method, so that a low-cost intelligent power device can be realized.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments will be described below with reference to the drawings. In the first to third embodiments, a vertical bipolar transistor made of a polycrystalline semiconductor and a BiCMOS circuit using the same will be described (claims 1 to 6 and 13). (Embodiment 1) FIG. 1 is a sectional view of a heterojunction bipolar transistor according to a first embodiment of the present invention.

That is, in FIG. 1, a collector region 3 made of a first polycrystalline semiconductor layer is formed on a base plate 1 with an insulating layer 2 interposed therebetween, and a collector region 3 is formed on the first polycrystalline semiconductor layer. A bipolar transistor including a base region 6 made of a polycrystalline semiconductor layer and an emitter region 8 formed on the second polycrystalline semiconductor layer and made of a third polycrystalline semiconductor layer is shown. The base plate 1 may be single crystal silicon or polycrystalline silicon.

This transistor will be described in more detail according to the manufacturing process. First, the surface of the silicon substrate 1 is oxidized to form a silicon oxide layer 2 having a thickness of about 1 μm. Next, a thickness of 100 to 100 is formed on the silicon oxide layer 2.
After forming an amorphous silicon layer having a thickness of about 0 nm, the element isolation insulating film 4 is formed.

Next, the amorphous silicon layer is annealed in an oxygen atmosphere at 600 ° C. for 24 hours to crystallize (polycrystal) the amorphous silicon layer to form polycrystalline silicon to be an n-type collector region. Form the layers. After that, n-type impurities are ion-implanted into this polycrystalline silicon layer to form an n-type polycrystalline silicon layer 3 as an n-type collector region. The element isolation insulating film 4 may be formed after the n-type polycrystalline silicon layer 3 is formed.

Next, a silicon oxide layer 5 having a thickness of 500 nm is formed on the entire surface by the CVD method, and then an opening is formed in this silicon oxide layer 5. This opening is used to contact the p-type polycrystalline silicon germanium layer 6 and the n-type polycrystalline silicon layer 3 as a p-type base region formed in a later step.

Next, the entire surface is doped with boron to a thickness of 20 to
P-type polycrystalline silicon germanium having a thickness of about 30 nm is formed by a CVD method in a vacuum atmosphere. Then, the p-type polycrystalline silicon germanium layer is patterned to form a p-type polycrystalline silicon germanium layer 6 as a p-type base region.

Next, after a silicon oxide film 7 is formed on the entire surface, an opening is formed in this silicon oxide film 7. This opening is used as an n-type emitter region formed in a later step.
-Type polycrystalline silicon layer 8 and p-type polycrystalline silicon germanium layer 6
Used to contact with.

Next, the entire surface is doped with phosphorus to a thickness of 500 n.
After forming the n-type polycrystalline silicon layer of about m, the n-type polycrystalline silicon layer is patterned to form the n-type polycrystalline silicon layer 8 as the n-type emitter region.

Next, after depositing an interlayer insulating film 9 on the entire surface, contact holes are opened in the interlayer insulating film 9 for the base, emitter and collector regions. Finally, Al
After depositing a conductive film such as a film, the conductive film is patterned to form a base electrode 10, an emitter electrode 11 and a collector electrode 12 to complete the basic structure of the bipolar transistor.

According to this embodiment, since each region of the bipolar transistor is formed of the polycrystalline semiconductor layer,
The cost is significantly reduced as compared with the case where a single crystal semiconductor layer is used.

Further, according to the research conducted by the present inventors, the pn junction formed by the p-type polycrystalline semiconductor and the n-type polycrystalline semiconductor has relatively good reproducibility. Even a bipolar transistor using a conductive layer,
It is possible to suppress variations in element characteristics to such an extent that there is no practical problem.

Further, in this embodiment, silicon germanium is used as the base material. Since this silicon germanium has an energy bandgap smaller than that of silicon which is the emitter material, the silicon germanium as the base material is polycrystalline. However, a sufficiently large current amplification factor Hfe can be obtained. Further, since the polycrystalline silicon germanium can have a higher germanium content ratio than the single crystal silicon germanium, the current amplification factor Hfe can be increased also by this.

Further, according to the present embodiment, since each transistor region is formed of the polycrystalline semiconductor layer, the bipolar transistor can be formed at a lower temperature than in the case of the single crystal semiconductor layer. (Embodiment 2) FIG. 2 is a sectional view showing the structure of a heterojunction bipolar transistor according to a second embodiment of the present invention. The parts corresponding to those of the bipolar transistor shown in FIG. 1 are designated by the same reference numerals as those shown in FIG.

The main difference between the bipolar transistor of this embodiment and that of the previous embodiment is the stacking order of the transistor regions. That is, in this embodiment, the emitter region 8, the base region 6 and the collector region 3 are stacked in this order in the respective transistor regions. Further, in this embodiment, the collector region 3 is formed of the n ⁺ -type polycrystalline silicon layer 3a,
It is formed of a laminated film of the n ⁻ -type polycrystalline silicon layer 3b to achieve a high breakdown voltage. (Embodiment 3) FIG. 3 shows Bi according to a third embodiment of the present invention.
It is sectional drawing which shows the structure of a CMOS transistor.

On the base plate 21, the collector region 24 and the C of the bipolar transistor are formed via the insulating layer 22.
A first polycrystalline semiconductor layer which is insulated from a MOS transistor region, a base region 31 of the bipolar transistor which is formed on the first polycrystalline semiconductor layer and is composed of a second polycrystalline semiconductor layer; An emitter region 33 of the bipolar transistor, which is formed on the second polycrystalline semiconductor layer and is formed of a third polycrystalline semiconductor layer, is formed.

This semiconductor device will be described in more detail according to the manufacturing process. First, the silicon substrate 21 is oxidized to form a silicon oxide layer 22 having a thickness of about 1 μm. Next, a thickness of 100 to 10 is formed on the silicon oxide layer 22.
After forming an amorphous silicon layer of about 00 nm,
The element isolation insulating film 23a is formed.

Then, the amorphous silicon layer is annealed in an oxygen atmosphere at 600 ° C. for 24 hours to crystallize (polycrystal) the amorphous silicon layer, thereby forming n ⁻ type collector regions 24a, n type. Collector region 24b, source regions 27Sn, 27Sp, drain region 27
A first polycrystalline silicon layer to be Dn, 27Dp and channel regions 28n, 28p is formed.

Next, the element isolation insulating films 23a, 23b and 23 are formed by partially oxidizing the first polycrystalline silicon layer.
form c. As a result, the first polycrystalline silicon layer is separated into the collector region 24 and the CMOS transistor region, and the CMOS transistor region is further divided into the p-channel type M.
The OS transistor region and the n-channel type MOS transistor region are separated.

Next, low-dose phosphorus is ion-implanted into the first polycrystalline silicon layer to form an n ⁻ -type collector region.
^A -type polycrystalline silicon layer 24a is formed. Ion implantation for adjusting the threshold value is performed on the first polycrystalline silicon layer to form an n-type channel region 28n and a p-type channel region 28p.
To form.

After that, a CMOS transistor is formed. First, the surface of the first polycrystalline silicon layer is thermally oxidized to form a gate oxide film 25 having a thickness of about 20 nm. Next, after forming a second polycrystalline silicon layer on the gate oxide film 25, this second polycrystalline silicon layer is processed by reactive ion etching (RIE) to form a gate electrode 26. The gate electrode 2 is formed by RIE at this time.
The gate oxide film 25 in regions other than 6 is also removed.

Next, phosphorus is selectively ion-implanted into the first polycrystalline silicon layer to form an n-type source region 27S.
The n-type and n-type drain regions 27Dn are formed, and boron is selectively ion-implanted into the first polycrystalline silicon layer to form the p-type source region 27Sp and the p-type drain region 27.
Form Dp. At this time, the n-type collector region 24b is also formed at the same time by the ion implantation of phosphorus. Then, the impurities are activated by a heat treatment at a temperature of about 800 ° C.

Next, after the silicon oxide layer 30 is formed on the entire surface by the CVD method, an opening is formed in the silicon oxide layer 30. This opening is used to contact the p-type polycrystalline silicon germanium layer 31 and the n ⁻ -type polycrystalline silicon layer 24a as a p-type base region formed in a later step.

Next, the natural oxide film formed on the surface of the n ⁻ -type polycrystalline silicon layer 24a at the bottom of the opening is removed with hydrofluoric acid, and then washed with ultrapure water to obtain n ^−.
The surface of the type polycrystalline silicon layer 24a and the like is terminated with hydrogen.

Next, the entire surface is doped with boron to a thickness of 20 to
A p-type polycrystalline silicon germanium layer having a thickness of about 30 nm is formed by a CVD method in a vacuum atmosphere. At this time, it is desirable to form a high-concentration p-type polycrystalline silicon germanium layer at a low temperature of 800 ° C. or lower, preferably 500 to 600 ° C. or lower. This is to suppress the diffusion of boron and effectively prevent the diffusion of boron into the collector region.

Thereafter, the p-type polycrystalline silicon germanium layer is patterned to form a p-type polycrystalline silicon germanium layer 31 as a p-type base region. At this time, since the surface of the n ⁻ -type polycrystalline silicon layer 24a is terminated by hydrogen, the pn junction interface between the n ⁻ -type polycrystalline silicon layer 24a and the p-type polycrystalline silicon germanium layer 31 becomes good. .

Next, after forming a silicon oxide film 32 on the entire surface, an opening is formed in this silicon oxide film 32. This opening is used to contact the n-type polycrystalline silicon layer 33 and the p-type polycrystalline silicon germanium layer 31 as an n-type emitter region formed in a later step.

Next, the natural oxide film formed on the surface of the p-type polycrystalline silicon germanium layer 31 at the bottom of the opening is removed with hydrofluoric acid, and then washed with ultrapure water to obtain p.
The surface of the type polycrystalline silicon germanium layer 31 and the like is terminated with hydrogen.

Next, the entire surface is doped with phosphorus to a thickness of 500 n.
After forming about n m-type polycrystalline silicon layer, this n-type polycrystalline silicon layer is patterned to form an n-type polycrystalline silicon layer 33 as an n-type emitter region.

At this time, the p-type polycrystalline silicon germanium layer 3
Since the surface of 1 is terminated with hydrogen, the pn of the p-type polycrystalline silicon germanium layer 31 and the n-type polycrystalline silicon layer 33 is
The bonding interface is good.

Next, after depositing an interlayer insulating film 34 on the entire surface,
Contact holes for each transistor region are opened in the interlayer insulating film 34. Finally, a conductive film such as an Al film is deposited on the entire surface, and then the conductive film is patterned to form a base electrode 35, an emitter electrode 36, a collector electrode 37, a source electrode 38S, a drain electrode 38D, a gate lead electrode (not shown). Forming a source electrode 39S, a drain electrode 39D, a gate lead electrode (not shown),
Complete the basic structure of a BiCMOS transistor.

In the BiCMOS transistor having such a structure, since each transistor region of the bipolar transistor and the CMOS transistor is formed by the polycrystalline semiconductor layer, the cost can be reduced as in the first embodiment.

Further, in the case of the present embodiment, after the natural oxide film is removed, the surface of the polycrystalline semiconductor layer which becomes the transistor region for forming the pn junction is terminated with hydrogen, so that a good pn junction can be obtained. . That is, the pn of the n ⁻ -type polycrystalline silicon layer 24 a and the p-type polycrystalline silicon germanium layer 31
The junction interface and the pn junction interface between the p-type polycrystalline silicon germanium layer 31 and the n-type polycrystalline silicon layer 33 are good. Therefore, the recombination current generated at the pn junction interface is reduced, and the current amplification factor Hfe can be further increased.

In this embodiment, polycrystalline silicon, which is a material whose diffusion is extremely fast, is used. However, since a high-concentration p-type polycrystalline silicon germanium layer is formed at a low temperature of 800 ° C. or lower, A good bipolar transistor can be manufactured.

Further, in the present embodiment, since the bipolar transistor requiring the low temperature process is formed after the process of the CMOS transistor requiring the high temperature process is completed, the CMOS transistor and the bipolar transistor are reliable on the same substrate. It can be formed without lowering the property.

Further, by using a BiCMOS transistor having a high performance vertical bipolar transistor, a highly accurate analog circuit can be realized.
The present invention is not limited to the above embodiment.

For example, although the silicon substrate is used as the base plate in the first to third embodiments, a glass substrate or a quartz substrate may be used instead. Also, the first
In the third embodiment, the case of the heterojunction bipolar transistor has been described, but the present invention can be applied to a normal bipolar transistor if a polycrystalline silicon layer having a low impurity concentration is used as the base region.

Further, as shown in FIG. 4, an insulating layer 42 having an opening is formed on a single crystal silicon substrate 41, and the single crystal silicon substrate 41 exposed at the bottom of the opening is used as a seed to form a single crystal silicon layer. 43 may be solid-phase grown, and the single crystal silicon layer 43 may be used to form the device of the above embodiment. For example, the single crystal silicon layer 43 may be used as the collector region 3 in FIG. That is, it is not necessary for all the transistor regions to be polycrystalline semiconductor layers.

Further, since the pn junction formed by the p-type polycrystalline semiconductor and the n-type polycrystalline semiconductor has good reproducibility, even if each of the collector, base and collector regions is formed of a polycrystalline semiconductor layer, the device characteristics It becomes possible to realize a bipolar transistor with a small variation.

By the way, as a result of a detailed study on the polycrystalline silicon film, the film thickness of the polycrystalline silicon film is 100 nm.
It was found that when the thickness was reduced to the following, a crystal having very excellent crystallinity was obtained. The present inventors have found that a thin bipolar film can be used to obtain a lateral bipolar transistor having performance comparable to that of a single crystal film. Next, the lateral bipolar transistor will be described in Example 4 (claims 7 and 1).
4)). (Embodiment 4) FIG. 5 is a schematic plan view of a bipolar transistor according to a fourth embodiment of the present invention, and FIG. 6 is a sectional view taken along the line A--A of FIG. An emitter region 55, a base region 56, a collector region 53 formed on a polysilicon substrate 51 with a silicon oxide film 52 interposed therebetween.
A lateral bipolar transistor consisting of
This transistor can be manufactured by a process compatible with the manufacturing process of a MOS transistor.

A more detailed structure of this transistor will be sequentially described according to the manufacturing process. First, a polysilicon substrate 51 is prepared, and an oxide film 52 is formed thereon. The thickness of the oxide film 52 is such that the breakdown voltage of the transistor is, for example, 250V.
When the following is low, it is 1 μm or less. Preferably 300n
m to 500 nm is preferable. When the withstand voltage is 500 V or more, it is 2 μm or more.

Next, amorphous silicon 53 is deposited on this oxide film to a thickness of about 100 nm. This film thickness is finally set so that the silicon layer below the gate oxide film 57 of the MOSFET is 150 nm or less, preferably 100 nm or less, and more preferably about 50 nm. However,
When the thickness is less than 5 nm, the film resistance increases, so the film thickness is 5
nm or more is preferable. Further, in order to improve the quality of the silicon film, annealing at 600 to 800 ° C. for 10 to 20 hours is followed by annealing at a high temperature of 1100 ° C. or higher. When the latter annealing temperature is 1300 ° C. or higher, the most remarkable effect is obtained.

The bipolar transistor is formed on the thin silicon layer 53 of which the film quality is improved, and the n-channel MO transistor is formed.
It is formed by adding p base diffusion to the process of forming S. First, the p base region 56 is selectively diffused into the polysilicon region on one side of the gate electrode 59, and then the diffusion corresponding to the source and drain layers of the MOS is performed, so that the emitter region 55 is formed.
And a collector extraction region 54 is formed. Then, the base take-out region 58 is formed to complete the lateral bipolar transistor.

In this embodiment, the polycrystalline silicon layer 53 is set to 1
By annealing at a temperature of 00 nm or less and at a temperature of 1100 ° C. or more, the grain of polycrystalline silicon is increased and the crystallinity is improved. Can be created.

When the thin polycrystalline silicon layer used in the lateral bipolar transistor is applied to MOS, a high breakdown voltage MOS transistor becomes possible. Next, this high withstand voltage M
The OS (corresponding to claim 8) will be described. (Embodiment 5) FIG. 7 shows the structure of a high breakdown voltage MOSFET to which a thin polycrystalline silicon film according to a fifth embodiment of the present invention is applied. A thin polycrystalline silicon layer 53 is formed on the polysilicon substrate 51 via an oxide film 52. The high breakdown voltage transistor formation region is isolated from peripheral elements by an element isolation insulating film 60 formed by selective oxidation (LOCOS). The gate oxide film 5 is formed on the channel formation region 61.
A gate electrode 59 is formed via the gate electrode 7. The channel region 61 may be a low concentration n-type. Gate electrode 59
Source / drain regions 62, 63 + 64 are formed on both sides of the.

High resistance thin film layer 63 for realizing high breakdown voltage
Is ion-implanted with phosphorus of 1 × 10 ¹¹ to 2 × 10 ¹³ / cm ² . In polycrystalline silicon, not all the implanted ions are activated and the activation rate is 10
%, The optimum dose is almost an order of magnitude higher than that of crystalline silicon.

By combining the lateral bipolar transistor or high breakdown voltage MOSFET and the polycrystalline silicon device described in the first to third embodiments, an inexpensive high breakdown voltage IC made of only polycrystalline silicon can be realized.

Next, an example of an intelligent power device in which an accessory circuit such as a control circuit made of the above-mentioned polycrystalline semiconductor is formed on a vertical MOSFET power element will be described as Example 6.
To 10 (corresponding to claims 9 to 12 and 15). (Embodiment 6) FIG. 8 is a sectional view of a power device having a control circuit according to a sixth embodiment of the present invention. A power element 71 formed of a vertical MOSFET is formed on the right side of the drawing, and a control circuit 72 formed of the BiCMOS circuit described in the third embodiment is formed in the central portion. In this embodiment, the control circuit 72 is formed via an insulating layer 76 (22) on the n-type substrate on which the vertical MOSFET is formed. Control circuit 72
Is composed of the BiCMOS circuit of the third embodiment (FIG. 3), the same parts as those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted. However, in FIG. 8, for convenience, only the bipolar transistor and nMOS transistor portions are shown.

The detailed structure of this device will be described according to the manufacturing method. First, as shown in FIG. 8, a p-type diffusion layer 77a is formed on the surface of the substrate on which the control circuit 72 is formed. The diffusion layer 77a may be the same diffusion layer as the p-type guard ring 78 formed inside the power element to secure the breakdown voltage, and is formed in the guard ring 78 or in contact therewith.

Next, after forming the gate oxide film 79 of the power element 71, a thick oxide film 76 (22) is formed in the portion where the control circuit 72 is formed by the LOCOS method. Further, about 0.6 μm of amorphous silicon is deposited on the entire surface, and the amorphous silicon layer is polycrystallized by annealing in an oxygen atmosphere at 600 ° C. for 24 hours.

In the portion forming the p base of the vertical power MOSFET 71, the polycrystalline silicon is removed by PEP, and boron is ion-implanted using the remaining polycrystalline silicon as a mask. Subsequently, boron is diffused by heating to form a p base (well) 77b.

An n ⁺ (or p ⁺ ) layer 73 is formed on the back surface of the silicon substrate 75 via an n buffer layer 74 to serve as a drain of a vertical MOSFET (IGBT in the case of p ⁺ ). After that, the BiCMOS circuit of the control circuit 72 is used in the third embodiment.
Vertical MOSFET formed by the same process as (Fig. 3)
Complete an intelligent power device that integrates the control circuit and its control circuit. (Embodiment 7) FIG. 9 is a sectional view of a power device having a control circuit according to a seventh embodiment of the present invention. This embodiment is basically the same as the sixth embodiment, but the method of forming the bipolar transistor of the control circuit is different. That is, a power element 71 composed of a vertical MOSFET is formed on the right side of the drawing, and a control circuit 72 'using the lateral bipolar transistor described in the fourth embodiment is formed in the central portion. Also in this embodiment, the control circuit 72 'is formed via the insulating layer 76 on the n-type substrate on which the vertical MOSFET is formed.

The control circuit 72 is composed of the lateral bipolar transistor of the fourth embodiment (FIG. 5), and each constituent region of the transistor is single crystallized by the method shown in FIG. different. Therefore, the same parts as those in FIG. 5 are denoted by the same numbers with a dash to facilitate understanding. In FIG. 9, only the bipolar transistor and nMOS transistor portions are shown for convenience, but it is assumed that a pMOS transistor is also formed and a CMOS circuit is used.

The detailed structure of this device will be described according to the manufacturing method. First, as shown in FIG. 9, the control circuit 72 '
A p-type diffusion layer 77a is formed on the surface of the substrate for forming.
The diffusion layer 77a may be the same diffusion layer as the p-type guard ring 78 formed inside the power element to secure the breakdown voltage, and is formed in the guard ring 78 or in contact therewith.

Next, after forming the gate oxide film 79 of the power element 71, a thick oxide film 76 (52) is formed in the portion where the control circuit 72 'is formed by the LOCOS method. Further, an opening 80 for exposing the substrate is formed in the vicinity of the portion where the lateral bipolar transistor is formed in the control circuit 72 '.

Next, amorphous silicon is deposited on the entire surface by about 0.
After depositing 1 μm, amorphous silicon near the portion in contact with the substrate is crystallized by a ZMR method using a heater. At this time, the other part of the amorphous silicon becomes polycrystalline silicon. The conduction path with the substrate through the opening 80 is cut after the single crystallization of the amorphous silicon is completed, and the single crystallized amorphous silicon is separated from the substrate.

The polycrystalline silicon in the portion of the power element 71 is removed, gate oxidation is performed on the entire surface, and a polycrystal of 0.6 μm is deposited on the entire surface to form the gate electrode of the CMOS transistor and the gate electrode of the power element 71.

In the portion forming the p base of the vertical power MOSFET 71, the polycrystalline silicon is removed by PEP, boron is ion-implanted using the remaining polycrystalline silicon as a mask, and then the p base (well) 77b is diffused. To form. This boron ion implantation and diffusion process is also used as the base diffusion of the base 56 'of the bipolar transistor formed in the crystallized amorphous silicon portion.

The bipolar transistor is formed by the same process as that of the fourth embodiment (FIGS. 5 and 6). In FIG. 9, reference numeral 55 'is an emitter region, 53' is a collector region, and 54 'is a collector extraction region.
Reference numerals 90 and 91 are collector and emitter electrodes, respectively. The base electrode is not visible in this cross section.

An nMOS transistor is formed in the polycrystalline silicon region isolated by the element isolation insulating film 81. Reference numerals 82 and 84 are regions to be source / drain later,
83 is a channel formation region. CM of polycrystalline silicon
In the OS transistor, the polycrystalline silicon of the channel portion 83 is usually a high resistance n-type, but in order to control the threshold value, low concentration p well or n well ion implantation and diffusion may be performed, respectively.

A gate oxide film 85 having a film thickness of 50 nm is formed on the channel forming region 83 of polycrystalline silicon by thermal oxidation, and polycrystalline silicon for the gate electrode 86 of the CMOS transistor is formed simultaneously with the gate electrode of the power element 71. Then, phosphorus is implanted to obtain high-concentration n-type polycrystalline silicon. The polycrystalline silicon other than the portion which becomes the gate electrode 86 of the CMOS is removed, and the n-type source / drain region and p
A type source / drain region (not shown) is formed by implanting As and B, respectively. Reference numerals 87 and 88 are electrodes in the source / drain regions.

As described above, the intelligent power device in which the vertical MOSFET and its control circuit are integrated is completed. (Embodiment 8) FIG. 10 is a sectional view schematically showing the structure of a power element with a control circuit according to an eighth embodiment of the present invention. Also in this embodiment, a control circuit 91a made of polycrystalline silicon is provided on the semiconductor substrate on which the vertical MOSFET 90 is formed.
91b is incorporated. A more detailed configuration of this power element will be described according to the manufacturing process.

First, an n-type substrate 92 made of single crystal silicon
Surface is oxidized to about 1 μm. Next, in order to form a gate electrode of the vertical MOSFET part, 50 is formed on the surface of the substrate.
Gate oxidation is performed to a thickness of about nm to form a gate oxide film 93. A polycrystalline silicon layer is deposited on this by about 1 μm,
By patterning this polycrystalline silicon layer,
The gate electrode 94 is formed. After this, this gate electrode 9
P-type impurities are ion-implanted from the surface using 4 as a mask,
A base region (well) 95 is formed. Then, an n-type impurity is ion-implanted to form an emitter region 96. Reference numeral 98 is a p-base contact region.

On the other hand, n-type impurities are diffused from the back surface of the substrate 92, and the n-type buffer layer 99 and the n ⁺ -type drain layer 10 are formed.
0 is formed to complete the vertical MOSFET section. Reference numeral 101 is a drain electrode. At this time, when the p ⁺ type drain layer is diffused instead of the n ⁺ type drain, a vertical IGBT is formed.

Next, the step of forming the thin film transistors 91a and 91b is performed. First, the oxide film 104 having a thickness of about 500 nm
Is deposited on the entire surface of the substrate by the CVD method. This oxide film 104
150 n thick to form a thin film transistor
An amorphous silicon layer having a thickness of m or less, preferably 100 nm or less, more preferably about 50 nm is deposited. The amorphous silicon layer is heated to be polycrystallized to form a polycrystalline silicon layer. At this time, annealing is performed at a temperature of 600 ° C. to 800 ° C. for 10 to 20 hours.
By annealing at a temperature of 00 ° C. or higher, the crystal grain size can be increased, and the transistor characteristics are improved. This polycrystalline silicon layer is doped with p-type and n-type impurities by 10 ¹² cm.
P-type and n-type active layers 111 to 11 which form respective regions of a transistor by ion implantation with a low dose amount of about ⁻²
Create 7.

Further, second gate oxidation is performed to form a MOS transistor 91b, and a second gate oxide film 105 is formed. The gate electrode 1 is formed on the oxide film 105.
A polycrystalline silicon layer to be 06 is deposited. After patterning this polycrystalline silicon layer to form the gate electrode 106, n-type and p-type impurities are ion-implanted at a high dose of about 10 ¹⁵ cm ^{-2 using the} gate electrode 106 as a mask. As a result, n-channel type (91b) and p
Source of channel type (not shown) MOS transistor
Forming a drain region;

On the other hand, the lateral NPN and PNP are formed by ion-implanting n-type and p-type impurities into the other region (91a).
(Not shown) Create transistor emitter and collector regions. After depositing the oxide film 118 on the entire surface of the substrate again, the contact holes are opened and the electrodes 121 to 126 are formed.
To form. Logic and analog circuits can be formed by combining these MOS transistors and bipolar transistors. (Embodiment 9) FIG. 11 is a schematic sectional view of a power semiconductor device including a control circuit according to a ninth embodiment. Since this embodiment is basically the same as the eighth embodiment, the same parts are designated by the same reference numerals and detailed description thereof will be omitted.

The present embodiment differs from the eighth embodiment in that the polycrystalline silicon deposited as the gate electrode 94 of the vertical power device 90 is made of the back gate 1 of the MOSTFT 91b '.
It is used as 25. This allows MOSTFT
The process can be simplified because it is not necessary to separately deposit a polycrystalline silicon layer to be the gate of 91b '. (Embodiment 10) FIG. 12 is a schematic sectional view of a power semiconductor device having a control circuit according to the tenth embodiment.
This embodiment is basically the same as the eighth embodiment, but the configuration of the control circuit portion is different. The same parts as those in the eighth embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

The control circuit of this embodiment includes a vertical bipolar transistor 91c similar to that of the first embodiment and a high breakdown voltage MOSFET 92d similar to that of the fourth embodiment.
That is, the vertical bipolar transistor 91c is configured by stacking a collector 131, a base 132, and an emitter 133 made of polycrystalline silicon in multiple layers. MOS
The TFT is a source region 134 made of polycrystalline silicon,
The channel forming region 135, the high breakdown voltage imparting region 136, and the drain region 137 are formed in a plane.

This embodiment is different from the eighth embodiment in that at the same time as the deposition of the emitter layer 131 of the vertical bipolar transistor 91c made of multilayer polycrystalline silicon, the MOS is formed.
The active layers 134 to 137 of the TFT 91d are formed, and at the same time as the deposition of the collector layer 133, a polycrystalline silicon layer to be the gate electrode 94 of the MOSTFT 91d is deposited. Since 91c is a vertical bipolar transistor, the characteristics of the bipolar transistor can be improved by reducing the thickness of the base layer, and it is not necessary to separately deposit a polycrystalline silicon layer to be the gate electrode 94 of the MOSTFT 91d. Therefore, the process can be simplified.

Although five examples of incorporating the control circuit made of polycrystalline silicon into the vertical power semiconductor element have been described above, the present invention is not limited to the above-mentioned embodiments, and these examples can be used in combination. Is.

[0097]

The present invention does not use expensive separation technology,
Since the control circuit is formed of inexpensive polycrystalline silicon, it becomes possible to provide an inexpensive smart power device. In addition, since the control circuit made of polycrystalline silicon has been improved in performance, this power device is capable of highly accurate analog control.

[Brief description of drawings]

FIG. 1 is a sectional view of a bipolar transistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a bipolar transistor according to a second embodiment of the present invention.

FIG. 3 is a sectional view of a BiCMOS transistor according to a third embodiment of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor device for explaining a modification example in which the polycrystalline semiconductor layer of the present invention is partially monocrystallized.

FIG. 5 is a schematic plan view of a lateral bipolar transistor according to a fourth embodiment of the present invention.

6 is a sectional view taken along the line AA of FIG.

FIG. 7 is a sectional view of a high voltage MOS transistor according to a fifth embodiment of the present invention.

FIG. 8 is a sectional view of a power device having a control circuit according to a sixth embodiment of the present invention.

FIG. 9 is a sectional view of a power device having a control circuit according to a seventh embodiment of the present invention.

FIG. 10 is a sectional view of a power device having a control circuit according to an eighth embodiment of the present invention.

FIG. 11 is a sectional view of a power device having a control circuit according to a ninth embodiment of the present invention.

FIG. 12 is a sectional view of a power device having a control circuit according to a tenth embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Silicon oxide layer 3 ... N-type polycrystalline silicon layer (n-type collector region) 4 ... Element isolation insulating film 5 ... Silicon oxide layer 6 ... P-type polycrystalline silicon germanium layer (p-type base region) 7 Silicon oxide film 8 N-type polycrystalline silicon layer (n-type emitter region) 9 Interlayer insulating film 10 Base electrode 11 Emitter electrode 12 Collector electrode 21 Silicon substrate 22 Silicon oxide layer 23 Element isolation insulating film 24 ... Collector region 24a ... N ^- type collector region 24b ... N type collector region 25 ... Gate oxide film 26 ... Gate electrode 27Sn ... N type source region 27Dn ... N type drain region 27Sp ... P type source region 27Dp ... P type drain region 28n ... n-type channel region 28p ... p-type channel region 30 ... silicon oxide layer 31 ... p-type polycrystalline silicon germanium layer 32 ... sili Oxide film 33 ... n-type polycrystalline silicon layer 34 ... interlayer insulating film 35 ... base electrode 36 ... emitter electrode 37 ... collector electrode 38S ... source electrode 38D ... drain electrode 39S ... source electrode 39D ... drain electrode 41 ... single crystal silicon substrate 42 ... Insulating layer 43 ... Single crystal silicon layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 27/06 29/165 H01L 29/165 (72) Inventor Keito Kawahisa Yukio Kawasaki, Kanagawa Prefecture Komukai-Toshiba-cho 1-ku, Toshiba Research & Development Center

Claims (15)

[Claims] 1. A base plate having a main surface, a first-conductivity-type first polycrystalline semiconductor layer selectively and insulatively formed on the main surface, and a first polycrystalline semiconductor layer on the first polycrystalline semiconductor layer. Second selectively formed
A conductive type second polycrystalline semiconductor layer, and a first selectively formed on the second polycrystalline semiconductor layer
A conductive type third polycrystalline semiconductor layer, and forms a transistor. 2. The first polycrystalline semiconductor layer is a collector region, the second polycrystalline semiconductor layer is a base region, and the third polycrystalline semiconductor layer is an emitter region. The semiconductor device according to claim 1. 3. The first polycrystalline semiconductor layer is an emitter region, the second polycrystalline semiconductor layer is a base region, and the third polycrystalline semiconductor layer is a collector region. The semiconductor device according to claim 1. 4. The semiconductor device according to claim 2, wherein an energy band gap of the polycrystalline semiconductor layer in the base region is smaller than that in the emitter region. 5. The semiconductor according to claim 1, wherein the first and third polycrystalline semiconductor layers are made of deposited silicon, and the second semiconductor layer is made of deposited silicon germanium. apparatus. 6. A fourth polycrystalline semiconductor layer formed insulatively in a region on the main surface different from a region on the main surface on which the first semiconductor region is formed, A source region selectively formed in the fourth polycrystalline semiconductor layer, and a drain region formed in the fourth polycrystalline semiconductor layer on the same surface as the source region with their ends facing each other. A channel forming region sandwiched between the source region and the drain region, and a fifth insulating region formed on the surface of the channel forming region.
2. The semiconductor device according to claim 1, further comprising: a gate electrode formed of the polycrystalline semiconductor layer according to claim 1. 7. A base plate having a main surface, and a thickness of 150 nm or less formed on the main surface insulatively.
a polycrystalline silicon layer having a thickness of nm or more, first and second regions of the first conductivity type which are laterally arranged in the polycrystalline silicon layer so that ends thereof face each other, and the first and the second regions. A second conductivity type third formed between the two regions and connected to the first and second regions.
A semiconductor device comprising: a region, and forming a transistor. 8. A base plate made of polycrystalline silicon, a first polycrystalline silicon layer having a thickness of 150 nm or less formed selectively and insulatively on a main surface of the base plate, and the first polycrystalline silicon. A gate electrode formed of a second polycrystalline silicon layer selectively and insulatingly formed on the layer, and a predetermined conductivity formed on the first polycrystalline silicon layer on one side surface of the gate electrode. Type first diffusion layer, and a first diffusion layer formed on the first polycrystalline silicon layer on a side surface of the gate electrode opposite to the side surface, and having a resistance value higher than that of the first diffusion layer. Second layer of the same conductivity type as the layer
2. A semiconductor device, comprising: 9. A first-conductivity-type first semiconductor layer made of a single crystal, a second-conductivity-type well selectively formed on a surface of the first semiconductor layer, and a second-conductivity-type well. A second semiconductor layer of the first conductivity type selectively formed on the surface of the well, and so as to partially and insulatingly oppose the first semiconductor layer, the well, and the second semiconductor layer. The first polycrystalline semiconductor layer formed in the first polycrystalline semiconductor layer and the first polycrystalline semiconductor layer in a region different from the surface region of the first semiconductor layer in which the first polycrystalline semiconductor layer is formed. A second polycrystalline semiconductor layer formed to have a different thickness, the second polycrystalline semiconductor layer is divided into a plurality of electrically different sections, and the plurality of sections are configured of at least one transistor. A semiconductor device characterized by being an element. 10. The film thickness of the second polycrystalline semiconductor layer is 1
The semiconductor device according to claim 9, wherein the thickness is 50 nm or less and 5 nm or more. 11. The plurality of areas comprises an emitter region and
10. The semiconductor device according to claim 9, comprising at least one bipolar transistor including a region corresponding to a base region adjacent to the base region and a region corresponding to the collector region adjacent to the base region. 12. At least one MOS transistor is formed in each of the plurality of areas, and each of the plurality of areas includes a source region, a drain region, and a region corresponding to a channel forming region interposed between these regions. 10. The semiconductor device according to claim 9, further comprising a gate electrode, which is insulated and attached to the channel formation region. 13. A step of preparing a base plate whose surface is insulated, a step of depositing a first amorphous semiconductor layer on the surface of the base plate, and a heat treatment of the first amorphous semiconductor layer. Forming a first conductive type first polycrystalline semiconductor layer, terminating the surface of the first semiconductor layer with hydrogen, and forming a second conductive layer on the surface of the first polycrystalline semiconductor layer. Depositing a conductive second polycrystalline semiconductor layer, terminating the surface of the second semiconductor layer with hydrogen, and depositing a first conductive first layer on the surface of the second polycrystalline semiconductor layer. 3. A method for manufacturing a semiconductor device, comprising: depositing the amorphous semiconductor layer of 3. 14. A step of preparing a base plate whose surface is insulated, a step of depositing a first conductivity type polycrystalline silicon layer on the surface of the base plate to a film thickness of 150 nm or less and 5 nm or more, A step of selectively and insulatingly forming a conductive layer on a conductive type polycrystalline silicon layer; and a second conductive type on the polycrystalline silicon layer on one side of the conductive layer using the conductive layer as a mask Selectively diffusing the impurities of to form the first region of the second conductivity type, and forming the conductive layer in the first region and on the polycrystalline silicon layer on the other side of the conductive layer. Selective first as mask
A conductivity type impurity is diffused to form a first conductivity type second region included in the first region and a third region facing the first region with the conductive layer interposed therebetween. A method of manufacturing a semiconductor device, comprising: 15. A step of selectively forming a second-conductivity-type base layer on the surface of the first-conductivity-type first semiconductor layer made of single crystal, and a step of forming a second-conductivity-type base layer on the surface of the second-conductivity-type base layer. Selectively forming a second semiconductor layer of one conductivity type, and at least partially and insulatively facing the first semiconductor layer, the base layer, and the second semiconductor layer. Forming a first polycrystalline semiconductor layer, and insulating the second polycrystalline semiconductor layer with a different thickness in a region different from the first polycrystalline semiconductor layer on the surface of the first semiconductor layer. And a step of dividing the second polycrystalline semiconductor layer into a plurality of electrically different areas to form a transistor, and a method of manufacturing a semiconductor device. .