JPH02207534A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the area of a semiconductor element and realize the high speed operation and the high density integration of a bipolar transistor by installing an outer collector region and an outer base region to lead out an active collector region and an active base region on a first insulating film and a second insulating film, respectively. CONSTITUTION:On a p-type Si substrate 10, an SiO2 film 11 is formed; a polycrystalline silicon film is stuck on the SiO2 film 11; after this film is processed in a desired form, it is recrystallized, thereby forming a single crystal silicon film 12; antimony of high concentration is thermally diffused into the film 12; an SiO2 film 13 and an aperture part 14 are formed on the film 12; by epitaxial growth art, a low concentration n-type (n<->)single crystal Si film 15 and a low concentration n-type (n<->) single crystal silicon film 16 are formed on the aperture part 14 and the SiO<2> film 3, respectively; then the film are processed in desired forms; high concentration boron is selectively ion-implanted in the film 16, and a high concentration p-type (p<+>) polycrystalline Si film 17 is formed by heat treatment; comparatively low concentration B ion is implanted in the film 15, and a p-type active base layer 18 is formed by heat treatment.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a bipolar transistor device suitable for high performance and high integration. [Prior Art] In bipolar transistor devices with very small dimensions, transistors whose minimum dimensions are on the order of submicrons, the parasitic capacitance between the base and collector and the parasitic capacitance between the collector and substrate are the most important performance parameters, and the device In order to speed up the process, it is necessary to reduce these parasitic capacitances. Conventional transistors of this type manufactured according to the prior art are disclosed in Japanese Patent Publication No. 62-5349, especially No. 1B.
As shown in the figure and FIG. 21, an external base electrode made of polycrystalline silicon is formed so as to laterally surround the emitter, the active base, and a portion of the collector region immediately below the emitter and the active base, which are formed in a stacked manner. ing. An insulator is provided between the external base electrode and the emitter, the emitter-base junction, the base-collector junction, and the collector region to separate the external base electrode from the emitter, emitter-base junction, base-collector junction, and collector region. Further, the collector region provided below the active base region surrounds the bottom and side surfaces of one of the base electrodes with an insulator interposed therebetween, and is drawn out to the main surface of the semiconductor substrate. [Problems to be Solved by the Invention] In the above conventional technology, the external base electrode electrically connected to the side surface of the active base region is drawn out to the main surface of the semiconductor substrate. ) can be miniaturized. Therefore, there is a feature that the junction capacitance between the base and the collector can be sufficiently reduced. However, the collector region provided below (inside) the active base region surrounds the bottom and side surfaces of one of the base electrodes via an insulator, and is drawn out to the main surface of the semiconductor substrate. Therefore, there is a problem in that it is difficult to miniaturize the collector region. Therefore, in the above conventional technology, the junction capacitance between the collector and the substrate is large;
Furthermore, between adjacent transistors (collector-collector)
A necessary distance must be provided for isolation, which increases the area of the entire 7, which has the disadvantage that high speed and high integration of bipolar transistors cannot be achieved sufficiently. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a bipolar transistor device that can eliminate the above-mentioned drawbacks and reduce the overall semiconductor element area. [Means for Solving the Problems] The above object includes a semiconductor substrate, a first region made of a first conductivity type single crystal semiconductor layer provided on the surface of the substrate, and an opening on the first region. a first insulating film provided as a first insulating film; a second region made of a first conductivity type single crystal semiconductor layer provided over the opening; a third region made of a second conductivity type polycrystalline semiconductor layer extending over the film; a fourth region of the second conductivity type provided within the second region; and within the fourth region. and a fifth region of the first conductivity type provided in the area, the first area being an external collector area, the second area being an active collector area,
The third area is an external base area. This is achieved by forming a bipolar transistor device in which the fourth region is an active base region and the fifth region is an emitter region. The above object also includes a first conductive type semiconductor substrate, a first insulating film provided with an opening on the surface of the substrate, and a second conductive type single crystal semiconductor provided on the opening. a first region consisting of a layer; and a first region connected to an end surface of the first region;
a second region made of a second conductivity type polycrystalline semiconductor layer extending over the insulating film; and a second region having an opening above the first region and provided above the first and second regions. a second insulating film, a third region made of a second R type single crystal semiconductor layer provided over the opening of the second insulating film, and a second insulating film connected to an end surface of the third region; A first plate extending over the membrane.
a fourth region made of a conductivity type polycrystalline semiconductor layer; a fifth region of the first conductivity type provided within the third region; and a sixth region of the second conductivity type provided within the fifth region. and
A bipolar transistor in which the first and second regions are external collector regions, the third region is an active collector region, the fourth region is an external base region, the fifth region is an active base region, and the sixth region is an emitter region. This can also be achieved by using a device. [Function] The bipolar transistor device is provided with an external collector region and an external base region extending over the first insulating film and the second insulating film, respectively, for drawing out the active collector region and the active base region to the outside. There is. As a result, the junction capacitance between the base and the collector can be sufficiently reduced as in the conventional device, and in the conventional device, the base electrode is provided in the semiconductor substrate so as to surround the bottom and side surfaces with an insulator interposed therebetween, and the base electrode is provided on the substrate surface. The high-concentration collector region that had been drawn out becomes almost unnecessary. Therefore, compared to conventional devices, the junction capacitance between the collector and the substrate can be significantly reduced, and the isolation interval between adjacent transistors (collector-to-collector) can also be significantly reduced.
It is possible to achieve higher speed and higher integration of transistor devices. [Example] Hereinafter, an example of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view showing a manufacturing method in which the present invention is applied to an npn type bipolar transistor in the order of manufacturing steps. First, a p-type Si substrate 10 is prepared, and a 5iOz film]1 is formed to a thickness of 5,000 layers on its surface by a thermal oxidation method6.
Next, a film with a thickness of 5000 mm is deposited on the SiO2 film 11 by CVD method.
Deposit human polycrystalline silicon film (polys i film),
After processing the polysi film into a desired shape, the single crystal silicon film 12 is formed by recrystallizing the polysi film with a cw-Ar laser while keeping the substrate 10 at a temperature of 500°C. Next, antimony (sb) is thermally diffused into the single crystal 5i12 to a high concentration. This results in Figure I
The configuration shown in A is obtained. Next, for example, by selective oxidation technology, as shown in FIG. 1B,
A SiO2 film 13 and an opening 1 are formed on the single crystal Si film 12.
form 4. Next, by an epitaxial growth technique using dichlorosilane (S i Cfl 2H2) gas, as shown in FIG. On the 5iOz film 13, there is a low concentration of n.
After forming the (n-) type polycrystalline Si film 16, it is processed into a desired shape. Next, using photoresist as a mask material, high concentration boron (B) ions are selectively implanted into the film 16, and heat treatment is performed to form a high concentration p
A p-type active base layer 18 is formed by forming a (P+) type polycrystalline Si film 17, and then implanting B ions at a relatively low concentration into the film 15 and subjecting it to heat treatment. Next, a SiOx layer 19 is deposited on the entire surface by CVD, and a portion of the base layer 18 is opened. Next, first, a polycrystalline Si film to which no impurities were added was deposited to a thickness of 20 μm using the CVD method, and then a high concentration of As ions was implanted into the Si film and heat treated.
As shown in FIG. 1E, an n+ emitter layer 22 is formed within the heavily doped n-type (n+) polycrystalline Si film 21 and the base layer 18. Next, a two-layer film 23 of SiO2 film and PSG film is deposited on the entire surface by CVD method, and then a first layer is formed using photoetching technology.
As shown in FIG. . Next, after depositing a conductive film such as AΩSi by sputtering method,
A collector electrode wiring layer 25, a collector electrode wiring layer 26, and a base electrode wiring layer 27 are formed by processing into a desired shape using a photoetching technique. The above is an example of the method for manufacturing the npn bipolar transistor of the present invention. In the bipolar transistor of the present invention obtained through the above-described steps, the n+3195 layer 12 is provided on the Si2 film 11, and there is no pn junction with the Si substrate 10. Further, the active base layer 18 is drawn out onto the Si2 film 13 by the p-polycrystalline Si film 17, and is connected to the base electrode wiring layer 26 at this position. With such a configuration and arrangement, it is possible to eliminate the need for a high concentration collector region provided in the substrate in the conventional device. Therefore, the junction capacitance between the n+3195 layer 12 and the substrate 10 can be significantly reduced. In addition, since the region for insulating and separating transistors is not a pn junction but a 5iOz film, the spacing can be significantly reduced, while the base-collector junction capacitance can be reduced as before, allowing high-speed bipolar transistors to be It is possible to achieve high integration and high integration. Next, another embodiment of the present invention will be described using FIG. FIG. 2 shows a cross-sectional view of a vertical structure when the present invention is applied to an npn bipolar transistor. The details of the manufacturing method will be omitted, and the differences from the first embodiment will be explained. First, a P-type Si substrate 20 is prepared, and a highly doped p-type channel stopper layer 23 is formed in a desired region within the substrate 20. Next, an opening 2 is formed on the Si substrate 20 by selective oxidation.
A 5iOz film 24 is formed in areas other than 0A. Next, S
By epitaxial growth technology using iCQ xHz gas, a single crystal Si film 21,
A polycrystalline Si film 22 is formed on each of the 5iOz films 24. Next, a high concentration of sb is added to these films 21 and 22.
By thermally diffusing them, they are made into an n0 film 21 and an n0 polycrystalline Si film 22, respectively. The subsequent steps are carried out in substantially the same manner as in the first embodiment, and the npn bipolar transistor shown in FIG. 2 is completed. In the bipolar transistor of the present invention obtained in this way, the n+Si film 21 (high concentration collector region)
Since a pn junction is formed between the and p-type Si substrate 20, the junction capacitance between the collector and the substrate increases compared to the first embodiment, but the junction area is small and is significantly larger than that of the conventional device. Can be reduced. On the other hand, this embodiment can be carried out using only one selective epitaxial technique without using a laser recrystallization technique, which has the advantage that the process is simple and the crystallinity of the bipolar active region is good. Next, another embodiment of the present invention will be described using FIG. FIG. 3 shows a cross-sectional view of a vertical structure when the present invention is applied to an npn bipolar transistor. Although a detailed explanation of the manufacturing method will be omitted, this embodiment is a modification of the first embodiment, in which the distance between the n+ emitter 30 and the p+ external base 31 is made closer in a self-aligning manner. . This allows the base resistance rbb parasitic to the base to be reduced, which has the effect of increasing the speed of the layer. Although all of the above three embodiments have been explained using an npn bipolar transistor as an example, the present invention may also be applied to a pnp bipolar transistor, or to a composite semiconductor device formed by a hybrid L5 with a CMOS transistor. It can be effective. Moreover, various changes in shape and detail or formation by various manufacturing methods can be made without departing from the spirit and scope of the invention. [Effects of the Invention] According to the present invention, the external collector region and the external base region necessary for drawing out the active collector region and the active base region to the outside are respectively provided on the insulating film. The highly doped collector region provided within the semiconductor substrate, which was necessary to bring out the lightly doped collector region provided below the active base region to the surface of the semiconductor substrate, can be almost eliminated. Moreover, for this reason, the isolation width between adjacent transistors can also be made finer. Therefore, the junction capacitance between the collector and the substrate can be significantly reduced, and the size of the entire transistor device can also be sufficiently reduced, which has the effect of increasing the speed and increasing the integration of the bipolar transistor device. 5,

[Brief explanation of the drawing]

FIGS. 1A to 1F are vertical structural cross-sectional views showing a method for manufacturing an npn bipolar transistor according to an embodiment of the present invention in the order of manufacturing steps, and FIGS. 2 and 3 are cross-sectional views of an npn bipolar transistor according to another embodiment of the present invention. It is a longitudinal structure sectional view. 12-n+si film, 12-n+ emitter layer, 15...
・n'-8i film (low concentration collector layer), 17...P+
Polycrystalline Si film (external base layer), 18...p-type base layer (active base layer).

Claims (1)

[Claims] 1. A semiconductor substrate, a first region comprising a first conductivity type single crystal semiconductor layer provided on the surface of the substrate, and an opening provided on the first region. a first insulating film, a second region made of a first conductivity type single crystal semiconductor layer provided over the opening, and a second region connected to an end surface of the second region and extending to the first insulating film. a third region made of a polycrystalline semiconductor layer of a second conductivity type provided in the second region; a fourth region of the second conductivity type provided in the second region; and a first conductivity region provided in the fourth region. A semiconductor device comprising: a fifth region of a mold; and a fifth region of a mold. 2. A first conductive type semiconductor substrate comprising a first conductive type semiconductor substrate, a first insulating film provided with an opening on the surface of the base body, and a second conductive type single crystal semiconductor layer provided on the opening. 1 area and
A second conductive type polycrystalline semiconductor layer connected to the end face of the first region and extending over the first insulating film.
a second insulating film provided on the first and second regions with an opening on the first region, and a second conductive film provided on the opening of the second insulating film. a third region made of a type single crystal semiconductor layer; and a fourth region made of a first conductivity type polycrystalline semiconductor layer connected to an end surface of the third region and extending over the second insulating film. and a fifth region of the first conductivity type provided within the third region, and a sixth region of the second conductivity type provided within the fifth region. . 4. The first region is an external collector region, the second region is an active collector region, the third region is an external base region, the fourth region is an active base region, and the fifth region is an emitter region; 2. The semiconductor device according to claim 1, wherein the semiconductor device is configured as a bipolar transistor device. 5. The first and second regions are external collector regions, the third region is an active collector region, the fourth region is an external base region, the fifth region is an active base region, and the sixth region is an active collector region. 3. The semiconductor device according to claim 2, wherein the semiconductor device has an emitter region and constitutes a bipolar transistor device.