JPH09102604A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the ON resistance of a transistor by forming a hollow in a semiconductor substrate, forming a conductive layer on the bottom surface of the hollow, and shortening the path of current. SOLUTION: A hollow 7 is formed on the back of a P-type silicon substrate 1. An N-type buried layer 6 is formed in a region which reaches the main surface from the bottom surface of the hollow 7 in the P-type silicon substrate 1. In an N-type epitaxial layer 2, a vertical type MOSFET forming region 4 and a control element forming region 5 are formed. A P-type isolation region 3 is formed for isolating the control element forming region 5 from the vertical type MOSFET forming region 4. Since the hollow 7 is formed in the P-type silicon substrate 1 and a drain electrode 8 is formed on the bottom surface of the hollow 7, the path of a current flowing in the P-type silicon substrate is shortened, and the ON resistance of the vertical type MOSFET can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of transistors equipped with power devices.

[0002]

2. Description of the Related Art In a semiconductor device having a plurality of transistors, at least one of which has an electrode formed on the back surface of a semiconductor substrate has a method of element isolation of a transistor, which is disclosed in Japanese Patent Laid-Open No. 50-39082. It is described in. According to this publication, the N-type epitaxial layer 5 and the N + semiconductor 1 in which the NPN transistor and the PNP transistor are formed.
The P-semiconductor layer 2 is interposed between the P and semiconductor layers to isolate these transistors from each other.

[0003]

In the above publication, it is necessary to form the P-semiconductor layer 2 on the N + semiconductor 1 for element isolation, and the N + burying layer 3 formed in the P- burying layer 2 is required. And N + semiconductor 1 are used as the collector region of the NPN transistor, the current flow path becomes long and NP
The ON resistance of the N-transistor increases.

[0004]

According to the present invention, there is provided a first conductivity type semiconductor substrate having a first main surface in which a recess is formed and a second main surface opposed to the first main surface, and a recess. A first impurity layer of a second conductivity type reaching the second main surface from the bottom surface, a first conductive layer formed on the bottom surface of the recess and electrically connected to the first impurity layer, In order to electrically separate the conductive type semiconductor substrate and the first conductive layer from the peripheral edge of the bottom surface of the recess,
A semiconductor layer that is formed on the entire main surface of the second main surface and has a third main surface that is formed on the entire second main surface and that opposes the second main surface. A first semiconductor region of the second conductivity type that reaches from the second main surface to the third main surface including
A second semiconductor region of the first conductivity type that is adjacent to the first semiconductor region and reaches the second main surface from the third main surface, and is adjacent to the second semiconductor region, and from the third main surface A semiconductor layer having a third semiconductor region of a second conductivity type that reaches the second main surface and is separated from the first semiconductor region by the second semiconductor region; and a third semiconductor layer in the first semiconductor region. First impurity region of the first conductivity type formed in the first semiconductor region including the main surface, and formed in the first impurity region including the third main surface in the first impurity region. A second impurity region of the second conductivity type, a second conductive layer formed on the third main surface in the second impurity region, and a first impurity region other than the second impurity region A third conductive layer formed on the third main surface,
Third impurity region of the first conductivity type formed in the third semiconductor region including the third main surface in the third semiconductor region, and the third impurity region including the third main surface in the third impurity region. Second conductivity type fourth impurity region formed in the impurity region, a fourth conductive layer formed on the third main surface in the fourth impurity region, and a fourth impurity region And a fifth conductive layer formed on the third main surface in the third impurity region excluding the third impurity region and a third main surface in the third semiconductor layer excluding the third impurity region. A sixth conductive layer and a second conductive type second impurity layer formed in the semiconductor substrate including the second main surface in the third semiconductor region.

[0005]

1 is a sectional view of a semiconductor device according to a first embodiment of the present invention. The first embodiment has a vertical MOS transistor having a drain electrode formed on the back surface and a bipolar transistor. The first embodiment will be described below with reference to the drawings.

A depression 7 is formed on the back surface of the P-type silicon substrate 1 having a concentration of about 1015 / cm3. Concentration 101 in the region reaching the main surface from the bottom surface of the depression 7 in the P-type silicon substrate 1.
An N-type buried layer 6 of about 9 / cm3 is formed. An N-type epitaxial layer 2 having a concentration of about 1015 / cm3 is formed on the main surface of the P-type silicon substrate 1. A vertical MOSFET formation region 4 and a control element formation region 5 are formed in the N-type epitaxial layer 2. Vertical MOSFE
In order to separate the control element formation region 5 from the T formation region 4, a concentration of about 1018 / cm3 is applied to a region from the main surface of the N type epitaxial layer 2 in the N type epitaxial layer 2 to the main surface of the P type silicon substrate 1. P-type isolation region 3 is formed. The concentration of 1018 / cm3 in the region facing the main surface of the N-type epitaxial layer 2 in the vertical MOSFET formation region 4.
P-type base region 9 and a concentration of 1 in P-type base region 9
The N-type source region 10 of about 020 / cm 3 is formed. A gate region 12 is formed on the P-type base region 9 with a gate insulating film 11 interposed therebetween. The gate region 12 is a vertical MO
It is connected to a gate electrode (not shown) at the outer peripheral portion of the SFET formation region 4. The N-type source region 10 and the P-type base region 9 are connected to the source electrode 13 formed on the entire main surface of the vertical MOSFET formation region 4. The gate electrode 12 is covered with the insulating film 14 and separated from the source electrode 13.

On the other hand, the control element forming region 5 has a bipolar transistor formed therein. In order to reduce the collector resistance of the bipolar transistor in a region of the P-type silicon substrate 1 facing the main surface of the P-type silicon substrate 1,
The N-type buried layer 24 having a concentration of about 1019 / cm3 is formed. A P-type base region 25 having a concentration of about 1018 / cm3 and an N-type emitter region 26 having a concentration of about 1020 / cm3 are formed in a region facing the main surface in the control element formation region 5. An emitter electrode 27 is formed on the N-type emitter region 26, and a base electrode 28 is formed on the base region 25. Further, collector electrode 29 is formed, and a high-concentration N-type diffusion layer is formed near the main surface of N-type epitaxial layer 2 below the collector electrode. N
A drain electrode 15 is formed below the mold burying layer 6, and a P-type silicon substrate 1 is separated from the drain electrode 15, so a back surface insulating film is formed between them.

In the above structure, the depression 7 has the P-type silicon substrate 1
And the drain electrode 8 is formed on the bottom surface of the recess 7, the path of the current flowing through the P-type silicon substrate is shortened, and the on-resistance of the vertical MOSFET is reduced.

In the above-described structure, the backside electrode forming type vertical MOSFET has been described as an embodiment. However, the above effects can be obtained if the backside electrode forming type transistor is used. For example, a backside collector having a collector electrode formed on the backside. It may be an electrode formation type bipolar transistor. In this case, a base and an emitter are formed in the vertical MOSFET formation region 4 of FIG. 1 and the drain electrode 15 is used as a collector electrode.

Next, the manufacturing method of the first embodiment will be described.

The N-type buried layer 6 and the N-type buried layer 24 are simultaneously formed on the main surface of the P-type silicon substrate 1 having the (100) plane orientation by diffusion. Next, the N-type epitaxial layer 2 is formed on the entire surface of the P-type silicon substrate 1 by a normal CVD method. After that, a P-type isolation region 3 is formed in the N-type epitaxial layer 2 by a diffusion method. Next, vertical MO
A P-type base region 9, an N-type source region 10, a gate region 12 and a source electrode 13 are formed in the SFET formation region 4.
Further, a bipolar transistor is formed in the control element formation region. Next, on the entire surface of the N-type epitaxial layer 2,
A protective film 21 of Si3N4 for protecting the electrodes of the control circuit and the source electrode 13 is formed by the CVD method. Next, a recess 7 is formed below the vertical MOSFET 4 on the back surface side of the P-type silicon substrate 1 with an alkaline etchant. Next, a back surface insulating film 8 of, eg, SiO 2 of about 5000 Å is formed on the entire back surface by a CVD method,
The N-type buried layer 6 is exposed again by a normal photolithography and etching process. Finally, a drain electrode 15 is formed by forming a conductive layer on the entire back surface by an evaporation method and patterning the structure, and the structure of the first embodiment is obtained.

In the above process, the buried layer 6 and the buried layer 24 can be simultaneously formed by a single diffusion process.

FIG. 2 is a sectional view of a semiconductor device according to the second embodiment of the present invention. The second embodiment has a vertical MOSFET having a drain electrode formed on the surface and a bipolar transistor.

In the second embodiment, a drain electrode 17 is newly formed on the main surface of the N-type drain diffusion layer 16 and the N-type epitaxial layer 2 as compared with the first embodiment. The second embodiment is the same as the first embodiment in that the conductive layer is formed on the N-type buried layer 6, but in the first embodiment, the conductive layer is a vertical MOSFET. The drain electrode 15 functions as the drain electrode of the buried layer 6 in the second embodiment.
, Which serves as a backing wiring for reducing the resistance component of the wiring. Since the respective roles are different, the conductive layer will be referred to as a back wiring metal 18.

The structure will be described in detail.
In the vertical MOSFET formation region 4 for taking out the drain electrode 16 from the main surface of the type silicon substrate 1, and N
An N-type drain diffusion layer 16 is formed in a region reaching the N-type buried layer 6 from the main surface of the N-type epitaxial layer 2 in the type epitaxial layer 2. A drain electrode 17 is formed on the main surface of the N-type epitaxial layer 2 on the N-type drain diffusion layer 16.

The vertical MOSFET of the second embodiment is
A current flows through the buried layer 6 and the N-type drain diffusion layer 16. Therefore, by reducing the resistance component of the buried layer 6, the on-resistance of the vertical MOSFET is reduced.

FIG. 3 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention, in which portions corresponding to those in FIG.

In the third embodiment, the back surface electrode forming type vertical MOSFET forming region 4 in the first embodiment is two.
The sidewalls of the recesses 7 formed under these vertical MOSFET formation regions are tapered so that the silicon base between the recesses has a ridge 19. Accordingly, in the third embodiment, the vertical MOSFET
Since the formation regions 4 are closely adjacent to each other, the integration degree of IC is increased.

FIG. 4, FIG. 5, FIG. 6, FIG. 7, FIG. 8, and FIG. 9 are process sectional views of a semiconductor device according to a third embodiment of the present invention. The third embodiment will be described below.

A SiO2 film 20 of about 3000 angstrom is formed by thermal oxidation on the main surface of the P-type silicon substrate 1 having a (100) plane orientation, and an opening is formed by a usual photolithography and etching process. The N-type buried layer 6 and the N-type buried layer 24 having a surface concentration of about 1018 / cm3 are formed by ion implantation using Sb as an ion species and thermal diffusion through the opening. (FIG. 4) Next, the SiO 2 film 20 is removed, and an N-type epitaxial layer 2 with ρ = 1Ωcm and a thickness of about 10 μm is formed on the main surface of the P-type silicon substrate 1. After that, a P-type isolation region 3 is formed in the N-type epitaxial layer 2 by a diffusion method to form a vertical MOSF.
A plurality of elements of ET4 are formed, and the source electrode 13 is formed. Next, a vertical MOSF is formed on the entire surface of the N-type epitaxial layer 2.
1.5μ for protecting the element such as ET4 and the source electrode 13
A m3 Si3N4 protective film 21 is formed by a CVD method. (FIG. 5) After that, a Si3N4 film 22 of about 2000 angstrom is formed on the back surface side of the P-type silicon substrate 1 as a mask of an alkaline etchant by a CVD method, and a vertical MO
A portion located below the SFET 4 is opened by a normal photolithography and etching process. Two adjacent vertical MOs
The remaining width W of the Si3N4 film 22 remaining between the SFETs 4 is set within the range of the following equation.

W <2rD r = a / d where D is the thickness of the P-type silicon substrate, d is the etching rate in the (100) direction, and a is the underetching rate in the direction perpendicular to the (100) direction. (FIG. 6) Next, using the Si3N4 film 22 as a mask, etching is performed with an alkaline etchant to form the depression 7. (FIG. 7) When the etching depth in the (100) direction reaches W / 2r, the P-type silicon substrate 1 sandwiched between the two openings 23.
The portion under the mask of 1 is under-etched at the etching rate a, and is separated from the Si3N4 film 22 between the openings 23 to form a ridge 19. The tip of the ridge 19 is thereafter etched in the (100) direction at an etching rate of d.

Thereafter, etching is continued until the N-type buried layer 6 is exposed, and the two exposed N
The P-type silicon substrate 1 is sandwiched between the mold burying layers 6.
A ridge 19 having a height that does not reach the back plane of the. (FIG. 8) Next, a back surface insulating film 8 of, eg, SiO 2 of about 5000 angstrom is formed on the entire back surface by a CVD method, and the N-type buried layer 6 is exposed again by a normal photolithography and etching process. Finally, a drain electrode 15 is formed by forming a conductive layer on the entire back surface by vapor deposition and patterning.
And the structure of the third embodiment is obtained. (FIG. 9)

[0023]

According to the present invention, since the depression is formed in the semiconductor substrate and the conductive layer is formed on the bottom of the depression, the on-resistance of the transistor is reduced.

Further, in the present invention, since the semiconductor substrate is used as the isolation region of the plurality of transistors, it is necessary to form a new isolation layer between the semiconductor substrate and the first semiconductor layer in order to isolate the plurality of transistors. Absent.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment.

FIG. 2 is a sectional view of a semiconductor device according to a second embodiment.

FIG. 3 is a sectional view of a semiconductor device according to a third embodiment.

FIG. 4 is a process sectional view of a semiconductor device according to a third embodiment.

FIG. 5 is a process sectional view of a semiconductor device according to a third embodiment.

FIG. 6 is a process sectional view of a semiconductor device according to a third embodiment.

FIG. 7 is a process sectional view of a semiconductor device according to a third embodiment.

FIG. 8 is a process sectional view of a semiconductor device according to a third embodiment.

FIG. 9 is a process sectional view of a semiconductor device according to a third embodiment.

[Explanation of symbols]

 1 is a P-type silicon substrate 2 is an N epitaxial layer 3 is a P-type isolation region 4 is a vertical MOSFET formation region 5 is a control element formation region 6 and 24 is an N-type buried layer 7 is a recess 8 is a back surface insulating film 9 is a P-type Base region 10 is N-type source region 11 is gate insulating film 12 is gate region 13 is source electrode 14 is insulating film 15 is drain electrode 16 is drain electrode 16 is N-type drain diffusion layer 17 is drain electrode 18 is backside wiring metal 19 is recess 20 SiO2 film 21 is protective film 22 is Si3N4 film 23 is opening 25 is P-type base region 26 is N-type emitter region 27, 33 is emitter electrode 28, 34 is base electrode 29, 35 is collector electrode 30, 31 is P-type The collector region 32 is a P-type emitter region

Claims (2)

[Claims] 1. A first main surface having a recess and the first main surface.
A first conductive type semiconductor substrate having a second main surface facing the main surface, a second conductive type first impurity layer reaching the second main surface from the bottom surface of the recess, and A first conductive layer formed on the bottom surface and electrically connected to the first impurity layer; and a semiconductor substrate of the first conductivity type and the first conductive layer for electrical isolation. From the periphery of the bottom surface of the recess to the first
A semiconductor layer that is formed on the entire main surface of the second main surface and has a third main surface that is formed on the entire second main surface and that opposes the second main surface. A second semiconductor region of the first conductivity type that extends from the second main surface including the impurity layer to the third main surface;
A second semiconductor region of a first conductivity type that is adjacent to the first semiconductor region, reaches the second main surface from the third main surface, and is adjacent to the second semiconductor region; A semiconductor layer having a second conductivity type third semiconductor region reaching from the third major surface to the second major surface and separated from the first semiconductor region by the second semiconductor region; A first impurity region of a first conductivity type formed in the first semiconductor region including the third main surface in the first semiconductor region; and a third impurity region in the first impurity region. A second conductivity type second impurity region formed in the first impurity region including a main surface, and a second conductivity formed on the third main surface in the second impurity region. A layer and the third main surface formed on the third main surface in the first impurity region excluding the second impurity region. A conductive layer, a third impurity region of a first conductivity type formed in the third semiconductor region including the third main surface in the third semiconductor region, and a third impurity region in the third impurity region A fourth impurity region of the second conductivity type formed in the third impurity region including the third main surface, and formed on the third main surface in the fourth impurity region. A fourth conductive layer, a fifth conductive layer formed on a third main surface in the third impurity region excluding the fourth impurity region, and the third impurity region excluded A sixth conductive layer formed on the third main surface in the third semiconductor layer, and a sixth conductive layer formed in the semiconductor substrate including the second main surface in the third semiconductor region. A semiconductor device having a second conductivity type second impurity layer. 2. A fifth impurity region of the second conductivity type, which is formed in the first semiconductor region and reaches the first conductive layer from the third main surface, and the fifth impurity region. The semiconductor device according to claim 1, further comprising a seventh conductive layer formed on the third main surface of the inside.