JPH07115099A - Bipolar semiconductor device and method of manufacturing it - Google Patents

Abstract

PURPOSE:To lead out even a fine emitter with low resistance by decreasing a step at the opening part of the emitter. CONSTITUTION:On an n-type silicon substrate 1, under the surface of which an insulating region 2 is buried and the surface of which is processed to be flat, a collector region 3 and an n-type polycrystalline silicon region layer 4 are foremed, and on which an oxide film 5 and a nitrate film 6 are formed (a). On a collector 3, a resist 7 is provided and ion-implanting B, a p-type polycrystalline silicon layer 8 that functions as base is formed (b). After some ashing of the surface of the resist 7, the nitrate film removed selectively (c), and an oxide film 9 is formed by thermal oxidation, a p-type monocrystalline region 10 is formed and then a base region 11 is formed by ion-implantation (d). The oxide film 5 is removed and an emitter region 13 is formed by the diffusion of impurity from an n-type polycrystalline silicon layer 12(e).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar semiconductor device and a manufacturing method thereof, and more particularly to a bipolar transistor having a fine emitter and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, there has been a strong demand for higher speed bipolar transistors in order to improve the performance of applied equipment. As a means for increasing the speed of a bipolar transistor, a shallow junction of the base has been adopted, along with a miniaturization of the emitter width and a self-aligned base extraction layer forming means. Thus, in a transistor having a miniaturized emitter, it is general that the emitter is formed so as to be self-aligned with the base. This is because by making full use of the self-alignment technique, it is possible to realize an emitter having a width finer than the limit of the photolithography technique.

FIG. 4 is a process sectional view showing a conventional manufacturing method of a bipolar transistor in which a base extraction layer and an emitter are formed by using a self-alignment technique. This is proposed in Japanese Patent Laid-Open No. 304932/1990. It was done. First, an n-type silicon substrate 101 having an insulating region 102 on its surface is prepared, and a first 50 nm-thick first substrate is formed thereon.
A silicon oxide film 103, a silicon nitride film 104 having a thickness of 100 nm, a first polycrystalline silicon layer 105 having a thickness of 400 nm containing p-type impurities, and a second silicon oxide film 106 having a thickness of 300 nm are sequentially stacked. Then, the second silicon oxide film 106 and the first polycrystalline silicon layer 1
05 is selectively removed to form an opening in a region where an emitter is to be formed [FIG. 4 (a)].

Next, the first polycrystalline silicon layer 1 in the opening
The side surface of 05 is oxidized to form a third silicon oxide film 107. Subsequently, the silicon nitride film 104 at the bottom of the opening is removed by etching with a hot phosphoric acid solution, and further side etching is performed to form a first polycrystalline silicon layer. Part of the bottom surface of 105 is exposed. Next, the first silicon oxide film 10 exposed in the opening
3 is etched to form a cavity, and a second polycrystalline silicon layer 108 having a thickness of about 300 nm is grown on the exposed n-type silicon substrate 101 to form the third silicon oxide film 1
07, filling the cavity under the first polycrystalline silicon layer 105. Subsequently, the second polycrystalline silicon layer 108 other than the cavity is removed by the reactive plasma etching method [FIG.
(B)].

Next, a fourth silicon oxide film 109 having a thickness of about 70 nm is formed on the exposed silicon region in the opening by thermal oxidation. By this heat treatment, boron in the p ⁺ -type first polycrystalline silicon layer 105 is diffused into the second polycrystalline silicon layer 108 to make it p-type and diffused into the silicon substrate through this, thereby forming the external base region. 11
Form 0. Next, boron is applied at 20 keV, 2 × 10 ¹³
Ions are implanted under the condition of cm ⁻² to form the internal base region 111 on the surface of the silicon substrate. Next, the portion of the fourth silicon oxide film 109 formed in the opening on the silicon substrate is removed by anisotropic etching to expose the surface of the silicon substrate [FIG. 4 (c)].

Next, a third polycrystalline silicon layer 112 is formed thickly, and this is etched back by reactive plasma etching so that the third polycrystalline silicon layer 1 is formed only in the opening.
12 is left and the surface of the opening is flattened. Next, add 5 arsenic
Ion implantation is performed under the conditions of 0 keV and 1 × 10 ¹⁶ cm ⁻² , and heat treatment is performed to diffuse the arsenic doped in the third polycrystalline silicon layer 112 into the internal base region 111 to form the emitter region 113. The final outer and inner base regions are formed. Next, an aluminum film is formed by a sputtering method and is patterned to form an emitter electrode 114 on the opening [FIG. 4 (d)].

[0007]

In the above-mentioned conventional bipolar transistor, the emitter can be formed in a self-aligned manner and an emitter with a narrow width can be realized. However, in the transistor having the conventional structure, since the emitter is taken out through the thick polycrystalline silicon layer 112, the emitter resistance increases in inverse proportion to the emitter area. For example, when the emitter width becomes about 0.2 μm, the emitter resistance Due to the increase, the characteristic deterioration becomes remarkable.
A method of reducing the emitter resistance is to reduce the step difference in the opening. In the conventional technique, the silicon oxide film 103, 1 is provided outside the polycrystalline silicon layer 105 for extracting the base.
06 and the thickness of the silicon nitride film 104 are added,
There was a limit to lowering the step height of the opening. Further, in the transistor having the conventional structure, the emitter opening is filled with polycrystalline silicon. Therefore, when a transistor with a wide emitter width is to be formed, the emitter opening cannot be filled with polycrystalline silicon, and the transistor is formed. There was the inconvenience of not being able to do it. Furthermore, in the above-mentioned conventional example, since the inside of the cavity is filled with polycrystalline silicon, the process is difficult, and it is difficult to produce with a high yield.

[0008]

In order to solve the above problems, according to the present invention, an insulating region (2) is formed on the surface, and a first conductivity type (n type) is formed in a region surrounded by the insulating region. A semiconductor substrate (1) having a first semiconductor region formed thereon and having a substantially flat surface, and a second substrate formed on the insulating region.
A conductive type (p-type) polycrystalline silicon layer (8);
A second semiconductor region (3) of the first conductivity type formed on the semiconductor region, and a first diffusion layer of the second conductivity type in the periphery and the surface region of the second semiconductor region. (10,
11) is formed, and a second diffusion layer (13) of the first conductivity type is formed in the surface region of the first diffusion layer, and a bipolar semiconductor device is provided.

Further, according to the present invention, an insulating region (2) is formed on the surface and a first semiconductor region of the first conductivity type (n type) is formed in a region surrounded by the insulating region. A first polycrystalline silicon layer (4) on the insulating region by growing silicon on a semiconductor substrate (1) having a substantially flat surface.
And forming a single-crystal second semiconductor region (3) of the first conductivity type on the first semiconductor region, and a second conductivity type of the first polycrystalline silicon layer (4). A step of doping the first polycrystalline silicon layer with a second conductivity type (p type) by doping with impurities, and on the first polycrystalline silicon layer (8) and the second semiconductor region (3) Forming an insulating film (9, 17) having an opening in the central portion of the second semiconductor region covering the second semiconductor region, and doping the second semiconductor region (3) with an impurity of the second conductivity type to form the insulating film (9, 17). Two
Of the second conductivity type (p-type) within the surface region of the semiconductor region of
And forming a diffusion layer (11) of the first diffusion layer, and doping the first diffusion layer with an impurity of the first conduction type through the opening to form a first conductivity type in the surface region of the first diffusion layer. (N type)
And a step of forming the second diffusion layer (13) are provided.

[0010]

Embodiments of the present invention will now be described with reference to the drawings. The npn-type transistor will be described below as an example. FIG. 1 is a sectional view showing an embodiment of a bipolar transistor according to the present invention. As shown in the figure, n is formed on the single crystal silicon region of the n-type silicon substrate 1 having a substantially flat surface, which has an insulating region 2 having a thickness of about 0.2 to 1 μm buried under the surface. Type collector region 3
However, a p-type polycrystalline silicon layer 8 serving as a base extraction layer is arranged on the insulating region 2. A p-type base region 11 is formed in the surface region of the n-type collector region, and an n-type emitter region 13 is formed in the surface region of the p-type base region 11.

On the outer periphery of the n-type collector region 3, the p-type single crystal silicon region 1 is formed so as to surround the n-type emitter region 13.
0 is formed, and the p-type base region 11 is connected to the p-type polycrystalline silicon layer 8 by this region. Also,
The p-type polycrystalline silicon layer 8 and the n-type collector region 3 have an opening above the n-type emitter region 13 and have a film thickness of 50.
A silicon oxide film 9 having a thickness of up to 100 nm is formed, and an n-type polycrystalline silicon layer 12 having a film thickness of 200 nm which is in contact with the n-type emitter region 13 through this opening is formed on the silicon oxide film 9. . The n-type polycrystalline silicon layer 12 is covered with an insulating film 14 and is connected to the emitter electrode 15 through an opening provided in the insulating film 14.

The feature of this structure is that, on the n-type silicon substrate 1 having the insulating region 2, the single crystal silicon layer (3) serving as the active region of the transistor and the polycrystalline silicon layer 8 serving as the base lead are substantially flat. The point is that there is almost no step at the connecting portion between the n-type polycrystalline silicon layer 12 and the emitter region 13 that is formed. Therefore, the n-type polycrystalline silicon layer 12
It is possible to reduce the emitter resistance due to the film thickness of.

2A to 2E are process sectional views for explaining a first embodiment of the method for manufacturing a bipolar semiconductor device according to the present invention. First, the n-type silicon substrate 1
Then, the insulating region 2 is formed so that the surface becomes substantially flat. In this structure, for example, a trench having a depth of 400 nm is provided on both sides of an active region having a width of 600 nm, a silicon oxide film is grown to 400 nm by thermal oxidation, and then a photoresist film is formed to have a flat surface and then etched. It can be formed by performing backing and removing the protrusions of the silicon oxide film. Next, by the epitaxial growth method,
A thickness of 300 nm containing about 1 × 10 ¹⁶ cm ^{−3 of} n-type impurities
Forming a silicon layer. This silicon layer becomes a single crystal n-type collector region 3 on the region where the silicon substrate is exposed, and becomes an n-type polycrystalline silicon layer 4 on the insulating region 2. Next, the surfaces of the collector region 3 and the polycrystalline silicon layer 4 are oxidized to form a silicon oxide film 5 having a film thickness of 30 nm, and a silicon nitride film 6 having a thickness of about 80 nm is grown on the silicon oxide film 5 by a CVD method [Fig. 2 (a)].

Next, a photoresist film 7 covering the n-type collector region 3 is formed, and boron is applied to the n-type polycrystalline silicon layer 4 with an energy of, for example, 50 keV and a dose of 1 × 10.
Ions are implanted under the condition of ¹⁶ cm ^-2 to form the p-type polycrystalline silicon layer 8. The p-type polycrystalline silicon layer 8 serves as a low resistance base lead layer. Here, the photoresist film 7 may be slightly larger or smaller than the size of the single crystal silicon layer (3) [FIG. 2 (b)].

Next, the photoresist film is isotropically etched by about 200 nm by being exposed to oxygen plasma, and the exposed silicon nitride film 6 is etched with a mixed gas of CF ₄ and O ₂ , for example. Isotropic etching of the photoresist film makes it possible to miniaturize the emitter that will be formed in a later step, and keeps the distance between the emitter and the base extraction layer to prevent the breakdown voltage of the emitter-base of the transistor from decreasing. can do. Here, it is also possible not to etch the photoresist film. The silicon nitride film under the photoresist film may be side-etched with a mixed gas of CF ₄ and O ₂ [FIG. 2 (c)].

Next, the photoresist film 7 is removed, the surfaces of the collector region 3 and the polycrystalline silicon layer 4 are oxidized using the silicon nitride film 6 as a mask, and the thickness is 100 to 200 nm.
A silicon oxide film 9 is formed to some extent. At this time, boron in the p-type polycrystalline silicon 8 layer diffuses into the single-crystal silicon layer, and the p-type single-crystal silicon region 10 is formed around the single-crystal layer. However, when the size of the photoresist film is slightly smaller than the size of the single crystal silicon layer, the p-type single crystal silicon region 10 is formed at the time of ion implantation and further diffuses in the oxidation process. Next, the silicon nitride film 6 is removed by a hot phosphoric acid solution, and then boron is removed at 10 keV, 2
Ions are implanted under the condition of × 10 ¹³ cm ^-2 to form the p-type base region 11 [FIG. 2 (d)].

Next, the silicon oxide film 5 on the single crystal silicon layer is removed by wet etching, a polycrystalline silicon layer is grown to a thickness of about 200 nm, and arsenic is added to 50 ke.
Ions are implanted under the condition of V, 1 × 10 ¹⁶ cm ⁻² and patterned by a photoresist film to form the n-type polycrystalline silicon layer 12. Then, heat treatment is performed at 1000 ° C. for 20 seconds to diffuse arsenic to the surface of the single crystal silicon layer,
The n-type emitter region 13 is formed. Next, an insulating film 14 is formed, an opening is formed on the n-type polycrystalline silicon layer 12,
An aluminum film is formed by a sputtering method and is patterned to form an emitter electrode 15 [FIG.
(E)].

As is clear from the above description, in the transistor of this embodiment, the step of the emitter opening is formed by the insulating film 1.
Since it can be formed to a thickness equal to or less than the layer, the distance between the emitter region and the emitter electrode can be formed as thin as the thickness of the n-type polycrystalline silicon layer 12 even if the emitter is miniaturized, and the emitter resistance can be reduced. Further, by performing isotropic etching of the photoresist film or the silicon nitride film, it is possible to form a fine emitter having a resolution equal to or lower than the resolution of the photoresist film, and to provide a fixed distance between the emitter and the base extraction layer. It is possible to prevent the breakdown voltage between the emitter and the base of the transistor from decreasing.

3 (a) to 3 (e) are process sectional views for explaining a second embodiment of the method for manufacturing a bipolar semiconductor device according to the present invention. The process up to the step of forming the insulating region 2 on the surface of the n-type silicon substrate 1 is the same as in the case of the first embodiment. Next, an n-type collector region 3 and an n-type polycrystalline silicon layer 4 having a thickness of about 300 nm are formed by an epitaxial growth method, and a BSG (borosilicate glass) having a thickness of 30 nm containing boron of about 4 to 6 mol% is formed thereon. ) A film 16 is formed [FIG. 3 (a)].

Next, the n-type collector region 3 is covered with a photoresist film 7 and boron is ion-implanted at an acceleration energy of 30 keV to about 1 × 10 ¹⁶ cm ^-2 to form a p-type polycrystalline silicon layer 8. . As in the previous embodiment, the photoresist film 7 may be slightly larger or smaller than the size of the single crystal silicon layer (3) [FIG.
(B)]. Next, the surface of the photoresist film is removed to about 200 nm by isotropic etching, and a silicon oxide film 17 is formed on the BSG film 16 by the liquid phase epitaxy method using the photoresist film as a mask. A suitable film thickness of this silicon oxide film 17 is about 50 to 200 nm [FIG.
(C)].

Next, the photoresist film 7 is removed, and boron is diffused from the BSG film 16 to the surface of the n-type collector region 3 by heat treatment at 1000 ° C. for 30 seconds to form the p-type base region 11. At this time, boron is also diffused on the surface of the p-type polycrystalline silicon layer 8. Further, at this time, boron in the p-type polycrystalline silicon layer 8 is also diffused, and the p-type single crystal silicon region 10 is formed around the single crystal layer. However, when the size of the photoresist film is slightly smaller than the size of the single crystal silicon layer, the p-type single crystal silicon region 10 is formed at the time of ion implantation of boron and further diffused by heat treatment [FIG. d)].

Next, the exposed BSG film is removed by a wet or dry etching method, and then the film thickness is about 20.
After growing a 0 nm polycrystalline silicon layer, arsenic was added to 50 nm.
Ions are implanted under the conditions of keV and 1 × 10 ¹⁶ cm ⁻² and patterned by a photoresist film to form an n-type polycrystalline silicon layer 12. Then, heat treatment at 1000 ° C. for 20 seconds diffuses arsenic to the surface of the single crystal silicon layer,
The n-type emitter region 13 is formed. Next, an insulating film 14 is formed, an opening is formed on the n-type polycrystalline silicon layer 12,
Aluminum is deposited by the sputtering method and patterned to form the emitter electrode 15 [FIG.
(E)].

According to this embodiment, the same effects as those of the first embodiment can be obtained, and in addition, the following effects can be obtained. Since the thermal oxidation is not performed after the p-type polycrystalline silicon layer 8 is formed, impurities in the p-type polycrystalline silicon layer 8 may be absorbed by the growing thermal oxide film [9 in FIG. 2 (d)]. In addition, the base can be pulled out with low resistance. For the same reason, the impurities in the p-type polycrystalline silicon layer 8 do not largely diffuse into the n-type single-crystal silicon layer (3), and the transistor can be formed with high accuracy, and the size can be further reduced. Can contribute to.

The preferred embodiment has been described above.
The present invention is not limited to these examples, and various modifications can be made within the scope of the present invention described in the claims. For example, in the embodiment, the epitaxial growth method is used to form the n-type single crystal silicon layer to be the collector region, but instead of this method, an amorphous silicon layer is formed and then partially monocrystallized. You may do it. Also, the doping impurities are changed to boron during the epitaxial growth for forming the collector region,
The base region may be formed by an epitaxial method. Further, as the substrate, a p-type silicon substrate having an n ⁺ -type buried layer and an n-type epitaxial layer formed on the surface can be used instead of the substrate of the embodiment. Also,
In the embodiment, the single transistor is explained, but
The present invention is applicable not only to a single unit but also to a bipolar type integrated circuit and Bi
The present invention can be applied to a semiconductor integrated circuit such as a CMOS integrated circuit, and can also be applied to a pnp transistor whose conductivity types are all reversed.

[0025]

As described above, the bipolar semiconductor device according to the present invention has an n-type transistor forming region.
Since the type single crystal silicon layer and the polycrystalline silicon layer serving as the base extraction layer are formed of the same layer of silicon, according to the present invention, the step difference in the emitter opening can be significantly reduced. Therefore, according to the present invention, it is possible to reduce the thickness of the polycrystalline silicon layer for extracting the emitter, and it is possible to extract with a low resistance even for a miniaturized emitter. Further, since the polycrystalline silicon for extracting the emitter is not formed by filling the opening, it is possible to avoid a situation in which the transistor cannot be formed because the opening cannot be filled. Therefore, according to the present invention, all the transistors can be stably formed even in a semiconductor integrated circuit in which large-sized transistors are mixedly present.

Further, according to the present invention, since the entire region of the transistor can be formed by only one photoresist process, there is no need to provide a margin for misalignment, which contributes to miniaturization of the device. be able to. In addition, in the conventional example in which the emitter is formed by the self-alignment method, a process requiring strict process control of filling the inside of the cavity with polycrystalline silicon is required, but such a process is not used in the present invention. In addition, since the manufacturing method is a combination of relatively easy steps, manufacturing with high yield becomes possible.

Further, by etching away the surface of the photoresist film by a predetermined thickness or by side-etching the silicon nitride film by a predetermined amount, an emitter having a width less than the resolution limit of the photoresist can be formed. it can. Furthermore, since a certain distance can be provided between the emitter and the base extraction layer, a required emitter-base breakdown voltage can be secured even in a miniaturized transistor.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a bipolar semiconductor device according to the present invention.

FIG. 2 is a process cross-sectional view for explaining the first embodiment of the method of manufacturing the bipolar semiconductor device according to the present invention.

FIG. 3 is a process sectional view for explaining the second embodiment of the method for manufacturing the bipolar semiconductor device according to the present invention.

FIG. 4 is a process cross-sectional view for explaining a conventional manufacturing method.

[Explanation of symbols]

 1 n-type silicon substrate 2 insulating region 3 n-type collector region 4 n-type polycrystalline silicon layer 5 silicon oxide film 6 silicon nitride film 7 photoresist film 8 p-type polycrystalline silicon layer 9 silicon oxide film 10 p-type single crystal silicon region 11 p-type base region 12 n-type polycrystalline silicon layer 13 n-type emitter region 14 insulating film 15 emitter electrode 16 BSG film 17 silicon oxide film 101 n-type silicon substrate 102 insulating region 103 first silicon oxide film 104 silicon nitride film 105 First polycrystalline silicon layer 106 Second silicon oxide film 107 Third silicon oxide film 108 Second polycrystalline silicon layer 109 Fourth silicon oxide film 110 External base region 111 Internal base region 112 Third polycrystalline Silicon layer 113 Emitter region 114 Emitter electrode

Claims (11)

[Claims] 1. A semiconductor substrate having a substantially flat surface, in which an insulating region is formed on the surface, and a first semiconductor region of the first conductivity type is formed in a region surrounded by the insulating region; A second-conductivity-type polycrystalline silicon film formed on the region, and a first-conductivity-type second semiconductor region formed on the first semiconductor region. A first diffusion layer of the second conductivity type is formed in the periphery and the surface region, and a second diffusion layer of the first conductivity type is formed in the surface region of the first diffusion layer. Characteristic bipolar semiconductor device. 2. The polycrystalline silicon film and the second semiconductor region are covered with an insulating film having an opening on the second diffusion layer, and the second insulating film is formed on the insulating film via the opening.
2. The bipolar semiconductor device according to claim 1, further comprising a first-conductivity-type polycrystalline silicon film formed in contact with the diffusion layer. 3. The polycrystalline silicon film of the second conductivity type and the second semiconductor region have a substantially flat surface, and no step is formed between them. Bipolar semiconductor device. 4. The bipolar semiconductor device according to claim 1, wherein the insulating region is composed of a silicon oxide film formed by a selective oxidation method. 5. Silicon is formed on a semiconductor substrate having a substantially flat surface, in which an insulating region is formed on the surface and a first semiconductor region of the first conductivity type is formed in a region surrounded by the insulating region. To form a first polycrystalline silicon film on the insulating region and a first polycrystalline silicon film on the first semiconductor region.
Forming a second semiconductor region of conductivity type and single crystal; and doping the first polycrystalline silicon film with an impurity of second conductivity type to make the first polycrystalline silicon film a second conductivity type. A step of forming an insulating film having an opening in a central portion of the second semiconductor region covering the first polycrystalline silicon film and the second semiconductor region; Forming a second diffusion type first diffusion layer in a surface region of the second semiconductor region by doping an impurity of a second conduction type; and forming a second diffusion type first diffusion layer in the first diffusion layer through the opening. An impurity of the first conductivity type is doped to form a first region in a surface region of the first diffusion layer.
And a step of forming a conductive type second diffusion layer. 6. Silicon is formed on a semiconductor substrate having a substantially flat surface, in which an insulating region is formed on the surface and a first semiconductor region of the first conductivity type is formed in a region surrounded by the insulating region. To form a first polycrystalline silicon film on the insulating region and a first polycrystalline silicon film on the first semiconductor region.
Forming a second semiconductor region of conductivity type and single crystal; forming a first silicon oxide film and a silicon nitride film on the first polycrystalline silicon film and on the second semiconductor region. And a step of forming a photoresist film covering the second semiconductor region on the silicon nitride film, and doping the first polycrystalline silicon film with a second conductivity type impurity using the photoresist film as a mask. To make the first polycrystalline silicon film a second conductivity type, a step of selectively removing the silicon nitride film by using the photoresist film as a mask, and a thermal oxidation process to perform a thermal oxidation treatment on the silicon nitride film. Forming a second silicon oxide film on an uncovered region, and doping a second conductivity type impurity using the second silicon oxide film as a mask to form a surface region of the second semiconductor region A first diffusion layer of a second conductivity type on the first silicon oxide layer, a step of etching away the first silicon oxide film on a region where the second silicon oxide film is not formed, and a first silicon oxide layer. Forming a second polycrystalline silicon film of the first conductivity type in contact with the first diffusion layer in the removed region of the film; and performing a heat treatment to remove impurities in the second polycrystalline silicon film. A step of diffusing into the first diffusion layer to form a second diffusion layer of the first conductivity type in the surface region of the first diffusion layer. 7. The photoresist is used as a mask to dope the first polycrystalline silicon film with impurities of a second conductivity type, and then the photoresist film is used as a mask to selectively remove the silicon nitride film. 7. The method for manufacturing a bipolar semiconductor device according to claim 6, wherein the surface of the photoresist film is removed by a predetermined thickness. 8. The bipolar semiconductor device according to claim 6, wherein the silicon nitride film is side-etched by a predetermined amount when the silicon nitride film is selectively removed using the photoresist film as a mask. Production method. 9. A silicon substrate is formed on a semiconductor substrate having a substantially flat surface, in which an insulating region is formed on the surface and a first semiconductor region of the first conductivity type is formed in a region surrounded by the insulating region. To form a first polycrystalline silicon film on the insulating region and a first polycrystalline silicon film on the first semiconductor region.
Forming a second semiconductor region of conductivity type and single crystal; forming a first silicon oxide film on the first polycrystalline silicon film and on the second semiconductor region; Forming a photoresist film on the silicon oxide film to cover the second semiconductor region, and doping the first polycrystalline silicon film with a second conductivity type impurity by using the photoresist film as a mask. A step of converting the first polycrystalline silicon film into a second conductivity type; a step of growing silicon oxide by using the photoresist film as a mask to form a second silicon oxide film; and a step of forming a second silicon oxide film in the second semiconductor region. A second conductivity type first impurity is doped into the surface region of the second semiconductor region by doping a second conductivity type impurity.
Forming a diffusion layer of the second silicon oxide film, etching the first silicon oxide film on the region where the second silicon oxide film is not formed, and removing the first silicon oxide film on the region where the first silicon oxide film is removed. Forming a second polycrystalline silicon film of the first conductivity type in contact with the first diffusion layer; and performing heat treatment to diffuse impurities in the second polycrystalline silicon film into the first diffusion layer. And a step of forming a second diffusion layer of the first conductivity type in the surface region of the first diffusion layer, the method of manufacturing a bipolar semiconductor device. 10. The photoresist film after the first polycrystalline silicon film is doped with an impurity of a second conductivity type using the photoresist film as a mask, and before the silicon oxide is grown using the photoresist film as a mask. 10. The method of manufacturing a bipolar semiconductor device according to claim 9, wherein the surface of the is removed by a predetermined thickness. 11. The first silicon oxide film contains impurities of a second conductivity type, and the first diffusion layer is formed by heat treatment so that the impurities of the first silicon oxide film are changed to the second impurities. 10. The method for manufacturing a bipolar semiconductor device according to claim 9, wherein the method is performed by diffusing into the semiconductor region.