JP5569526B2 - Semiconductor device - Google Patents
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- JP5569526B2 JP5569526B2 JP2011521864A JP2011521864A JP5569526B2 JP 5569526 B2 JP5569526 B2 JP 5569526B2 JP 2011521864 A JP2011521864 A JP 2011521864A JP 2011521864 A JP2011521864 A JP 2011521864A JP 5569526 B2 JP5569526 B2 JP 5569526B2
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- 239000004065 semiconductor Substances 0.000 title claims description 70
- 239000000758 substrate Substances 0.000 claims description 45
- 239000012535 impurity Substances 0.000 claims description 23
- 239000010410 layer Substances 0.000 description 158
- 230000015556 catabolic process Effects 0.000 description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 13
- 229920005591 polysilicon Polymers 0.000 description 13
- 238000000605 extraction Methods 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 238000004364 calculation method Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- -1 phosphorus ions Chemical class 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66265—Thin film bipolar transistors
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- Bipolar Transistors (AREA)
Description
本発明は、半導体装置に関し、特にバイポーラトランジスタを備えた半導体装置に関する。 The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a bipolar transistor.
バイポーラトランジスタは、例えば、半導体基板に、第１導電型のコレクタ層と第２導電型のベース層と第１導電型のエミッタ層とが順番に積層して設けられ、これらの各層に個々に導通する電極が形成された構造をもつ。このようなバイポーラトランジスタのエミッタコレクタ耐圧特性やベースコレクタ耐圧特性に代表される耐圧特性において高い耐圧を得るには、低濃度コレクタ層の膜厚を厚くする必要がある。 For example, the bipolar transistor is formed by sequentially laminating a first conductivity type collector layer, a second conductivity type base layer, and a first conductivity type emitter layer on a semiconductor substrate, and each of these layers is electrically connected to each other. A structure in which an electrode is formed. In order to obtain a high breakdown voltage in the breakdown voltage characteristic represented by the emitter-collector breakdown voltage characteristic and the base collector breakdown voltage characteristic of such a bipolar transistor, it is necessary to increase the thickness of the low concentration collector layer.
一方、コレクタと基板間の容量低下を図るため、ＳＯＳ（Ｓｅｍｉｃｏｎｄｕｃｔｏｒ ｏｎ Ｓａｐｐｈｉｒｅ）に代表される絶縁性基板上に半導体層が設けられた基板や、ＳＯＩ（Ｓｅｍｉｃｏｎｄｕｃｔｏｒ ｏｎ Ｉｎｓｕｌａｔｏｒ）基板に代表される半導体基板上に埋込絶縁層を介して半導体層が設けられた基板を用いて形成された種々のバイポーラトランジスタが提案されている。例えば、特開平８−９７２２５号公報には、ＳＯＩ基板を用いて形成されたバイポーラトランジスタが開示されている。 On the other hand, in order to reduce the capacitance between the collector and the substrate, a substrate in which a semiconductor layer is provided on an insulating substrate typified by SOS (Semiconductor on Sapphire), or a semiconductor substrate typified by an SOI (Semiconductor on Insulator) substrate. Various bipolar transistors formed using a substrate on which a semiconductor layer is provided via a buried insulating layer have been proposed. For example, Japanese Patent Application Laid-Open No. 8-97225 discloses a bipolar transistor formed using an SOI substrate.
しかしながら、上記のようなバイポーラトランジスタにおいて、所望の耐圧特性を得るには、絶縁性基板上あるいは埋込絶縁層上の半導体層の厚さを数ミクロン以上に厚くする必要がある。高い耐圧特性を得るために、この半導体層の厚さを数ミクロン以上に厚くすると、製造コストが増加し、さらに、通常用いられる汎用のＣＭＯＳやｎｐｎバイポーラトランジスタ、ｐｎｐバイポーラトランジスタと同一ウェハ内に作り込むことが困難になり、そのためワンチップＩＣの製造が困難になる。 However, in the bipolar transistor as described above, in order to obtain a desired breakdown voltage characteristic, it is necessary to increase the thickness of the semiconductor layer on the insulating substrate or the buried insulating layer to several microns or more. In order to obtain high breakdown voltage characteristics, if the thickness of this semiconductor layer is increased to several microns or more, the manufacturing cost increases, and further, it is formed on the same wafer as the general-purpose CMOS, npn bipolar transistor, and pnp bipolar transistor that are usually used. It becomes difficult to manufacture a one-chip IC.
本発明は上記問題を解決するためになされたものであって、その目的は、高耐圧のバイポーラトランジスタを備えた半導体装置を提供することにある。 The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device including a high breakdown voltage bipolar transistor.
本発明の一態様によれば、半導体基板上の絶縁層の上または絶縁性基板の上に設けられた半導体層と、第１導電型のコレクタ領域、第２導電型のベース領域および第１導電型のエミッタ領域を含むバイポーラトランジスタと、を有し、前記コレクタ領域、前記ベース領域および前記エミッタ領域は、下層側からこの順で積層配置され、前記絶縁層または前記絶縁性基板と前記コレクタ領域との間に、第２導電型半導体層領域を有する半導体装置が提供される。 According to one embodiment of the present invention, a semiconductor layer provided on an insulating layer on a semiconductor substrate or on an insulating substrate, a collector region of a first conductivity type, a base region of a second conductivity type, and a first conductivity A bipolar transistor including an emitter region of a type, and the collector region, the base region, and the emitter region are stacked in this order from the lower layer side, the insulating layer or the insulating substrate and the collector region, In the meantime, a semiconductor device having a second conductivity type semiconductor layer region is provided.
本発明によれば、絶縁性基板上に半導体層が設けられた基板や半導体基板上に絶縁層を介して半導体層が設けられた基板を用いて形成可能なバイポーラトランジスタ構造を有しながら、前記半導体層の厚さにかかわらず、高い耐圧特性を実現できる半導体装置を提供することができる。 According to the present invention, while having a bipolar transistor structure that can be formed using a substrate provided with a semiconductor layer on an insulating substrate or a substrate provided with a semiconductor layer via an insulating layer on the semiconductor substrate, A semiconductor device capable of realizing high withstand voltage characteristics regardless of the thickness of the semiconductor layer can be provided.
本発明の一実施形態による半導体装置は、半導体基板上の絶縁層の上または絶縁性基板の上に設けられた半導体層と、第１導電型のコレクタ領域、第２導電型のベース領域および第１導電型のエミッタ領域を含むバイポーラトランジスタと、を有し、前記コレクタ領域、前記ベース領域および前記エミッタ領域は、下層側からこの順で積層配置され、前記絶縁層または前記絶縁性基板と前記コレクタ領域との間に、第２導電型半導体層領域を有する。 A semiconductor device according to an embodiment of the present invention includes a semiconductor layer provided on an insulating layer on a semiconductor substrate or an insulating substrate, a first conductivity type collector region, a second conductivity type base region, and a first conductivity type. A bipolar transistor including an emitter region of one conductivity type, and the collector region, the base region, and the emitter region are stacked in this order from the lower layer side, and the insulating layer or the insulating substrate and the collector A second conductivity type semiconductor layer region is provided between the regions.
上記半導体装置において、前記絶縁層または前記絶縁性基板と前記コレクタ領域との間の前記半導体層領域は、第２導電型不純物濃度が第１導電型不純物濃度に対して同等である領域を含んでいてもよい。 In the semiconductor device, the semiconductor layer region between the insulating layer or the insulating substrate and the collector region includes a region in which the second conductivity type impurity concentration is equal to the first conductivity type impurity concentration. May be.
上記半導体装置において、前記絶縁層または前記絶縁性基板と前記コレクタ領域との間の前記半導体層領域は、第２導電型不純物濃度が前記コレクタ領域の第１導電型不純物濃度より低いことが好ましい。 In the semiconductor device, the semiconductor layer region between the insulating layer or the insulating substrate and the collector region preferably has a second conductivity type impurity concentration lower than a first conductivity type impurity concentration of the collector region.
上記半導体装置において、前記絶縁層または前記絶縁性基板と前記コレクタ領域との間の前記半導体層領域は、第１導電型不純物が導入されていないノンドープ領域を含んでいてもよい。 In the semiconductor device, the semiconductor layer region between the insulating layer or the insulating substrate and the collector region may include a non-doped region into which the first conductivity type impurity is not introduced.
上記半導体装置は、前記コレクタ領域が、前記絶縁層上または前記絶縁性基板上の第２導電型の前記半導体層の上層側に第１導電型不純物を導入して形成された第１導電型領域であり、前記第２導電型半導体層領域が、前記絶縁層または前記絶縁性基板に接し、前記第１導電型領域に至る半導体領域である構造をとることができる。 In the semiconductor device, the collector region is formed by introducing a first conductivity type impurity into the upper layer side of the second conductivity type semiconductor layer on the insulating layer or the insulating substrate. The second conductivity type semiconductor layer region may be a semiconductor region that is in contact with the insulating layer or the insulating substrate and reaches the first conductivity type region.
上記導体装置は、前記ベース領域が、前記絶縁層上または前記絶縁性基板上の前記半導体層の表面に形成されたフィールド絶縁膜で囲まれた領域に設けられ、前記コレクタ領域が、前記フィールド絶縁膜下において、前記ベース領域下から該フィールド絶縁膜の外縁まで延在し、前記コレクタ領域の延在部に接続する引き出し領域が設けられ、該引き出し領域に電気的に接続するように、前記フィールド絶縁膜外側の前記半導体層上にコレクタ電極が設けられている構造をとることができる。 In the conductor device, the base region is provided in a region surrounded by a field insulating film formed on the surface of the semiconductor layer on the insulating layer or the insulating substrate, and the collector region is provided in the field insulating region. Under the film, there is provided a lead region extending from below the base region to the outer edge of the field insulating film and connected to the extending portion of the collector region, and the field is electrically connected to the lead region. A structure in which a collector electrode is provided on the semiconductor layer outside the insulating film can be employed.
本発明の一実施形態による半導体装置は、第１導電型のコレクタ領域、第２導電型のベース領域および第１導電型のエミッタ領域が下層側からこの順に積層配置されたバイポーラトランジスタを備えている。このコレクタ領域は、半導体基板上の絶縁層の上または絶縁性基板（以下、絶縁層と絶縁性基板を併せて「絶縁基体」という）の上の第２導電型半導体層に第１導電型不純物をイオン注入により導入してこの半導体層の上層側に形成することができる。このコレクタ領域上にベース領域およびエミッタ領域が積層される。このように形成されたコレクタ領域と絶縁基体の間の半導体層領域は、第２導電型を有する。すなわち、この半導体層領域は、コレクタ領域の導電型と反対の導電型を有し、この半導体層領域とコレクタ領域とでｎｐ接合あるいはｐｎ接合が形成されている。 A semiconductor device according to an embodiment of the present invention includes a bipolar transistor in which a first conductivity type collector region, a second conductivity type base region, and a first conductivity type emitter region are stacked in this order from the lower layer side. . The collector region is formed on the second conductive type semiconductor layer on the insulating layer on the semiconductor substrate or on the insulating substrate (hereinafter, the insulating layer and the insulating substrate are collectively referred to as “insulating base”). Can be introduced by ion implantation and formed on the upper layer side of this semiconductor layer. A base region and an emitter region are stacked on the collector region. The semiconductor layer region thus formed between the collector region and the insulating substrate has the second conductivity type. That is, the semiconductor layer region has a conductivity type opposite to that of the collector region, and an np junction or a pn junction is formed between the semiconductor layer region and the collector region.
上記のように形成されたコレクタ領域と絶縁基体の間の第２導電型の半導体層領域は、第２導電型の不純物濃度が前記コレクタ領域の第１導電型不純物濃度より低い。 The second conductivity type semiconductor layer region between the collector region and the insulating base formed as described above has a second conductivity type impurity concentration lower than the first conductivity type impurity concentration of the collector region.
この第２導電型の半導体層領域は、第１導電型不純物濃度が第２導電型不純物濃度と同等またはそれ以下になるように、第１導電型不純物が導入されたドープ領域であっても、第１導電型不純物が導入されていないノンドープ領域であってもよい。すなわち、この第２導電型の半導体層領域は、コレクタ領域の導電型（第１導電型）に対して反対の導電型（第２導電型）を持ち、第２導電型である限り第１導電型不純物を含んでいてもよいし、含まなくてもよい。 Even if the second conductivity type semiconductor layer region is a doped region into which the first conductivity type impurity is introduced so that the first conductivity type impurity concentration is equal to or less than the second conductivity type impurity concentration, It may be a non-doped region in which the first conductivity type impurity is not introduced. That is, the semiconductor layer region of the second conductivity type has the opposite conductivity type (second conductivity type) to the conductivity type of the collector region (first conductivity type), and the first conductivity as long as it is the second conductivity type. A type impurity may or may not be included.
このような構造にすることにより、前記絶縁基体上の半導体層において、コレクタ領域に相当する上層側領域に対して下層側領域の伝導帯下端のポテンシャルが持ち上がり、ベースコレクタ接合に逆バイアスを印加すると、コレクタ領域に相当する上層側領域から下層側領域にわたって空乏層が一様に広がる。この現象は、エミッタコレクタ間隔（基板平面におけるエミッタ領域の中央部からコレクタ電極までの最短距離）を広げた場合でも同様に生じる。したがって、上記構造によって、前記半導体層の厚みによらないで、エミッタコレクタ間隔を広げることにより、耐圧特性を向上させることできる。 By adopting such a structure, in the semiconductor layer on the insulating substrate, the potential at the lower end of the conduction band of the lower layer region is raised with respect to the upper layer region corresponding to the collector region, and a reverse bias is applied to the base collector junction The depletion layer uniformly spreads from the upper layer side region corresponding to the collector region to the lower layer side region. This phenomenon occurs even when the emitter-collector interval (the shortest distance from the center of the emitter region to the collector electrode in the substrate plane) is increased. Therefore, with the above structure, the breakdown voltage characteristic can be improved by widening the emitter-collector interval without depending on the thickness of the semiconductor layer.
以下、図面を参照して、本発明の実施の形態について詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
図１は、本実施形態におけるｎｐｎ型バイポーラトランジスタの一例を示す断面図である。 FIG. 1 is a cross-sectional view showing an example of an npn-type bipolar transistor in the present embodiment.
図１に示すバイポーラトランジスタは、半導体基板（シリコン基板）１上に絶縁層（埋込酸化膜）２を介して半導体層（ＳＯＩ層）が設けられたＳＯＩ基板を用いて形成される。このＳＯＩ層には、下層側に低濃度第２導電型層（低濃度ｐ型領域）３、上層側に第１導電型のコレクタ層（ｎ型コレクタ領域）４が設けられる。第１導電型コレクタ層４上には第２導電型のベース層（ｐ型ベース領域）７が設けられ、このベース層７の表面領域には第１導電型のエミッタ層（ｎ型エミッタポリシリコン層）８が設けられている。このエミッタ層８上にはエミッタ電極９が設けられている。第２導電型のベース層７の周辺領域のフィールド酸化膜１２上にはベース引き出し用の第２導電型ポリシリコン領域（ｐ型ポリシリコン領域）１１が設けられている。この第２導電型ポリシリコン領域１１上には、ベース電極６が設けられている。第２導電型ポリシリコン領域１１とエミッタ層８は層間絶縁膜１０で絶縁されている。コレクタ層４の周辺領域には、オーミック性電極を形成するために、イオン注入などによりコレクタ引き出し用の第１導電型高濃度領域（ｎ＋引き出し層）１３が形成されている。この第１導電型高濃度領域１３上にはコレクタ電極５が設けられている。The bipolar transistor shown in FIG. 1 is formed using an SOI substrate in which a semiconductor layer (SOI layer) is provided on a semiconductor substrate (silicon substrate) 1 with an insulating layer (buried oxide film) 2 interposed therebetween. This SOI layer is provided with a low-concentration second conductivity type layer (low-concentration p-type region) 3 on the lower layer side and a first conductivity-type collector layer (n-type collector region) 4 on the upper layer side. A second conductivity type base layer (p type base region) 7 is provided on the first conductivity
なお、本発明において、第１導電型とはｐ型とｎ型の一方を意味しており、第２導電型とはｐ型とｎ型の他方を意味する。以下においては、本発明の一実施形態として、第１導電型をｎ型とし、第２導電型をｐ型としたものを例示するが、この形態に限定されない。 In the present invention, the first conductivity type means one of p-type and n-type, and the second conductivity type means the other of p-type and n-type. In the following, an embodiment in which the first conductivity type is n-type and the second conductivity type is p-type is illustrated as an embodiment of the present invention, but the present invention is not limited to this.
上記のバイポーラトランジスタ構造は、埋込酸化膜２上に１０１５ｃｍ−３程度の低濃度ｐ型層をＳＯＩ層として有するＳＯＩ基板を用いて、下記の通り形成することができる。The above bipolar transistor structure can be formed as follows using an SOI substrate having a low-concentration p-type layer of about 10 15 cm −3 as an SOI layer on the buried
まず、ＳＯＩ基板上に、バイポーラトランジスタを形成する部分を規定するために、ＬＯＣＯＳプロセスにてフィールド酸化膜１２を形成する。その後、リンのイオン注入を行い、ＳＯＩ層の上層側領域に１０１６ｃｍ−３程度のｎ型層であるコレクタ層４を形成する。次に、このコレクタ層４の一部分に選択的に高濃度リンイオン注入を行い、ｎ＋コレクタ引き出し層１３を形成する。その後、コレクタ電極５を前記ｎ＋コレクタ引き出し層１３上に設ける。First, a
このようにして、ＳＯＩ層の埋込酸化膜２に近い下層側領域は低濃度ボロンでドーピングされたｐ型層となっており、このＳＯＩ層のベース層に近い上層側領域は、イオン注入法でリンがドーピングされたｎ型層（コレクタ層４）となっている。本例の場合、このｐ型層（低濃度ｐ型領域３）は、０．５μｍ程度の厚みに設定することができる。
In this way, the lower layer side region of the SOI layer near the buried
次に、ボロンのイオン注入を行い、バイポーラトランジスタのベース層７を形成する。なお、ベース層は、拡散またはエピタキシャル層で形成してもよい。このようにして、ベース層の厚みより厚いフィールド酸化膜１２でベース層側面が囲まれ、基板平面方向にベース層中心部からフィールド酸化膜に至って不純物濃度がほぼ均一であるベース層が形成される。その後、ポリシリコン層を形成し、これを加工してベース引き出し用ポリシリコン領域１１を形成する。
Next, boron ions are implanted to form the base layer 7 of the bipolar transistor. Note that the base layer may be formed of a diffusion or epitaxial layer. In this way, the base layer side surface is surrounded by the
次に、層間絶縁膜１０を形成し加工した後、ベース層に通じる高濃度ｎ型ポリシリコン層を形成し加工してエミッタ層８とする。その後、エミッタ層８上にエミッタ電極９を、ベース引き出し用ポリシリコン領域１１上にベース電極６をそれぞれ設ける。
Next, after forming and processing the
エミッタ層８のベース層と接触する部分の幅（図１における横方向の幅：エミッタ幅ＷＥ）は、高耐圧特性を重視する点、つくり易さの点から、例えば０．３μｍ程度又はそれ以上に設定することができる。The width of the portion of the emitter layer 8 in contact with the base layer (lateral width in FIG. 1: emitter width W E ) is, for example, about 0.3 μm or so from the viewpoint of emphasizing high breakdown voltage characteristics and ease of manufacturing. It can be set above.
ベース層７のエミッタコレクタ間隔方向の幅（図１における横方向の幅：ベース幅ＷＢ）は、エミッタ層８と引き出し用ポリシリコン領域１１との間に層間絶縁膜１０を設けて絶縁を確保するため、エミッタ幅ＷＥより例えば０．４μｍ程度広く又はそれ以上広く設定することができる。The width of the base layer 7 in the emitter-collector interval direction (lateral width in FIG. 1: base width W B ) is ensured by providing an
このようにして形成したｎｐｎバイポーラトランジスタのエミッタコレクタ耐圧特性、ベースコレクタ耐圧特性において、例えばＳＯＩ層の下層側領域に１０１５ｃｍ−３程度の低濃度ｐ型層３、ＳＯＩ層の上層側領域に１０１６ｃｍ−３程度のｎ型層（コレクタ層）４を配置することにより、ＳＯＩ層の上層側領域に比べてＳＯＩ層の下層側領域の伝導体下端のポテンシャルが持ち上がるため、ベースコレクタ接合に逆バイアスが印加したとき、ＳＯＩ層の上層側領域と下層側領域の全体に均一に空乏層が広がり、コレクタ引き出し用高濃度ｎ型領域１３近辺において最も高い電界が印加されるため、ＳＯＩ層の厚みによらないで、エミッタコレクタ間隔を広げることにより、耐圧特性を向上させることできる。In the emitter-collector breakdown voltage characteristics and base-collector breakdown voltage characteristics of the npn bipolar transistor thus formed, for example, a low concentration p-
図２に、ＳＯＩ層の下層側領域に１０１５ｃｍ−３程度の低濃度ｐ型層３、ＳＯＩ層の上層側領域に１０１６ｃｍ−３程度のｎ型層（コレクタ層）４が配置されたｎｐｎバイポーラトランジスタにおいて、エミッタ電極９とコレクタ電極５の間隔（エミッタコレクタ間隔：ΔＬＥ−Ｃ）に対する、エミッタコレクタ耐圧（ＢＶＣＥＯ）とベースコレクタ耐圧（ＢＶＣＢＯ）のシミュレーション計算値の変化を示す（図中に「ｓｉｍ．特性」として「◇」（ベースコレクタ耐圧）及び「○」（エミッタコレクタ耐圧）で示す）。エミッタコレクタ間隔が広がるにしたがって、空乏層がコレクタ層の横方向に大きく広がり、それぞれの耐圧特性が向上する。これは、ＳＯＩ層の下層側領域に低濃度ｐ型層３、ＳＯＩ層の上層側領域にｎ型層４が配置されていることにより、ＳＯＩ層の上層側領域に比べてＳＯＩ層の下層側領域の伝導体下端のポテンシャルが持ち上がるため、ＳＯＩ層と埋込酸化膜の界面に存在するドーパント不純物のパイルアップ層の影響が軽減されているためと考えられる。実際に拡散試作を行ったデバイスのエミッタコレクタ耐圧とベースコレクタ耐圧を、図２にシミュレーション計算値と併せて示す（図中に「実測特性」として「◆」（ベースコレクタ耐圧）及び「●」（エミッタコレクタ耐圧）で示す）。シミュレーション耐圧特性とほぼ同等の耐圧特性が実デバイスにおいて得られていることが分かる。In FIG. 2, a low-concentration p-
なお、ＳＯＩ層の下層側領域にｐ型のノンドープ層が設けられている場合においても、上記実施例とほぼ同じ耐圧特性向上効果が得られる。また、ＳＯＩ層の下層側領域に第１導電型の不純物濃度と第２導電型の不純物濃度が同程度であるｐ型のドープ層が設けられている場合においても、上記実施例に示したような耐圧特性の向上を得ることができる。 Even when a p-type non-doped layer is provided in the lower layer side region of the SOI layer, substantially the same breakdown voltage characteristic improving effect as that in the above embodiment can be obtained. In addition, even when a p-type doped layer having the same impurity concentration of the first conductivity type and the impurity concentration of the second conductivity type is provided in the lower layer side region of the SOI layer, as shown in the above embodiment. It is possible to obtain a significant improvement in breakdown voltage characteristics.
以上のように、本発明によれば、絶縁基体上の半導体層の膜厚を維持したまま、バイポーラトランジスタのエミッタコレクタ耐圧特性、ベースコレクタ耐圧特性を大きく向上させることができる。従って、通常の汎用的なＣＭＯＳ、ｎｐｎバイポーラトランジスタ、ｐｎｐバイポーラトランジスタと同一ウェハ内に、本発明の高耐圧トランジスタを作り込むことができ、ワンチップＩＣの提供が可能となる。 As described above, according to the present invention, the emitter-collector breakdown voltage characteristic and the base-collector breakdown voltage characteristic of the bipolar transistor can be greatly improved while maintaining the film thickness of the semiconductor layer on the insulating substrate. Therefore, the high breakdown voltage transistor of the present invention can be fabricated in the same wafer as a general general-purpose CMOS, npn bipolar transistor, and pnp bipolar transistor, and a one-chip IC can be provided.
以上、実施例を参照して本発明を説明したが、本発明は上記実施例に限定されるものではない。本発明の構成や詳細には、本発明の範囲内で当業者が理解し得る様々な変更をすることができる。 While the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.
この出願は、２００９年７月１０日に出願された日本出願特願２００９−１６３６８５を基礎とする優先権を主張し、その開示の全てをここに取り込む。 This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2009-163685 for which it applied on July 10, 2009, and takes in those the indications of all here.
１ シリコン基板
２ 埋込酸化膜
３ 低濃度ｐ型領域
４ コレクタ層（ｎ型コレクタ領域）
５ コレクタ電極
６ ベース電極
７ ベース層（ｐ型ベース領域）
８ エミッタ層（ｎ型エミッタポリシリコン層）
９ エミッタ電極
１０ 層間絶縁膜
１１ ベース引き出し用ポリシリコン領域（ｐ型ポリシリコン領域）
１２ フィールド酸化膜
１３ コレクタ引き出し用高濃度ｎ型領域（ｎ＋引き出し層）1
5
8 Emitter layer (n-type emitter polysilicon layer)
9
12
Claims (5)
前記コレクタ領域、前記ベース領域および前記エミッタ領域は、下層側からこの順で積層配置され、
前記絶縁層または前記絶縁性基板と前記コレクタ領域との間に、第２導電型半導体層領域を有し、
前記第２導電型半導体層領域の第２導電型不純物濃度が、前記コレクタ領域の第１導電型不純物濃度より低く、
前記第１導電型はｎ型であり、前記第２導電型はｐ型である、半導体装置。 A bipolar transistor including a semiconductor layer provided on an insulating layer on a semiconductor substrate or on an insulating substrate; a collector region of a first conductivity type; a base region of a second conductivity type; and an emitter region of a first conductivity type Have
The collector region, the base region and the emitter region are stacked in this order from the lower layer side,
Between the insulating layer or the insulating substrate and the collector region, a second conductivity type semiconductor layer region,
Second conductivity type impurity concentration of said second conductivity type semiconductor layer region, rather low than that of the first conductivity type impurity concentration of the collector region,
The semiconductor device, wherein the first conductivity type is n-type and the second conductivity type is p-type .
前記第２導電型半導体層領域は、前記絶縁層または前記絶縁性基板に接し、前記第１導電型領域に至る半導体領域である、請求項１から３のいずれか一項に記載の半導体装置。 The collector region is a first conductivity type region formed by introducing a first conductivity type impurity into the upper layer side of the second conductivity type semiconductor layer on the insulating layer or the insulating substrate;
4. The semiconductor device according to claim 1, wherein the second conductive type semiconductor layer region is a semiconductor region that contacts the insulating layer or the insulating substrate and reaches the first conductive type region. 5.
前記コレクタ領域は、前記フィールド絶縁膜下において、前記ベース領域下から該フィールド絶縁膜の外縁まで延在し、
前記コレクタ領域の延在部に接続する引き出し領域が設けられ、該引き出し領域に電気的に接続するように、前記フィールド絶縁膜外側の前記半導体層上にコレクタ電極が設けられている、請求項４に記載の半導体装置。 The base region is provided in a region surrounded by a field insulating film formed on the surface of the semiconductor layer on the insulating layer or on the insulating substrate,
The collector region extends under the field insulating film from below the base region to an outer edge of the field insulating film,
5. A lead region connected to the extending portion of the collector region is provided, and a collector electrode is provided on the semiconductor layer outside the field insulating film so as to be electrically connected to the lead region. A semiconductor device according to 1.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH02207534A (en) * | 1989-02-08 | 1990-08-17 | Hitachi Ltd | Semiconductor device |
| JPH0637099A (en) * | 1992-07-15 | 1994-02-10 | Hitachi Ltd | Semiconductor substrate and manufacture thereof |
| JP2001345377A (en) * | 2000-06-01 | 2001-12-14 | Unisia Jecs Corp | Semiconductor device |
| JP2002050709A (en) * | 2000-08-04 | 2002-02-15 | Hitachi Ltd | Semiconductor integrated circuit device and manufacturing method thereof |
| JP2003017503A (en) * | 2001-06-29 | 2003-01-17 | Denso Corp | Method for manufacturing semiconductor device, and semiconductor device |
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| JPH01241168A (en) * | 1988-03-23 | 1989-09-26 | Hitachi Ltd | Bipolar transistor and manufacture thereof |
| JPH0346346A (en) * | 1989-07-14 | 1991-02-27 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH11307537A (en) * | 1998-04-20 | 1999-11-05 | Hitachi Ltd | Semiconductor integrated circuit device and producing method therefor |
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| JPH02207534A (en) * | 1989-02-08 | 1990-08-17 | Hitachi Ltd | Semiconductor device |
| JPH0637099A (en) * | 1992-07-15 | 1994-02-10 | Hitachi Ltd | Semiconductor substrate and manufacture thereof |
| JP2001345377A (en) * | 2000-06-01 | 2001-12-14 | Unisia Jecs Corp | Semiconductor device |
| JP2002050709A (en) * | 2000-08-04 | 2002-02-15 | Hitachi Ltd | Semiconductor integrated circuit device and manufacturing method thereof |
| JP2003017503A (en) * | 2001-06-29 | 2003-01-17 | Denso Corp | Method for manufacturing semiconductor device, and semiconductor device |
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