JPH11307537A - Semiconductor integrated circuit device and producing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide techniques capable of producing a semiconductor integrated circuit device having a high-performance bipolar transistor. SOLUTION: An intrinsic base region 10 is connected through a first graft base region 11a formed in the active region of an epitaxial layer 2 and a second graft base region 11b composed of a selected epitaxial layer 7 having a thickness of about 5 nm to a base extraction electrode 5 but when forming an emitter opening part 6, after a silicon oxide film 12 and a polycrystalline silicon film, consisting of the base extraction electrode 5 are worked successively while using a silicon oxide film 4 for a stopper film, the silicon oxide film 4 is removed through wet etching. Thus, the surface of the epitaxial layer 32 is not groven and a distance between the intrinsic base region 10 and the base extraction electrode 5 is kept short and constant.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having a bipolar transistor.

[0002]

2. Description of the Related Art The structure of an intrinsic base region and a graft base region of a bipolar transistor includes an intrinsic base region formed by impurities introduced into an active region of a semiconductor substrate, and an impurity diffused from a base lead electrode to the semiconductor substrate. A first structure forming a graft base region, a single crystal silicon film being grown on an active region of a semiconductor substrate, an intrinsic base region being formed by the single crystal silicon film, and a base extraction electrode and a semiconductor substrate A second structure that forms a graft base region by the single crystal silicon film grown in the gap, and an intrinsic base region that is formed by impurities introduced into the active region of the semiconductor substrate; Third Graft Base Region Constructed by Inserted Single Crystal Silicon Film There is a structure.

A bipolar transistor having the above first structure is disclosed in, for example, IEE,
Transaction Electron Devices (IEEE
Transaction Electron Devices, Very-High-Speed Sil
icon Bipolar Transistors with In-situ Doped Polysi
licon Emitter and Rapid Vapor-Phase Doping Basevo
l.42, p406, 1995).

A bipolar transistor having the second structure is disclosed in, for example, Japanese Patent Application Laid-Open No. 63-289.
No. 863.

A bipolar transistor having the above third structure is described in, for example, International Electron Device Meetings.
chnical Digest, Process Integration Technology for
sub-30ps ECL BiCMOS usingHeavily Boron Doped Epit
axial Contact pp. 441-444, 1994).

Next, a method of manufacturing the npn-type bipolar transistor having the first structure will be briefly described with reference to FIGS.

First, although not shown, a collector buried layer, an epitaxial layer and a collector pulling diffusion layer are formed on a semiconductor substrate 33 made of p-type single crystal silicon. Next, after a field insulating film 34 is formed on the main surface of the semiconductor substrate 33, the base extraction electrode 35 is formed by processing the polycrystalline silicon film deposited on the semiconductor substrate 33 to which a p-type impurity is added. (Figure 1
6).

Next, after depositing a silicon oxide film 36 on the semiconductor substrate 33, the silicon oxide film 36 and the polycrystalline silicon film forming the base lead-out electrode 35 are sequentially etched by using a resist pattern as a mask to form an emitter opening 37. (FIG. 17).

Next, after implanting p-type impurity ions at a low energy into the semiconductor substrate 33, the semiconductor substrate 33 is subjected to a heat treatment to form an intrinsic base region 38. When heat treatment is performed on the semiconductor substrate 33, p-type impurities diffuse into the semiconductor substrate 33 from the polycrystalline silicon film forming the base extraction electrode 35, and the graft base region 39 is formed.
Is formed (FIG. 18).

Next, after a sidewall spacer 40 composed of an insulating film is formed on the side walls of the silicon oxide film 36 and the base extraction electrode 35 (FIG. 19), an n-type impurity deposited on the semiconductor substrate 33 is added. The emitter electrode 41 is formed by processing the polycrystalline silicon film.
Thereafter, heat treatment is performed on the semiconductor substrate 33 to diffuse n-type impurities from the emitter electrode 41 into the semiconductor substrate 33,
An emitter region 42 is formed (FIG. 20).

Next, a method for manufacturing an npn-type bipolar transistor having the second structure will be briefly described with reference to FIGS.

First, although not shown, a collector buried layer, an epitaxial layer, and a collector pull-up diffusion layer are formed on a semiconductor substrate 43 made of p-type single crystal silicon. Next, after forming a field insulating film 44 on the main surface of the semiconductor substrate 43, a silicon oxide film 45 is deposited on the semiconductor substrate 43 (FIG. 21). Next, the base extraction electrode 46 is formed by processing the polycrystalline silicon film to which the p-type impurity is added, deposited on the semiconductor substrate 43 (FIG. 22).

Next, after depositing a silicon oxide film 47 on the semiconductor substrate 43, the silicon oxide film 47 and the polycrystalline silicon film forming the base lead-out electrode 46 are sequentially etched using a resist pattern as a mask, and an emitter opening 48 is formed. Is formed (FIG. 23).

Next, after removing the silicon oxide film 45 exposed in the active region of the semiconductor substrate 43 (FIG. 24), the single crystal silicon film 49 doped with a p-type impurity is removed by an epitaxial growth technique. The single crystal silicon film 49 is grown to form an intrinsic base region 50 (FIG. 25). Here, the graft base region 51 connecting the base extraction electrode 46 and the intrinsic base region 50 is formed by a single crystal silicon film 49 formed between the base extraction electrode 46 and the semiconductor substrate 43.

Next, after a sidewall spacer 52 composed of an insulating film is formed on the side wall of the silicon oxide film 47 and the intrinsic base region 50 (FIG. 26), an n-type impurity deposited on the semiconductor substrate 43 is added. The resulting polycrystalline silicon film is processed to form an emitter electrode 53. Thereafter, the semiconductor substrate 43 is subjected to a heat treatment, so that the emitter electrode 5
3 to n-type impurities are diffused into the single crystal silicon film 49 to form the emitter region 54 (FIG. 27).

Next, a method of manufacturing the npn-type bipolar transistor having the third structure will be briefly described with reference to FIGS.

First, although not shown, a collector buried layer, an epitaxial layer and a collector pull-up diffusion layer are formed on a semiconductor substrate 55 made of p-type single crystal silicon. Next, after a field insulating film 56 is formed on the main surface of the semiconductor substrate 55, a silicon oxide film 57 is deposited on the semiconductor substrate 55. Next, the semiconductor substrate 55
The base extraction electrode 58 is formed by processing the polycrystalline silicon film to which p-type impurities are added, which is deposited thereon.
8).

Next, after a silicon oxide film 59 is deposited on the semiconductor substrate 55, the silicon oxide film 59 and the polycrystalline silicon film forming the base lead-out electrode 58 are sequentially etched by using a resist pattern as a mask to form an emitter opening 60. Is formed (FIG. 29).

Next, after removing the silicon oxide film 57 exposed in the active region of the semiconductor substrate 55 (FIG. 30), a polycrystalline silicon film 61 is deposited on the semiconductor substrate 55 (FIG. 3).
1) Then, the polycrystalline silicon film 61 is etched back to leave the polycrystalline silicon film 61 between the base extraction electrode 58 and the semiconductor substrate 55 (FIG. 32).

Next, after implanting p-type impurity ions into the semiconductor substrate 55 with low energy, the semiconductor substrate 55 is subjected to a heat treatment to form an intrinsic base region 62 (FIG. 33). Here, a graft base region 63 connecting the base extraction electrode 58 and the intrinsic base region 62
Is constituted by a polycrystalline silicon film 61 formed between the base extraction electrode 58 and the semiconductor substrate 55.

Next, after a sidewall spacer 64 composed of an insulating film is formed on the side walls of the silicon oxide film 59 and the base extraction electrode 58 (FIG. 34), an n-type impurity deposited on the semiconductor substrate 55 is added. The resulting polycrystalline silicon film is processed to form an emitter electrode 65.
Thereafter, heat treatment is performed on the semiconductor substrate 55 to diffuse n-type impurities from the emitter electrode 65 into the semiconductor substrate 55,
An emitter region 66 is formed (FIG. 35).

[0022]

However, the present inventor has found that the method for manufacturing the bipolar transistor has the following problems.

In the npn-type bipolar transistor having the first structure, as shown in FIG. 18, a silicon oxide film 36 and a base lead electrode 35 are formed.
When the emitter opening 37 is formed by sequentially etching the polycrystalline silicon film constituting the semiconductor substrate 33, the surface of the semiconductor substrate 33 is also shaved. Since it takes a long time from when the etching apparatus determines that the etching of the polycrystalline silicon film is completed to when the etching operation is stopped, the semiconductor substrate 33 is usually used.
Is cut by about 80 nm.

Further, the scraping of the semiconductor substrate 33 causes the distance between the intrinsic base region 38 and the graft base region 39 to vary. If the shaved amount of the semiconductor substrate 33 is larger than the designed value, the base operation increases and the circuit operation becomes slow. Conversely, if the amount of scraping of the semiconductor substrate 33 is smaller than the design value, the graft base region 39 and the emitter region 42 are too close to each other, and the breakdown voltage between the emitter region and the base region is reduced.

Further, the positional relationship between the base lead-out electrode 35 and the active region is determined by the alignment accuracy of the lithography technique. The parasitic capacitance between them increases, which hinders the speeding up of the circuit operation.

In the npn-type bipolar transistor having the second structure, since the intrinsic base region 50 and the emitter region 54 are constituted by the single crystal silicon film 49 formed by the epitaxial growth technique, the single crystal silicon film The quality of 49 affects the characteristics of the bipolar transistor. In particular, the variation of the sheet resistance of the intrinsic base region 50 formed on the single crystal silicon film 49 is ± 20%, and the breakdown voltage or cutoff frequency of the bipolar transistor fluctuates due to the variation of the sheet resistance.

In the npn-type bipolar transistor having the third structure, as shown in FIG. 32, when the polycrystalline silicon film 61 is etched back, the surface of the semiconductor substrate 55 in the emitter opening 60 is cut off. Occurs.

An object of the present invention is to provide a technique capable of realizing a semiconductor integrated circuit device having a high-performance bipolar transistor.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0030]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) In the semiconductor integrated circuit device of the present invention, the intrinsic base region has a bipolar transistor connected to the base extraction electrode via the graft base region, and the base extraction electrode has an emitter opening. An insulating film is provided between the base extraction electrode and the active region of the silicon substrate, and has a thickness of 10 nm or less in contact with the active region of the silicon substrate exposed at the emitter opening and the surface of the base extraction electrode. An epitaxial layer is provided, an intrinsic base region is provided in a part of the active region of the silicon substrate in contact with the selective epitaxial layer,
The above-mentioned graft base region is constituted by a first graft base region formed in the active region of the silicon substrate around the intrinsic base region and a second graft base region formed in a part of the selective epitaxial layer. is there.

(2) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the method of manufacturing a bipolar transistor according to the above (1), first, an insulating film for element isolation is formed in an element isolation region of a silicon substrate. A first silicon oxide film and a polycrystalline silicon film are sequentially deposited on a silicon substrate, and then the polycrystalline silicon film is etched using a resist pattern as a mask to form a base lead electrode formed of the polycrystalline silicon film. . Next, after depositing a second silicon oxide film on the silicon substrate, the first silicon oxide film is used as a stop film, and a polycrystalline film forming the second silicon oxide film and the base lead electrode using the resist pattern as a mask. The silicon film is sequentially etched by dry etching to form an emitter opening.
Next, the exposed first silicon oxide film is removed by wet etching. Next, the surface of the silicon substrate exposed at the emitter opening and the surface of the base extraction electrode are formed by epitaxial growth technique.
After growing a selective epitaxial layer having a thickness of sub-nm or less, impurities are introduced into the silicon substrate through the emitter opening, and then the silicon substrate is subjected to a heat treatment, so that an intrinsic base region is formed in a part of the active region of the silicon substrate. Forming a first graft base region in the active region of the silicon substrate around the intrinsic base region by diffusing impurities from the polycrystalline silicon film forming the base extraction electrode into the silicon substrate and the selective epitaxial layer; A second graft base region is formed in a part of the selective epitaxial layer.

According to the above means, when forming the emitter opening, the second silicon oxide film is used as the stop film to form the second opening.
After the silicon oxide film and the polycrystalline silicon film are sequentially processed by dry etching, the first silicon oxide film is removed by wet etching, so that the surface of the silicon substrate is hardly shaved. As a result, the distance between the intrinsic base region and the base extraction electrode can be kept short and constant, so that the base resistance does not vary and always has a low resistance value.

Further, since the graft base region is formed in a self-aligned manner, the area of the graft base region can be set regardless of the alignment accuracy of the lithography technique, and the parasitic region between the collector region and the base region can be set. Resistance can be reduced. Further, since the first silicon oxide film is formed between the base extraction electrode and the silicon substrate, the range in which impurities diffuse from the polycrystalline silicon film forming the base extraction electrode is narrow, and the collector region and the base region And the parasitic capacitance between them can be kept low. Furthermore, the parasitic capacitance between the collector region and the base region is the difference between the parasitic capacitance between the base lead-out electrode and the silicon substrate via the first silicon oxide film and the junction capacitance between the collector region and the base region. Since the value is approximated to the series value, the parasitic capacitance is smaller than the conventional parasitic capacitance between the collector region and the base region where the first silicon oxide film is not provided. Therefore, the delay time can be reduced by reducing the base resistance r _{bb ′} and the parasitic resistance C _TC between the collector region and the base region.

Further, since the selective epitaxial layer is extremely thin, the film quality of the selective epitaxial layer does not affect the yield or circuit operation of the bipolar transistor.

[0036]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows np according to an embodiment of the present invention.
SOI (Sili) showing a part of an n-type bipolar transistor
FIG. 3 is a cross-sectional view of a main part of a (con on insulator) substrate. The SOI substrate is composed of a silicon layer provided on a supporting substrate via a buried oxide film. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

As shown in FIG. 1, a field insulating film 3 is formed on a main surface of an epitaxial layer 2 provided on a silicon layer 1, and an active region of the epitaxial layer 2 is defined by the field insulating film 3. Have been.

A silicon oxide film 4 having a thickness of about 10 nm formed on an active region formed by epitaxial layer 2 and a polycrystalline silicon film to which p-type impurities, for example, boron (B) are added. The base extraction electrode 5 has an emitter opening 6 formed therein. A selective epitaxial layer 7 is formed on the surface of the base extraction electrode 5 and the epitaxial layer 1 exposed by providing the emitter opening 6. The thickness of the selective epitaxial layer 7 is about 5 nm.

The emitter region 8 is formed on the surface of the active region constituted by the epitaxial layer 2 and on a part of the selective epitaxial layer 7. On the emitter region 8, polycrystalline silicon doped with an n-type impurity is formed. An emitter electrode 9 composed of a film is formed. In the emitter region 8, the n-type impurity added to the emitter electrode 9 is selectively epitaxial layer 7 and epitaxial layer 2.
Is formed by diffusion.

The intrinsic base region 10 is formed in the active region constituted by the epitaxial layer 2 surrounding the emitter region 8, and the base is drawn out through the first graft base region 11a and the second graft base region 11b. It is connected to the electrode 5.

The first graft base region 11a is provided in the epitaxial layer 2 between the intrinsic base region 10 and the base lead electrode 5, and the first graft base region 11a
Is formed by diffusion of the p-type impurity added to the semiconductor. Second
Of the base extraction electrode 5
The p-type impurity added to the base extraction electrode 5 is diffused and formed in the selective epitaxial layer 7 provided on the side wall of the first and the first graft base region 11a.

In order to insulate between the emitter electrode 9 and the base extraction electrode 5, a silicon oxide film 12 is formed on the base extraction electrode 5, and a gap between the emitter electrode 9 and the second graft base region 11 b is provided. To insulate the emitter electrode 9 from the second graft base region 11b.
, An insulating film 13, for example, a silicon oxide film is formed.

Next, a method of manufacturing the npn-type bipolar transistor formed on the SOI substrate according to the first embodiment will be described with reference to FIGS.

First, as shown in FIG. 2, a predetermined region of the p-type silicon layer 1 formed on the support substrate 14 with the first buried oxide film 15 interposed therebetween is accelerated to 3 × with an acceleration energy of, for example, 100 keV. Antimony (Sb) ions of about 10 ¹⁵ cm ^-2 are implanted. Next, 120
By performing a heat treatment at 0 ° C., the crystallinity of the silicon layer 1 is recovered, and an n-type collector burying layer 16 is formed.

Next, as shown in FIG. 3, an n-type epitaxial layer 2 having a thickness of, for example, about 0.5 μm is grown on the silicon layer 1 by using an epitaxial growth technique. Next, after forming a groove 17 of about 0.4 μm in the epitaxial layer 2 using a dry etching technique, a silicon oxide film (not shown) is deposited on the SOI substrate,
A second buried oxide film 18 is formed in the groove 17 by flattening the surface of the silicon oxide film by, for example, a chemical mechanical polishing (CMP) method.

Next, as shown in FIG. 4, an n-type impurity such as phosphorus (P) is
1 × 10 ¹⁶ cm at 80 keV acceleration energy
After implanting about ⁻² , the SOI substrate is subjected to a heat treatment at 950 ° C. to form a collector pulling diffusion layer 19.

Next, as shown in FIG. 5, a deep groove 20 penetrating through the second buried oxide film 18, the epitaxial layer 2 and the silicon layer 1 and reaching the first buried oxide film 15 is formed by a dry etching technique. It is formed using. Thereafter, a silicon oxide film 21 is deposited on the SOI substrate by a chemical vapor deposition (CVD) method, and then the surface of the silicon oxide film 21 is planarized by, for example, a CMP method. A silicon oxide film 21 is buried in the deep groove 20.

At this time, the voids 22 are generated inside the deep groove 20, but do not affect the subsequent manufacturing process and do not affect the operation characteristics of the bipolar transistor.

Next, as shown in FIG. 6, at a low temperature of about 700 ° C. using organic silane as a source gas on the SOI substrate,
A silicon oxide film 23 of about 10 nm is deposited. Since the silicon oxide film 23 is deposited at a low temperature, the density of the silicon oxide film is lower than that of the silicon oxide film formed on the single crystal silicon by the thermal oxidation process, and the wet etching is about ten times that of the silicon oxide film formed by the thermal oxidation process. Have speed.

Next, after depositing a 200 nm polycrystalline silicon film 24 on the SOI substrate by the CVD method, a p-type impurity, for example, B ion is added to the polycrystalline silicon film 24 at about 1 × 10 ¹⁶ cm ^−2. Then, heat treatment is performed on the SOI substrate at 570 ° C. for 20 hours. Thereafter, the polycrystalline silicon film 24 is
Is etched.

Next, as shown in FIG. 7, an insulating film, for example, a silicon oxide film 25 is deposited on the SOI substrate. At this time, since the silicon oxide film 25 is deposited at a high temperature of about 800 ° C. using inorganic silane as a source gas, the silicon oxide film 25 has a high density.
It has a wet etching rate about 1.7 times that of a silicon oxide film formed on single crystal silicon by thermal oxidation.

Next, using the resist pattern as a mask, the silicon oxide film 25 and the polycrystalline silicon film 24 are sequentially etched to form the emitter openings 6. The processed polycrystalline silicon film 24 forms the base extraction electrode 5.

Next, as shown in FIG. 8, a part of the exposed silicon oxide film 23 is removed by wet etching. At this time, since there is a difference between the wet etching rate of the silicon oxide film 23 and the wet etching rate of the silicon oxide film 25, the silicon oxide film 25 is not removed.

Further, when the emitter opening 6 is formed in the silicon oxide film 25 and the polycrystalline silicon film 24, the silicon oxide film 23 serves as a stop film for etching.
The silicon oxide film 23 is formed by wet etching.
Is removed, so that the surface of the epitaxial layer 2 is hardly shaved.

Thereafter, the exposed epitaxial layer 2
A selective epitaxial layer 7 having a thickness of about 5 nm is grown on the surface of the base extraction electrode 5. Although a part of the silicon oxide film 23 under the base extraction electrode 5 is etched by the above wet etching to form a gap of about 10 nm, the growth of silicon from the base extraction electrode 5 and the epitaxial layer 2 causes the base extraction electrode 5 and the The epitaxial layer 2 is connected.

Next, as shown in FIG. 9, a p-type impurity
For example, after implanting B ions at about 1 × 10 ¹⁴ cm ⁻² to introduce shallow p-type impurities into the epitaxial layer 2,
By subjecting the I-substrate to heat treatment for a short time, an intrinsic base region 10 composed of p-type impurities is formed. While this heat treatment is performed on the SOI substrate, the polycrystalline silicon film 24 forming the base extraction electrode 5 also
Type impurity diffuses into the epitaxial layer 2 and the selective epitaxial layer 7 to form the first graft base region 11a.
And the second graft base region 11b is formed.

Next, as shown in FIG. 10, after a silicon oxide film 26 and a polycrystalline silicon film 27 to which P is added are sequentially deposited on the SOI substrate by the CVD method, the polycrystalline silicon film 27 is formed, for example, by RIE. (Reactive Ion Etchi
ng) to form sidewall spacers made of the polycrystalline silicon film 27 inside the emitter openings 6. The thickness of the silicon oxide film 26 is about 50 nm, and the thickness of the polycrystalline silicon film 27 is about 100 nm.

Next, after the silicon oxide film 26 is removed by about 60 nm by wet etching, a p-type impurity, for example, P-added about 200 n is added to the SOI substrate.
Then, a polysilicon film 28 having a thickness of m is deposited, and then the polysilicon film 28 is etched using the resist pattern as a mask. The processed polycrystalline silicon film 28
An emitter electrode 9 is formed.

Thereafter, the SOI substrate is subjected to a heat treatment at 900 ° C. for a short time to diffuse the p-type impurity added to the polycrystalline silicon film 28 into the selective epitaxial layer 7 and the epitaxial layer 2, thereby forming an n-type emitter. Region 8 is formed.

Next, as shown in FIG. 11, the silicon oxide film 25 and the silicon oxide film 23 are sequentially etched by using a dry etching technique, and a part of the surface of the base extraction electrode 5 and the surface of the collector pulling diffusion layer 19 are formed. To expose. Thereafter, a titanium (Ti) film is deposited on the SOI substrate, and then a heat treatment is performed on the SOI substrate, so that the surface of each of the emitter electrode 9, the base extraction electrode 5, and the collector pulling diffusion layer 19 is selectively formed. A low-resistance Ti silicide layer 29 is formed.

Next, as shown in FIG. 12, after thickly depositing the interlayer insulating film 30 on the SOI substrate, the interlayer insulating film 30 is etched using the resist pattern as a mask, so that the collector pull-up diffusion layer 19 is formed. A contact hole 31a is formed, a contact hole 31b is formed on the base extraction electrode 5, and a contact hole 31c is formed on the emitter electrode 9.

Thereafter, the contact holes 31a, 3a
A first metal film 32a, for example, a tungsten film or an aluminum alloy film is embedded in 1b and 31c. After this, S
A second metal film 32b is deposited on the OI substrate, and then the second metal film 32b is
By etching b, a wiring layer composed of the first metal film 32a and the second metal film 32b is formed, and the npn-type bipolar transistor of the present embodiment is completed.

In this embodiment, a silicon oxide film is used as an insulating film provided on polycrystalline silicon film 24, but a silicon nitride film may be used.

Further, an SOI substrate in which the silicon layer 1 is provided on the support substrate 14 with the first buried oxide film 15 interposed therebetween is used as the substrate for forming the semiconductor integrated circuit device.
A semiconductor substrate formed of single-crystal silicon of the type may be used.

As described above, according to the present embodiment, when forming the emitter opening 6, first, the silicon oxide film 23 is formed.
Is used as a stop film, the silicon oxide film 25 and the polycrystalline silicon film 24 are sequentially processed by dry etching using a resist pattern as a mask, and then the silicon oxide film 23 is removed by wet etching. Is less likely to be scraped. As a result, the distance between the intrinsic base region 10 and the base extraction electrode 5 can be kept short and constant, so that the base resistance does not vary and always has a low resistance value.

FIG. 13A is a graph showing the relationship between the base resistance r _{bb ′} and the distance of the connecting portion. FIG.
As shown in (b), the base resistance r _{bb ′} is composed of components R ₁ , R ₂ , R ₃ of the base electrode and components R ₄ , R _{5 of the} connecting portion
And the component _Rb of the intrinsic base region.
The sheet resistance of the base electrode is 2Ω / □, the sheet resistance of the connecting part is 3.5kΩ / □, and the sheet resistance of the intrinsic base region is
It was 4.5 kΩ / □. Further, the diffusion depth of the p-type impurity from the polycrystalline silicon film forming the base extraction electrode is 45 nm, the lateral diffusion of the n-type impurity from the polycrystalline silicon film forming the emitter electrode 5 is 25 nm, and the emitter opening is formed. The lateral length of the insulating film provided inside the
m.

In the conventional bipolar transistor shown in FIG. 20, when the semiconductor substrate 33 is scraped by 80 nm, the distance between the connecting portions becomes 85 nm, and FIG.
From (a), the base resistance r _{bb ′} becomes 430Ω.

On the other hand, in the present embodiment, since the shaving amount of the epitaxial layer 2 is the same as the thickness of the selective epitaxial layer 7, the shaving amount of the epitaxial layer 2 is reduced to 5 nm of the thickness of the selective epitaxial layer 7. Assuming a variation of 6 nm in consideration of the variation, the base resistance r
_{bb '} becomes 260Ω.

Further, since the graft base region is formed in a self-aligned manner, the area of the graft base region can be set regardless of the alignment accuracy of the lithography technique, and the parasitic region between the collector region and the base region can be set. Resistance can be reduced.

FIG. 14A is a graph showing the relationship between the parasitic capacitance C _TC between the collector region and the base region and the margin between the active region and the emitter opening.
FIG. 3B is a plan view of the bipolar transistor for explaining a margin between the active region and the emitter opening.

In the conventional bipolar transistor, a margin between the active region and the emitter opening is required to be 0.25 μm from the alignment accuracy of the lithography technique in order not to generate a region where the base electrode does not contact the active region. Therefore, the parasitic capacitance is about 1.1 fF.

On the other hand, in the present embodiment, the distance between the base extraction electrode 5 and the epitaxial layer 2 is about 10
Since silicon oxide film 4 of nm is formed, the range of diffusion of p-type impurities from polycrystalline silicon film 24 forming base extraction electrode 5 is narrower than that of the conventional bipolar transistor shown in FIG. As a result, the parasitic capacitance between the collector region and the base region is reduced. Further, the parasitic capacitance between the collector region and the base region is approximated to the series value of the parasitic capacitance between the base extraction electrode 5 and the epitaxial layer 2 and the junction capacitance between the collector region and the base region. Base extraction electrode 5 and epitaxial layer 2 through silicon oxide film 4 of about 10 nm
Is 2.2 fF, the parasitic capacitance between the collector region and the base region in the present embodiment is approximately 0.7 fF.
fF.

FIG. 15 shows an ECL (Emitter Coupled Logi).
c) Simulation results of circuit delay time are shown. FIG. 15A shows a simulation result of the delay time of the conventional bipolar transistor shown in FIG.
FIG. 15B is a simulation result of the delay time of the bipolar transistor according to the present embodiment. When the cutoff frequency f _TMAX of, for example, 40 GHz is realized by reducing the base resistance r _{bb ′} and the parasitic resistance C _TC between the collector region and the base region, the delay time, which is 26 ps in the conventional bipolar transistor, is reduced to 20 ps Can be shortened.

The selective epitaxial layer 7 has a thickness of about 5 nm.
Therefore, the film quality of the selective epitaxial layer 7 does not affect the yield or circuit operation of the bipolar transistor.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above embodiment, the case where the present invention is applied to an npn-type bipolar transistor has been described. However, the present invention can be applied to a pnp-type bipolar transistor.

[0078]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the base resistance of the bipolar transistor and the parasitic capacitance between the collector region and the base region can be reduced, so that the delay time can be shortened and the high-performance bipolar transistor can operate quickly. Can be realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part of an SOI substrate showing a bipolar transistor according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a bipolar transistor according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a bipolar transistor according to an embodiment of the present invention.

FIG. 4 is a fragmentary cross-sectional view of the SOI substrate, illustrating the method for manufacturing the bipolar transistor according to one embodiment of the present invention;

FIG. 5 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a bipolar transistor according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a bipolar transistor according to an embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of the SOI substrate, illustrating the method for manufacturing the bipolar transistor according to one embodiment of the present invention;

FIG. 8 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a bipolar transistor according to an embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view of the SOI substrate, illustrating the method for manufacturing the bipolar transistor according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the SOI substrate, illustrating the method for manufacturing the bipolar transistor according to one embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the SOI substrate, illustrating the method for manufacturing the bipolar transistor according to one embodiment of the present invention;

FIG. 12 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a bipolar transistor according to an embodiment of the present invention.

13A is a graph showing a relationship between a base resistance and a distance of a connecting portion between an emitter region and a base extraction electrode, and FIG. 13B is a circuit diagram showing components of the base resistance.

14A is a graph showing a relationship between a parasitic capacitance between a collector region and a base region and a margin between an active region and an emitter opening, and FIG. 14B is a graph showing an active region and an emitter. FIG. 3 is a plan view of a bipolar transistor for explaining a margin between the opening and an opening.

FIG. 15A is a graph showing a simulation result of the delay time of the conventional ECL circuit, and FIG. 15B is a graph showing a simulation result of the delay time of the ECL circuit of the present embodiment.

FIG. 16 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a conventional bipolar transistor (first structure).

FIG. 17 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a conventional bipolar transistor (first structure).

FIG. 18 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a conventional bipolar transistor (first structure).

FIG. 19 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a conventional bipolar transistor (first structure).

FIG. 20 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a conventional bipolar transistor (first structure).

FIG. 21 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a conventional bipolar transistor (second structure).

FIG. 22 is a cross-sectional view of a main part of an SOI substrate, showing a method for manufacturing a conventional bipolar transistor (second structure).

FIG. 23 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a conventional bipolar transistor (second structure).

FIG. 24 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a conventional bipolar transistor (second structure).

FIG. 25 is a cross-sectional view of a main part of an SOI substrate, showing a method for manufacturing a conventional bipolar transistor (second structure).

FIG. 26 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a conventional bipolar transistor (second structure).

FIG. 27 is a cross-sectional view of a main part of an SOI substrate, showing a method for manufacturing a conventional bipolar transistor (second structure).

FIG. 28 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a conventional bipolar transistor (third structure).

FIG. 29 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a conventional bipolar transistor (third structure).

FIG. 30 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a conventional bipolar transistor (third structure).

FIG. 31 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a conventional bipolar transistor (third structure).

FIG. 32 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a conventional bipolar transistor (third structure).

FIG. 33 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a conventional bipolar transistor (third structure).

FIG. 34 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a conventional bipolar transistor (third structure).

FIG. 35 is a cross-sectional view of a main part of an SOI substrate, illustrating a method for manufacturing a conventional bipolar transistor (third structure).

[Explanation of symbols]

 Reference Signs List 1 silicon layer 2 epitaxial layer 3 field insulating film 4 silicon oxide film 5 base extraction electrode 6 emitter opening 7 selective epitaxial layer 8 emitter region 9 emitter electrode 10 intrinsic base region 11a first graft base region 11b second graft base region Reference Signs List 12 silicon oxide film 13 insulating film 14 support substrate 15 first buried oxide film 16 collector buried layer 17 groove 18 second buried oxide film 19 collector pulling diffusion layer 20 deep groove 21 silicon oxide film 22 void 23 silicon oxide film 24 many Crystalline silicon film 25 silicon oxide film 26 silicon oxide film 27 polycrystalline silicon film 28 polycrystalline silicon film 29 titanium silicide layer 30 interlayer insulating film 31a contact hole 31b contact hole 31c contact hole L 32a Metal film 32b Metal film 33 Semiconductor substrate 34 Field insulating film 35 Base extraction electrode 36 Silicon oxide film 37 Emitter opening 38 Intrinsic base region 39 Graft base region 40 Sidewall spacer 41 Emitter electrode 42 Emitter region 43 Semiconductor substrate 44 Field insulation Film 45 silicon oxide film 46 base extraction electrode 47 silicon oxide film 48 emitter opening 49 single crystal silicon film 50 intrinsic base region 51 graft base region 52 sidewall spacer 53 emitter electrode 54 emitter region 55 semiconductor substrate 56 field insulating film 57 silicon oxide Film 58 Base extraction electrode 59 Silicon oxide film 60 Emitter opening 61 Polycrystalline silicon film 62 Intrinsic base region 63 Graft base electrode 64 De wall spacer 65 emitter electrode 66 emitter region

Claims (9)

[Claims] 1. A semiconductor integrated circuit device having a bipolar transistor in which an intrinsic base region is connected to a base extraction electrode via a graft base region, wherein the base extraction electrode is provided with an emitter opening, An insulating film is provided between the extraction electrode and the active region of the silicon substrate; a selective epitaxial layer is provided in contact with the active region of the silicon substrate in the emitter opening and the surface of the base extraction electrode; The intrinsic base region is provided in a part of the active region of the silicon substrate in contact with a layer, and a first graft base region formed in the active region of the silicon substrate around the intrinsic base region; The graph according to the second graft base region formed in part of the layer; A semiconductor integrated circuit device comprising a base region. 2. The semiconductor integrated circuit device according to claim 1, wherein an emitter region is provided in another part of said selective epitaxial layer and an active region of said silicon substrate in contact with another part of said selective epitaxial layer. And a semiconductor integrated circuit device. 3. The semiconductor integrated circuit device according to claim 1, wherein said first graft base region is not formed in an active region of said silicon substrate under said insulating film. Circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein at least said selective epitaxial layer in contact with an active region of said silicon substrate is made of single crystal silicon. 5. The semiconductor integrated circuit device according to claim 1, wherein said selective epitaxial layer has a thickness of 10 nm or less. 6. The semiconductor integrated circuit device according to claim 1, wherein said insulating film has a thickness of 20 nm or less. 7. After forming an element isolation insulating film in an element isolation region of a silicon substrate, a first layer is formed on the silicon substrate.
Sequentially depositing an insulating film and a polycrystalline silicon film, and then etching the polycrystalline silicon film using a resist pattern as a mask to form a base lead electrode formed by the polycrystalline silicon film, (b) After depositing a second insulating film on the silicon substrate, using the first insulating film as a stop film, and using the resist pattern as a mask, the polycrystal constituting the second insulating film and the base lead-out electrode Etch the silicon film sequentially
Forming an emitter opening, (c) removing the exposed first insulating film by wet etching, and (d) exposing at the emitter opening by an epitaxial growth technique. Growing a selective epitaxial layer on the surface of the silicon substrate and the base extraction electrode; and (e) introducing an impurity into the silicon substrate through the emitter opening, and then performing a heat treatment on the silicon substrate. Forming an intrinsic base region in a part of the active region of the silicon substrate; diffusing impurities from the polycrystalline silicon film forming the base extraction electrode into the silicon substrate and the selective epitaxial layer; Forming a first graft base region in an active region of the silicon substrate; The method of manufacturing a semiconductor integrated circuit device characterized by a step of forming a second graft base region in a part of the Kisharu layer. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein said second insulating film is a silicon oxide film or a silicon nitride film. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein the first insulating film is a silicon oxide film deposited at a temperature of 750 ° C. or less using organosilane as a source gas. The method for manufacturing a semiconductor integrated circuit device, wherein the second insulating film is a silicon oxide film deposited at a temperature of 750 ° C. or higher using inorganic silane as a raw material.