JP3196716B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device including a self-aligned bipolar transistor.
In particular, it is possible to manufacture a semiconductor device having excellent high-frequency characteristics with no variation in the base width due to process variations .
Construction method .

[0002]

2. Description of the Related Art A conventional semiconductor device of this type (hereinafter referred to as "conventional example") proposed in Japanese Patent Application Laid-Open No. 7-307347 will be described with reference to FIGS. In addition,
FIG. 5 is a cross-sectional view illustrating the structure of a conventional semiconductor device, and FIGS. 6 and 7 are views illustrating a method of manufacturing the conventional semiconductor device. It is sectional drawing.

First, the structure of a conventional semiconductor device will be described. In the conventional example, as shown in FIG. 5, an N ⁻ -type epitaxial layer (see FIG. 5) surrounded by a field oxide film 104 for element isolation. (Collector layer) 103
A silicon oxide film 106 having an opening in a predetermined region of the epitaxial layer 103; a P ⁺ -type base electrode supported by the silicon oxide film 106 and having a tip protruding into the opening in a cantilever shape. A polycrystalline silicon layer 107 for use; a P ^{+ type} external base layer 11 formed in a protruding portion of the polycrystalline silicon layer 107 and a surface region of the N ⁻ type epitaxial layer 103.
A P-type epitaxial base layer 111 having substantially the same thickness as the silicon oxide film 106 formed by epitaxial growth on the N ⁻ -type epitaxial layer 103; And an N ⁺ -type emitter layer 114 formed on the surface of the epitaxial base layer 111.

In FIG. 5, reference numeral 101 denotes a P ^- type silicon substrate;
2 is an N ⁺ type buried layer, 105 is an N ⁺ type collector extraction layer,
108 is a silicon nitride film, 109 is a first side wall, 11
2 is a second side wall, and 113 is a polycrystalline silicon layer for an N ⁺ type emitter electrode.

That is, the conventional semiconductor device is composed of (A) P
(B) P ⁺ type polycrystalline silicon for base electrode, in which a cavity formed below polycrystalline silicon layer 107 for ⁺ type base electrode is filled with polycrystalline silicon formed separately from the base epitaxial layer. It is characterized in that the cavity formed below the layer 107 is formed in a self-aligned manner with respect to the emitter opening formed in the polycrystalline silicon layer 107.
The features of (A) and (B) can reduce the base resistance, prevent facets from entering the edge of the base epitaxial layer, and realize miniaturization by self-alignment technology. This realizes a semiconductor device having excellent characteristics.

Next, a method of manufacturing the conventional semiconductor device will be described with reference to FIGS. In addition,
FIG. 6 is a cross-sectional view of a main part of a manufacturing method of “a conventional method of manufacturing a semiconductor device” including steps A to C, and FIG.
FIG. 7 is an essential part cross-sectional view of a manufacturing step in steps D to F following step C in FIG. 6.

First, as shown in step A of FIG.
Arsenic or antimony is ion-implanted into a P ^- type silicon substrate 101 having an impurity concentration of 1 to 5 × 10 ²⁰ cm ^-3 and a thickness of
An N ⁺ -type buried layer 102 of 1 to ² μm is formed, and an impurity concentration of 5 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁶ cm ⁻³ and a thickness of 1.0 to 1.8 are formed thereon.
A μm-type N ⁻ -type epitaxial layer (collector layer) 103 is formed. For further element isolation, a well-known LOCO (LOCO
A field oxide film 104 is formed by an S: Local Oxidation of Silicon (Silicon) technique, and then an N ⁺ -type collector lead-out layer 105 (see FIG. 5 described above) is formed by partial phosphorus diffusion.

Thereafter, a silicon oxide film 106 having a thickness of 40 to 140 nm is formed on the entire surface. Next, after growing a polycrystalline silicon layer 107 for a P ⁺ type base electrode and a silicon nitride film 108, photolithography and dry etching are applied to the nitride film 108 and the polycrystalline silicon layer 107 to form an N. ^- field oxide type epitaxial layer 103
By 104, an emitter opening is formed in the center of the prescribed region (the region where the base is formed thereafter) (see step A in FIG. 6).

Next, as shown in step B of FIG. 6, a silicon nitride film is deposited on the entire surface, and this is etched back by anisotropic dry etching to form a first film on the side wall of the emitter opening.
Is formed. Subsequently, the silicon oxide film 106 at the emitter opening is removed by wet etching. Further, by continuing the etching for a predetermined time, the silicon oxide film 106 around the emitter opening is formed.
At the desired depth from the edge of the opening. Thus, a donut-shaped cavity is formed below the P ⁺ -type base electrode polycrystalline silicon layer 107. As a result of this wet etching, the P ⁺
The surface of N ⁻ -type epitaxial layer 103 is exposed below the bottom surface of polycrystalline silicon layer 107 for the base electrode (→ step B in FIG. 6).
reference).

Next, a polycrystalline silicon layer 110 is grown on the entire surface. This polycrystalline silicon layer 110 is a silicon oxide film 1
This is for embedding in a cavity around the emitter opening formed by removing 06 (→ see step C in FIG. 6).

Subsequently, as shown in a step D of FIG. 7, the polycrystalline silicon layer 110 is left only in the cavity and the other polycrystalline silicon layer 110 is removed by isotropic dry etching.
At this time, in the dry etching, the polycrystalline silicon layer 110
N ^- type epitaxial layer 103 needs to be completely removed
Overetching is performed so as to dig about 3 to 9 nm. Thereafter, heat treatment is performed to diffuse impurities from the P ⁺ -type base electrode polycrystalline silicon layer 107, thereby increasing the concentration and the resistance of the remaining polycrystalline silicon layer 110 (see FIG. 7).
Step D).

Next, as shown in step E of FIG. 7, a P-type epitaxial base layer 111 is selectively formed on a portion where the surface of the N ⁻ -type epitaxial layer 103 is exposed by using a UHV / CVD method or a molecular beam epitaxial method. Formed.

Subsequently, as shown in a step F of FIG. 7, a second sidewall 112 is formed by depositing a silicon oxide film and etching back the silicon oxide film, and thereafter, a polycrystalline silicon layer 113 for an N ⁺ type emitter electrode is formed. Form. Thereafter, a heat treatment is performed to explain with reference to FIG. 5 described above. An N ⁺ -type emitter layer 114 is formed by impurity diffusion from the N ⁺ -type emitter electrode polysilicon layer 113, and at the same time, a polycrystalline silicon layer is formed. P ^{+ type} external base layer 115 by impurity diffusion from 110
Is formed to obtain the conventional semiconductor device shown in FIG.

[0014]

The above conventional example
(Conventional semiconductor device) forms a polycrystalline silicon layer connecting the base electrode polycrystalline silicon layer and the base layer during a period from the formation of the emitter contact to the formation of the polycrystalline silicon for the emitter electrode. The polycrystalline silicon layer is left only in the cavity by etching (see the above-mentioned “polycrystalline silicon layer 110” in step C of FIG. 6 and step D of FIG. 7), and further, a base layer is formed after forming an oxide film. Like that. For this reason, in the conventional example, there is a possibility that the base width may be influenced by the variation in the etching amount in the etching step, and as a result, there is a problem that the high frequency characteristics of the semiconductor device vary.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems in the prior art, and an object (problem) of the present invention is to suppress a change in a base width due to a variation in an etching amount in an etching process, and to reduce a variation in the base width. An object of the present invention is to provide a method of manufacturing a semiconductor device having excellent high frequency characteristics.

[0016]

According to the manufacturing method of the present invention ,
The semiconductor device to be manufactured includes: a polycrystalline silicon layer for a base electrode of the second conductivity type supported by the element isolation region and having an emitter opening above the buried layer; and in a region of the collector layer of the first conductivity type and A second conductive type external base layer diffused between the intrinsic base layer and the base electrode polycrystalline silicon layer, and a method of manufacturing a semiconductor device according to the present invention. A step of forming a buried layer of the first conductivity type and a step of forming an intrinsic base layer of the second conductivity type during a period from the formation of the emitter contact to the formation of the emitter layer. And forming a sidewall on the side wall of the emitter opening. Since the semiconductor device can be realized without passing through an etching process such as spacing varies with, to suppress a change in base width due to variations of the etching amount in the "etching process, with a no excellent high-frequency characteristics variation semiconductor
To provide a method for manufacturing an apparatus ".

That is, it is manufactured by the manufacturing method according to the present invention.
A first conductivity type collector layer surrounded by an element isolation region; a buried layer formed in or on a surface region of the collector layer; A polycrystalline silicon layer for a base electrode of a second conductivity type which is supported and has an opening above the buried layer; an intrinsic base layer formed at a predetermined depth from the surface of the collector layer above the buried layer; An emitter layer formed in or on the surface region of the intrinsic base layer; and diffused and formed in the region of the collector layer and between the intrinsic base layer and the base electrode polycrystalline silicon layer. a second conductivity type extrinsic base layer has at least a "
It is characterized by: The second conductive type base electrode polycrystalline silicon layer is directly formed on the element isolation region and the second conductive type external base layer .

The method of manufacturing a semiconductor device according to the present invention comprises the steps of: (1) forming a first conductive type polycrystalline silicon layer on a first conductive type collector layer surrounded by an element isolation region; (2) selectively etching the first-type first insulating film and the base-electrode polycrystalline silicon layer so as to be located substantially at the center of the collector layer; (3) a step of introducing a first conductivity type impurity into the collector layer exposed by the emitter opening to form a first conductivity type buried layer; A second type of first insulating film having a different etching property from that of the first type of first insulating film is deposited, and a second conductivity type impurity is introduced through the emitter opening to form a second conductive type impurity on the collector layer. Forming an intrinsic base layer of the second conductivity type; A second insulating film of the same type as the first insulating film of the second type and a second insulating film of the same type as the first insulating film of the first type are formed in this order, and this is etched back to form the emitter opening. Forming a sidewall on the side wall; and (6) introducing a first conductivity type impurity into the intrinsic base layer;
And a step of forming an emitter layer through a subsequent heat treatment. (Claim 1) is the gist (items specifying the invention).

Further, in the method for manufacturing a semiconductor device according to the present invention, in the manufacturing method, a second conductivity type impurity diffuses from the polycrystalline silicon layer for the base electrode into the collector layer during the heat treatment. An external base layer of the second conductivity type is formed thereon (claim 2).

[0020]

Next, a semiconductor device according to the present invention will be described .
The present invention will be specifically described with reference to an embodiment of a manufacturing method.However, the present invention is not limited only to the following embodiment (example), and for example, the conductivity type and impurities to be ion-implanted are arbitrary. And various modifications and changes are possible within the scope of the gist (items specifying the invention) of the method of manufacturing a semiconductor device according to the present invention described above.

(Embodiment) FIG. 1 shows a semiconductor device manufactured by a manufacturing method according to the present invention.
FIG. 4 is a diagram showing a reference example , and is a cross-sectional view illustrating a structure of a semiconductor device of the reference example . Also, FIG. 2 is a diagram illustrating an embodiment of a method of manufacturing a semiconductor device of the present embodiment, a manufacturing process sequence sectional views comprises the step A~ Step D,
FIG. 3 is a sectional view in the order of the manufacturing process including steps E to G following step D in FIG.

[0022] First, to describe the structure of the semiconductor device of the present embodiment, the present reference example, as shown in FIG. 1, surrounded by a first oxide film 3 for element isolation on · N ⁺ -type silicon substrate 1 N ^- type collector layer (first
A collector layer) second conductivity type, - N ^- and N ⁺ -type buried layer 7 formed on a surface region or surface of the type collector layer 2, is supported by the-first oxide film 3 N ⁺ -type buried layer 7 A polycrystalline silicon layer 4 for a base electrode of the second conductivity type having an opening above the N ^- type collector layer 2 above the N ⁺ -type buried layer 7 at a predetermined depth from the surface thereof. An emitter layer 12 formed in or on the surface region of the intrinsic base layer 8; an emitter layer 12 in the region of the N ⁻ -type collector layer 2 and the polycrystalline silicon layer 4 for the base electrode. P ⁺ type external base layer (second conductive type external base layer) formed by diffusion between
And a structure having:

As described above, in the present embodiment , the first oxide film 3
The second conductive type base electrode polycrystalline silicon layer 4 is directly formed on the (first oxide film 3 for element isolation) and the P ⁺ type external base layer (second conductive type external base layer) 14. The structure is. In FIG. 1, 5 is a first nitride film (a first type of first insulating film), 9 is a second oxide film (a second type of first insulating film),
10 is a third oxide film (a second type of second insulating film), 11 is a second nitride film (a first type of second insulating film), 13 is a polycrystalline silicon layer for an emitter electrode, 15 is a base electrode, 16 Indicates an emitter electrode.

That is, the semiconductor device of the present embodiment includes: a base electrode polycrystalline silicon layer 4 supported by the first oxide film 3 and having an emitter opening above the N ⁺ type buried layer 7.
A structure having a P ⁺ -type external base layer 14 formed by diffusion in the region of the N ⁻ -type collector layer 2 and between the intrinsic base layer 8 and the base-electrode polycrystalline silicon layer 4. It is characterized by the structure provided (the structure in which the base electrode polycrystalline silicon layer 4 is directly formed on the first oxide film 3 and the P ^{+ type} external base layer 14). A step of forming the N ⁺ -type buried layer 7, a step of forming the intrinsic base layer 8, and a step of forming a sidewall on a side wall of the emitter opening during a period from the formation of the emitter contact to the formation of the emitter layer 12. And at least a manufacturing method having at least a step of changing the base width or the distance between the base surface and the substrate. Suppressing a change in the base width by the variability is obtained by realizing a semiconductor device having a no excellent high-frequency characteristics variation resulting.

Next, a method of manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. First, as shown in step A of FIG. 2, on an N ⁺ type silicon substrate 1,
The epitaxial method, the resistivity 0.5~3Ω · cm N ^-
A collector layer (collector layer of the first conductivity type) 2 is grown to a thickness of 0.5 to 2 μm. Subsequently, a known LOCOS (Local Oxidation of Silicon) is used for element isolation.
The first oxide film (element isolation region) 3 is formed in a region other than the active portion by such a technique.

Next, as shown in step B of FIG. 2, a polycrystalline silicon layer is grown to a thickness of about 1000 to 2000 °, and boron is ion-implanted to reduce the specific resistance, thereby forming a base (of the second conductivity type). An electrode polycrystalline silicon layer 4 is formed. Note that boron may be introduced during the formation of polycrystalline silicon. Subsequently, a first nitride film (first type of first insulating film) 5 is grown on the base electrode polycrystalline silicon layer 4 by about 2000 °.

Next, the first nitride film 5 and the polycrystalline silicon layer 4 for the base electrode are patterned by photolithography and dry etching to form an N-type collector.
An emitter opening is formed at a substantially central portion of the collector layer 2 (a region where the intrinsic base layer is formed thereafter) (see step B in FIG. 2). At this time, since it is necessary to completely remove the polycrystalline silicon layer, over-etching is performed so that the N ⁻ type collector layer (epitaxial layer) 2 is slightly etched, but the amount is about 200 to 300 °.

Next, as shown in step C of FIG. 2, phosphorus (first conductivity type impurity) is ion-implanted on the N ⁻ type collector layer 2 exposed by the emitter opening (first conductivity type impurity). A buried layer (N ⁺ SIC) 7 is formed. The ion implantation is performed at an acceleration energy of, for example, 300 to 400 keV,
The treatment is performed at a dose in the range of × 10 ¹² to 1 × 10 ¹³ cm ⁻² .

Next, as shown in step D of FIG. 2, after removing the photoresist 6, a second oxide film (a second type of first insulating film) 9 having a thickness of about 100 to 500 ° is deposited by thermal oxidation. Then, to form the intrinsic base layer 8, N
^- P-type impurity on the type collector layer 2 (second conductivity type impurity)
BF ²⁺ is ion-implanted. The ion implantation is performed, for example,
1 × 10 ^{13 to} 5 × 10 ¹³ c with acceleration energy of 10 to 30 keV
This is performed at a dose in the range of m- ² . In addition, thickness 100-3
A third oxide film 10 having a thickness of about 00 ° and a second nitride film 11 having a thickness of about 1200 to 2000 ° are sequentially formed.

Thereafter, as shown in step E of FIG. 3, the second nitride film 11, the third oxide film 10 and the second oxide film 9 are etched back by a dry etching process to form sidewalls on the side walls of the emitter openings. Form.

Next, as shown in step F of FIG.
The polycrystalline silicon layer 13 for the emitter electrode of about 2000 ° is formed by the VD method, and arsenic is used to form the emitter layer.
Then, arsenic is driven into the intrinsic base layer 8 by heat treatment. The ion implantation is performed at an acceleration energy of, for example, 60 keV and a dose of about 1 × 10 ¹⁶ cm ⁻² . Also,
At the time of the heat treatment, in the region where the N ⁻ type collector layer 2 is in contact with the base electrode polycrystalline silicon layer 4, the P ⁺ type impurity is diffused from the base electrode polycrystalline silicon layer 4 by boron (diffusion of the second conductivity type). An external base layer 14 is formed.

Thereafter, the polysilicon layer 13 for the emitter electrode is patterned by a photolithography process,
Similarly, the first nitride film 5 is formed by a photolithography process.
Is patterned to form a polycrystalline silicon layer 4 for the base electrode.
Forming a contact hole connecting the substrate and the base electrode.

Subsequently, as shown in a step G of FIG. 3, the base electrode 15 and the emitter electrode 16 are formed by a sputtering method of Al—Cu or the like, and then patterned by a lithography step to obtain the reference example shown in FIG. Semiconductor device is obtained.

Hereinafter, the semiconductor device of the reference example will be described in more detail with reference to FIG. 4 in comparison with the above-described conventional semiconductor device. FIG. 4 is a diagram for explaining the impurity profile of the semiconductor device of the reference example in comparison with the conventional example. FIG. 4A shows the impurity distribution in the depth direction of the semiconductor device of the reference example. , FIG. 4 (B)
Shows the impurity distribution in the depth direction in the conventional semiconductor device. (Note that in FIG. 4B, in order to properly compare with the reference example , N
Structure of PN type bipolar transistor (see FIGS. 5 to 7)
7 shows an impurity profile when a PNP-type bipolar transistor having the opposite conductivity type is used. )

First, in the conventional semiconductor device, as described above, between the formation of the emitter contact and the formation of the polysilicon for the emitter electrode, the polysilicon layer for the base electrode is connected to the base layer. Since the polycrystalline silicon layer is formed, the polycrystalline silicon layer is left only in the cavity by dry etching, and the oxide film is formed, the base layer is formed, so the distance between the base surface and the substrate changes. There is a possibility that the base width may change due to a variation in the amount of etching in the etching step. That is, FIG.
As shown in (B), when the etching amount is small and large, the impurity (As) distribution of the emitter layer 114 and the impurity (B) distribution of the base layer 111 change from the solid line in the figure to the one-dot chain line. As a result, the base width changes from “WB ′” to “W
B "".

On the other hand, in the semiconductor device of the present embodiment , the step of forming the N ⁺ type buried layer 7 and the step of forming the intrinsic base layer 8 during the period from the formation of the emitter contact to the formation of the emitter layer 12. Since the method is realized by a manufacturing method including a step of forming and a step of forming a sidewall on a side wall of the emitter opening, an etching step in which a distance between a base surface and a substrate is changed is not included, and the base due to process variation is not included. The change in the width WB is suppressed. That is, the impurity (As) distribution of the emitter layer 12, the impurity (B) distribution of the base layer 8, and the impurity (P) of the N ⁺ type buried layer 7
The distribution is as shown in FIG. 4A, and the base width is “W
B ".

Further, the relationship between the base width “WB” and the high-frequency characteristics will be described to further clarify the effect of the semiconductor device of the present embodiment . Here, a cutoff frequency “fT” which gives an indication of a limit of a high frequency when a transistor is used as an amplifier is considered as a remarkable characteristic of a high frequency characteristic of a semiconductor device.

"K" is the Boltzmann constant, "T" is the absolute temperature, "Cte" is the emitter capacitance, "q" is the unit charge of electrons, "Ic" is the collector current, "N" is the constant, "μB"
Is the electron mobility, “rcs” is the collector resistance, and “Ccb”
Is the collector capacitance, “Xs” is the collector depletion layer width, “vx”
Is the collector depletion layer running saturation speed, the cutoff frequency “fT” is given by the following equation.

[0039]

[Formula 1] · Expression ··· fT = 1 / 2π · (τe + τb + τc + τx) [where τe = k · T · C · te / q · Ic · τb = WB2 / N · Dn, Dn = k · T · µB τc = rcs · Ccb τx = Xs / 2vx]

Therefore, for example, in the conventional semiconductor device, if the base width “WB” changes from 1000 ° to 700 ° due to a change in the amount of dry etching, the parameter “τb” decreases to about half, Also,
Assuming that the base width “WB” changes from 1000 ° to 1300 °, the parameter “τb” increases by about 1.7 times, and the cutoff frequency “fT” changes accordingly, causing variations in the high-frequency characteristics of the semiconductor device. It will be. In contrast, reference
In the semiconductor device of the example , since the change in the base width “WB” due to the variation in the process is suppressed, such variation in the high-frequency characteristics can be suppressed, and as a result, excellent high-frequency characteristics without variation are provided. A semiconductor device can be realized.

[0041]

As described in detail above, the present invention provides a second conductivity type base electrode polycrystalline silicon layer having an emitter opening above a buried layer supported by an element isolation region, a first conductivity type collector layer, Device structure having a second conductivity type external base layer diffused in the region of the layer and between the intrinsic base layer and the polycrystalline silicon layer for the base electrode
Forming a buried layer of the first conductivity type, forming an intrinsic base layer of the second conductivity type between the formation of the emitter contact and the formation of the emitter layer; And a step of forming a side wall, characterized in that the semiconductor device can be realized without going through an etching step such that the base width or the distance between the base surface and the substrate changes, A change in the base width due to a variation in the etching amount in the etching process can be suppressed,
As a result, a half with excellent high frequency characteristics without variation
This has a remarkable effect that a method for manufacturing a conductor device can be provided.

[Brief description of the drawings]

FIG. 1 shows a semiconductor device manufactured by a manufacturing method according to the present invention.
It is a view showing one reference example of a cross-sectional view illustrating a structure of a semiconductor device of the present embodiment.

FIG. 2 is a view for explaining one embodiment of a method for manufacturing a semiconductor device according to the present invention, and is a cross-sectional view in the order of manufacturing steps including steps A to D.

FIG. 3 is a sectional view in the order of the manufacturing process, which includes a process E to a process G following the process D in FIG. 2;

FIG. 4 is an explanatory diagram for explaining an impurity profile in a semiconductor device of a reference example in comparison with a conventional example;
FIG. 3B is a diagram illustrating an impurity distribution in a depth direction in a semiconductor device of a reference example , and FIG. 3B is a diagram illustrating an impurity distribution in a depth direction of a semiconductor device of a conventional example.

FIG. 5 is a cross-sectional view illustrating a structure of a conventional semiconductor device.

FIG. 6 is a view illustrating a method for manufacturing a conventional semiconductor device, and is a cross-sectional view of a main part in the order of manufacturing steps including steps A to C;

7 is a fragmentary cross-sectional view of a manufacturing step consisting of steps D through F following step C in FIG. 6;

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 21/331 H01L 29/73

Claims (2)

(57) [Claims] (1) A first device surrounded by an element isolation region.
A second conductive type base electrode layer is formed on the conductive type collector layer.
Sequentially depositing a crystalline silicon layer and a first type of first insulating film
Process and (2) The first type of first insulating film and the base electrode
By selectively etching the crystalline silicon layer, the collector
Forming an emitter opening located substantially at the center of the data layer
When, (3) The collector exposed by the emitter opening
Introducing impurities of the first conductivity type on the layer to fill the first conductivity type
Forming an embedded layer, (4) Etching property is different from that of the first type of first insulating film.
Depositing a second type of first insulating film, and forming the emitter opening
To introduce impurities of the second conductivity type through the
Forming an intrinsic base layer of the second conductivity type in (5) a second insulating film of the same type as the first insulating film of the second type;
The first type of first insulating film and the same type of second insulating film are sequentially formed.
And etch it back to the side wall of the emitter opening.
Forming a sidewall; (6) introducing an impurity of a first conductivity type into the intrinsic base layer;
Forming an emitter layer through a subsequent heat treatment; Of a semiconductor device having at least
Method. 2. The method for manufacturing a semiconductor device according to claim 2, wherein
In the heat treatment, the second conductive type base electrode
The impurity of the second conductivity type is removed from the polycrystalline silicon layer by the collector.
Diffused into the base layer and form a second conductivity type external base layer there
3. The manufacturing of a semiconductor device according to claim 2, wherein
Method.