JP2003017503A - Method for manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a process cost. SOLUTION: The dopant concentration of a scheduled region for forming the side surface of a trench for element isolation in an SOI layer 3 is made 1×10<18> cm<-3> or higher and the dopant concentration of a scheduled region for forming the side surface of a gate trench in the trench gate type MOS transistor is made under 1×10<18> cm<-3> . Next, by etching the SOI layer 3, the trench 42 for element isolation and the gate trench 43 of a trench gate type MOS transistor are formed simultaneously. Further a thick oxide film 44 on the side surface of the trench 42 for element isolation and a thin gate oxide 45 on the side surface of the gate trench 43 are formed simultaneously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

[0002]

2. Description of the Related Art It is known to form a trench gate type MOS transistor on an element formation island in a semiconductor layer on an SOI substrate (Japanese Patent Laid-Open No. 8-330601).
JP-A-8-204195).

Generally, in wafer processing, trench etching has a large process load, and there is a demand for cost reduction. In addition to this, since a deep diffusion layer is formed by diffusion from the substrate surface in each of the drain, channel, and source regions (impurity diffusion regions), there is an improvement in that it is difficult to make the current flow uniformly in the depth direction. It has been demanded.

[0004]

The present invention has been made under such a background, and a first object thereof is to make it possible to reduce the process cost. The second purpose is to make it easier to make the current flow uniformly in the depth direction in addition to the first purpose.

[0005]

According to the present invention, it is necessary to form a thick oxide film and a thin oxide film in the element isolation trench and the gate trench, respectively. Although it has been etched and dug separately, the present invention makes it possible to form the element isolation trench and the gate trench at the same time. In wafer processing, trench etching has a large process load, and the present invention enables a significant cost reduction.

According to the manufacturing method of claim 4,
The semiconductor device according to claim 14 is obtained. Claim 7,
According to the invention described in 9, the device isolation trench, the gate trench, and the drain region trench have heretofore been provided with a thick oxide film and a thin oxide film, and an electrode material film (for example, a polysilicon film) without the oxide film. Although it was separately etched for the reason that it was necessary to form each of them, the present invention makes it possible to simultaneously form the element isolation trench and the gate trench and drain region trench. In wafer processing, trench etching has a large process load, and the present invention enables a significant cost reduction.

According to the eighth and tenth aspects of the present invention, the element isolation trench, the gate trench, the drain region trench, and the collector region trench have heretofore been thick oxide film, thin oxide film, and no oxide film. In order to form the electrode material film (for example, a polysilicon film) in the above method, the trenches for element isolation, the gate trench, the trench for the drain region, and the collector are separately formed by etching. The region trench can be formed at the same time. In wafer processing, trench etching has a large process load, and the present invention enables a significant cost reduction.

According to the invention described in claims 11 to 13,
In addition to the actions and effects of the invention described in claims 1 to 10, as a method of forming a source region, a channel region, a drift region or a drain region of a trench gate type MOS transistor, by digging a trench to epitaxially grow a semiconductor layer, With respect to the impurity concentration distribution, it is possible to form a uniform concentration distribution in the depth direction, and it is possible to obtain a power MOS having a low on-resistance with no current bias.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a vertical cross section of the semiconductor device according to the present embodiment. A thin single crystal silicon layer (single crystal semiconductor layer) 3 is formed on a silicon substrate 1 with a silicon oxide film (insulating film) 2 interposed therebetween, and constitutes an SOI substrate. SOI
The single crystal silicon layer 3 as a layer has a (110) plane as a main surface and a thickness of 1 to 100 μm. Single crystal silicon layer 3
In, the element isolation trenches 4 reaching the insulating film 2 are formed, and a large number of element formation islands are sectioned and formed in the trenches 4. Regarding the element isolation trench 4, a silicon oxide film 5 is formed on the side surface of the trench 4 and a polysilicon film 6 is filled inside the silicon oxide film 5. In the first element formation island, CM
An OS transistor is formed, an NPN transistor is formed on the second element formation island, and a trench gate type LDMOS transistor is formed on the third element formation island.

Regarding the CMOS transistor, as an N-channel MOS, a P well region 10 is formed in the surface layer portion of the N type silicon layer 3, and an N well is formed in the surface layer portion of the P well region 10.
A type source region 11 and an N type drain region 12 are formed. Further, a gate electrode 13 is arranged on the P well region 10 via a gate oxide film (not shown).
On the other hand, as a P-channel MOS, a P-type source region 14 and a P-type drain region 15 are formed in the surface layer portion of the N-type silicon layer 3, and a gate oxide film (not shown) is further formed on the N-type silicon layer 3. The gate electrode 16 is arranged via the. In the formation island of the CMOS transistor, N
An N ⁺ buried layer 17 is formed in the type silicon layer 3.

Regarding the NPN transistor, a P well region 20 is formed in the surface layer portion of the N type silicon layer 3, and an N type emitter region 21 and a P ⁺ region are formed in the surface layer portion of the P well region 20.
A base region 22 is formed. Further, an N type collector region 24 and an N ⁺ contact region 25 are formed in the surface layer portion of the N type silicon layer 3. An N ⁺ buried layer 23 is formed in the N-type silicon layer 3 on the island where the NPN transistor is formed.

Details of the trench gate type MOS transistor are shown in FIG. In FIG. 2, the N ⁺ buried layer 30 is formed in the N-type silicon layer 3. A channel P well region (P type base region) 31 is formed in the surface layer portion of the N-type silicon layer 3, and a P ⁺ contact region 32 and an N type source region 33 are formed in the surface layer portion of the channel P well region 31. Has been formed. In addition, the N-type silicon layer 3
A gate trench 34 is formed in the gate trench 34. The gate trench 34 extends from the N-type source region 33 to the channel P in the direction parallel to the surface of the N-type silicon layer 3 and in the depth direction.
It is formed so as to penetrate the well region 31. A gate oxide film 35 is formed on the inner wall surface of the gate trench 34, and a polysilicon gate electrode 36 is filled inside the gate oxide film 35. Further, the N ⁺ drain region 37 is formed at a site spaced from the channel P-well region 31 in the N-type silicon layer 3 N ⁺
The contact N ⁺ region 3 is formed on the surface layer of the drain region 37.
8 is formed.

Of the silicon layer 3, the N ⁺ buried layer 3
0, channel P well region 31, P ⁺ contact region 3
2, the N-type source region 33, the N ⁺ drain region 37, the contact N ⁺ region 38, the gate trench 34, and the region where the gate oxide film 35 is not formed are used as the drift region.

Then, as shown in FIG.
When a predetermined positive voltage is applied to 6, the electrons are induced near the gate oxide film 35 in the entire surface of the channel P well region 31 adjacent to the gate trench 34 to form a channel. A drain current flows laterally from the region 33 to the drain region 37.

Next, a semiconductor device of this type, namely, SOI
A method of manufacturing a composite IC (dielectric isolation semiconductor integrated circuit having a CMOS logic element, a bipolar element, and a power element) in which BiCMOS (NPN transistor and CMOS) and a gate trench type power MOS transistor are integrated in a layer Will be described with reference to FIG.

First, as shown in FIG. 4A, a single crystal silicon layer 3 having a (110) plane as a main surface is arranged on a silicon substrate 1 with a silicon oxide film 2 interposed therebetween. At this time,
1 × 10 ¹⁸ c in a region where an element isolation trench is formed in advance
High-concentration layers 40 and 41 having a dopant concentration of m ⁻³ or more
Are formed from the upper surface and the lower surface of the SOI layer 3. As described above, the impurity concentration in the region to be formed on the side surface of the element isolation trench in the SOI layer 3 is set to 1 × 10 ¹⁸ cm ⁻³ or more and the impurity in the region to be formed on the side surface of the gate trench in the trench gate type MOS transistor is set. Concentration 1 × 1
It is less than 0 ¹⁸ cm ^-3 .

Then, as shown in FIG.
Anisotropic etching is performed from the main surface of the OI substrate to simultaneously form the element isolation trench 42 whose side surface is the (111) plane and the gate trench 43 of the trench gate type MOS transistor whose side surface is the (100) plane.

At this time, the gate trench 43 may be formed shallower than the element isolation trench 42 by utilizing the loading effect by setting the pattern width. Subsequently, the damage layer is removed from the side surface of the trench by light etching or sacrificial oxidation, and then, as shown in FIG.
As shown in (c), a thick oxide film 44 is formed on the side surface of the element isolation trench 42 by performing thermal oxidation (gate oxidation) utilizing the concentration difference, and at the same time, the gate trench 4 is formed.
A thin oxide film (gate oxide film) 45 is formed on the side surface of 3. The thick oxide film 44 has a thickness of 100 to 300 nm, and the thin oxide film 45 has a thickness of 50 to 150 nm.

Further, as shown in FIG. 4D, an impurity-doped polysilicon film (reference numerals 46 and 47) is formed, and etched back and patterned. As a result, the impurity-doped polysilicon films 46 and 47 are arranged (embedded) in the trenches 42 and 43. Thus, the impurity-doped polysilicon film 47 as a gate electrode material film is formed inside the gate oxide film 45 in the gate trench 43. Further, the DMOS source / channel regions 48 and 49 are formed by ion implantation and diffusion.

In this way, the element isolation trench and the gate trench have been formed by separately etching them because it is necessary to form a thick oxide film and a thin oxide film, respectively. Thus, in the present embodiment, the element isolation trench is formed. 42 and the gate trench 43 can be simultaneously formed. In wafer processing, trench etching has a large process load, and this embodiment makes it possible to significantly reduce costs.

As a method of simultaneously forming the element isolation trench and the gate trench, the impurity concentration control and the crystal plane control may be performed independently. That is, as a manufacturing method for controlling the impurity concentration, the impurity concentration of the region to be formed on the side surface of the element isolation trench in the SOI layer 3 is set to 1 × 10 ¹⁸ cm ⁻³ or more and the gate trench of the trench gate type MOS transistor is formed. The impurity concentration of the side surface formation region is set to less than 1 × 10 ¹⁸ cm ⁻³ , and then the SOI layer 3 is etched to simultaneously form the element isolation trench 42 and the gate trench 43 of the trench gate type MOS transistor. A thick oxide film 44 is formed on the side surface of the element isolation trench 42 and a thin gate oxide film 45 is formed on the side surface of the gate trench 43 at the same time by thermal oxidation utilizing the concentration difference. Then, a gate electrode material film 47 is formed inside the gate oxide film 45 in the gate trench 43. On the other hand, as a manufacturing method for controlling the crystal plane, the SOI layer 3 is etched so that the side surface is (111).
The element isolation trench 42 that becomes the surface and the side surface is (100)
A gate trench 43 of a trench gate type MOS transistor to be a surface is formed at the same time, and then a thick oxide film 44 is formed on the side surface of the element isolation trench 42 by thermal oxidation utilizing the difference in plane orientation, and a side surface of the gate trench 43. At the same time, a thin gate oxide film 45 is formed. Then, a gate electrode material film 47 is formed inside the gate oxide film 45 in the gate trench 43.

As shown in FIG. 5, a (110) substrate was used to form an element isolation trench having a side surface of (111) and a gate trench having a side surface of (100). , (100) substrate, and the side surface is (11
The same effect can be obtained by laying out (arranging) the element isolation trenches which are 0) and the gate trenches whose side surfaces are (100). In particular, in the case of FIG. 6, since the (100) substrate is used, a planar type CMOS can be easily formed on the main surface of the SOI layer. (Second Embodiment) Next, the second embodiment will be described with reference to the first embodiment.
The difference from the above embodiment will be mainly described.

As shown in FIG. 7A, the silicon substrate 1
A single crystal silicon layer 3 is arranged on the above with a silicon oxide film 2 interposed therebetween. Then, the SOI layer 3 is etched to form a single trench 50 in the gate trench formation region of the trench gate type MOS transistor and a plurality of trenches 51 in the element isolation trench formation region at the same time. In FIG. 7, the width of the trench 51 is the same as the width of the trench 50 in the gate trench formation region. Further, in FIG. 7, three trenches 51 are provided.

Further, as shown in FIG. 7B, thermal oxidation (gate oxidation) is performed to form a silicon oxide film 52 on the side surfaces of a plurality of trenches 51 formed in the element isolation trench forming region, and A gate oxide film 53 is simultaneously formed on the side surface of the trench 50 formed in the gate trench formation region.

Thereafter, as shown in FIG. 7C, an impurity-doped polysilicon film (reference numerals 54 and 55) is formed and etched back. As a result, the impurity-doped polysilicon film 54 is formed in the plurality of trenches 51 formed in the element isolation trench forming region, and the impurity-doped polysilicon film 55 is simultaneously formed in the trench 50 formed in the gate trench forming region. Be done (placed). Thus, an impurity-doped polysilicon film 55 as a gate electrode material film is formed inside the gate oxide film 53 in the trench 50 formed in the gate trench formation region.

As a result, as a structure of the semiconductor device, a plurality of trenches 51 are provided in parallel in the element isolation trench formation region, and the side surface of each of the element isolation trenches 51 is covered with a gate oxide formed on the side surface of the gate trench 50. The same oxide film 52 as the film 53 is formed, and the inside of each trench 51 for element isolation is formed with the same polysilicon film 54 as the polysilicon gate electrode (gate electrode material film) 55 inside the gate trench 50. The filled one is obtained.

Thus, although the element isolation trench and the gate trench have been separately etched and dug up to this point, this embodiment allows the element isolation trench and the gate trench to be formed simultaneously. In wafer processing, trench etching has a large process load, and this embodiment makes it possible to significantly reduce costs.

In addition, three gate trenches (see FIG. 7C)
By forming trenches for element isolation by arranging the trenches indicated by reference numeral 51 in FIG. 1) in parallel, a breakdown voltage (element isolation breakdown voltage) that is six times the gate breakdown voltage can be provided. Specifically, the gate breakdown voltage is 10 V or higher, and the element isolation breakdown voltage is 6
It becomes possible to make it 0 volt or more.

The width of the trench 51 is the gate trench.
It may be different from the width of the trench 50 in the formation region.
Also, the number of trenches 51 may be any number other than three.
Yes. You may implement combining 1st and 2nd embodiment.
Yes. That is, the isolation trench of the SOI layer 3
The impurity concentration of the side surface formation planned region is set to 1 × 10.¹⁸cm ^-3Since
Trench gate type MOS transistor
Concentration of the area to be formed on the side surface of the gate trench in
1 x 10¹⁸cm^-3And then the SOI layer 3 is
Of the trench gate type MOS transistor
The side surface of the gate trench formation region is a (110) plane.
The one trench 50 is formed in the trench for element isolation.
Trays whose sides are (111) or (110) in the area
Bunches 51 are lined up at the same time.
Complexes formed in the trench formation region for element isolation by thermal oxidation
A thick oxide film on the side surfaces of the trenches 51
Thin side surface of the trench 50 formed in the trench formation region
A gate oxide film is formed at the same time. And gate train
Gate oxide film in the trench 50 formed in the trench formation region
A gate electrode material film 55 is formed inside. (Third Embodiment) Next, the third embodiment will be described with reference to the first embodiment.
The difference from the above embodiment will be mainly described.

As shown in FIG. 8A, the silicon substrate 1
A single crystal silicon layer 3 is arranged on the above with a silicon oxide film 2 interposed therebetween. Then, as shown in FIG. 8B, the element isolation trench 60 and the gate trench 61 of the trench gate type MOS transistor are simultaneously formed in the SOI layer 3 by anisotropic dry etching. Here, for example, the width of the element isolation trench 60 is set to 2 μm, and the gate trench 6 is formed.
The width of 1 is 0.5 μm.

After the damage layer is removed from the side surfaces of the trenches 60 and 61 by light etching or sacrificial oxidation, as shown in FIG. 8C, the element isolation trench 6 is formed.
0 and the gate trench 61, the oxide film 6 on the trench side surface.
2 is formed, and an impurity-doped polysilicon film (electrode material film) 63 is deposited on the inside thereof. At this time, the gate trench 61 side is completely filled and the element isolation trench 60 side is not filled due to the difference in trench width (the polysilicon film thickness and the trench width are designed). Here, for example, the thickness of the oxide film 62 is 50 to 150 nm, and the thickness of the impurity-doped polysilicon film 63 is 0.
It is 3 to 1.0 μm.

Subsequently, the impurity-doped polysilicon film 63 is etched back to remove S as shown in FIG. 9 (a).
The upper surface of the OI layer 3 and the impurity-doped polysilicon film 63 inside the element isolation trench 60 are removed, and the impurity-doped polysilicon film 63 inside the gate trench 61 is left. Then, as shown in FIG. 9B, C
The oxide film 64 fills the inside of the element isolation trench 60 by depositing and etching back the VD oxide film. further,
DMOS channel P region 65 by ion implantation and diffusion
And the N ⁺ source region 66 and the like are formed.

A metal film may be used as the electrode material film instead of the impurity-doped polysilicon film 63. In this way, the isolation trench 60 and the gate trench 6 are formed.
1 is formed with an oxide film 62, and a polysilicon film 63 is formed thereon.
At the time of growing, the polysilicon film thickness and the trench width are designed such that the gate trench 61 side is filled and the element isolation trench 60 side is not filled due to the difference in trench width, and the polysilicon etchback step after that is performed. Thus, the polysilicon film 63 is removed only on the element isolation trench 60 side and the oxide film 64 is buried. As a result, the element isolation trench and the gate trench have been separately etched and dug up to now, but the element isolation trench 60 and the gate trench 61 can be simultaneously formed by this embodiment. In wafer processing, trench etching has a large process load, and this embodiment makes it possible to significantly reduce costs. (Fourth Embodiment) Next, a fourth embodiment will be described.
The difference from the above embodiment will be mainly described.

In the present embodiment, the element isolation trench, the gate trench of the trench gate type MOS transistor, the N type drain region and the N type collector region of the NPN transistor shown in FIG. 1 can be formed more easily. It is the one. This method may be applied when the element isolation trench, the gate trench of the trench gate type MOS transistor, and the drain region are to be formed more simply (for example, when the bipolar transistor is not integrated).

As shown in FIG. 10A, a patterned silicon oxide film 70 is arranged on the SOI layer 3 of the SOI substrate, and the SOI layer 3 is etched using the silicon oxide film 70 as a mask. An element isolation trench 71, a gate trench 72 of a trench gate type MOS transistor, and a drain region trench 73 (not shown, but a collector region trench of a bipolar transistor is similar to the trench 73) are simultaneously formed.

Then, as shown in FIG. 10B, an oxide film 74 is formed on the side surface of each trench. After that,
The oxide film 74 in the unnecessary portion is removed by wet etching. In this wet etching, as shown in FIG. 10C, the wet etching solution spills around the oxide film 74 in the element isolation trench 71 and the drain region trench (same for the collector region trench) 73, so that the gate is removed. With respect to the oxide film 74 in the trench 72, the wet etching solution is prevented from wrapping around the trench 72.
The oxide film 74 in 1 and 73 is removed. That is, FIG.
In the trench forming step in (a), the gate trench 7
The width of 2 is a small dimension.

Further, as shown in FIG. 10D, an impurity-doped polysilicon film (or metal film) 75 as an electrode material film is formed on the upper surface of the SOI layer 3 including the inside of the trench. At this time, the inside of the gate trench 72 and the inside of the drain region trench (also the collector region trench) 73 are filled, and the inside of the element isolation trench 71 is not filled. Then, as shown in FIG. 11A, a CVD oxide film 76 is formed to fill the inside of the element isolation trench 71 with the CVD oxide film 76.

Subsequently, as shown in FIG. 11B, the oxide film 76 is flattened by etching back or CMP. Further, as shown in FIG. 11C, by performing heat treatment, the impurities in the impurity-doped polysilicon film 75 inside the drain region trench (and the collector region trench) 73 and the element isolation trench 71 are removed. Impurities in the impurity-doped polysilicon film 75 inside are diffused into the silicon layer 3. As a result, the N-type drain region 78 (as well as the collector region) is formed.

As described above, according to the present embodiment, the element isolation trench, the gate trench, the drain region trench, and the collector region trench have heretofore been thickly doped with an oxide film and a thin oxide film, or doped with impurities without an oxide film. Since it was necessary to separately form the top polysilicon film, it was separately etched and dug. However, according to this embodiment, the element isolation trench 71, the gate trench 72, the drain region trench 73, and the collector region trench are simultaneously formed. Will be able to. In wafer processing, trench etching has a large process load, and this embodiment makes it possible to significantly reduce costs.

As another example, the following may be performed. Figure 1
From the state of 0 (d) to the impurity-doped polysilicon film 75
Is etched back to remove the impurity-doped polysilicon film 75 in the trench 71, and subsequently, as shown in FIG. 12A, a CVD oxide film 76 is formed to form a CVD oxide film in the element isolation trench 71. Embed with 76. And
As shown in FIG. 12B, the oxide film 76 is flattened by etching back or CMP. Further, as shown in FIG. 12C, heat treatment is performed to form an N-type drain region 78 (same for the collector region). (Fifth Embodiment) Next, a fifth embodiment will be described.
The difference from the above embodiment will be mainly described.

As shown in FIG. 13A, the SOI layer 3 is etched by using the patterned oxide film 80 on the SOI layer 3 of the SOI substrate as a mask to etch the element isolation trench 81 and the trench gate type MOS transistor. A gate trench 82 and a drain region trench 83 (not shown, the collector region trench of the bipolar transistor is similar to the trench 83) are formed at the same time.

Then, as shown in FIG. 13B, an oxide film 84 is formed on the side surface of the trench so that only the inside of the drain region trench 83 (same for the collector region trench) is filled in each trench. In other words, the width of each trench is designed to do so. Furthermore, FIG.
As shown in (c), the impurity-doped polysilicon film (gate electrode material film) 8 is formed so that the inside of the gate trench 82 is filled and the inside of the element isolation trench 81 is not filled.
5 is formed into a film. In other words, the width of the gate trench 82 and the film thickness of the impurity-doped polysilicon film 85 are designed so as to do so. Then, as shown in FIG. 13D, when the etch back is performed, the impurity-doped polysilicon film 85 remains in the trench 82 and is removed from the trench 81.

Continuing, as shown in FIG.
The VD oxide film 86 is deposited to fill the inside of the element isolation trench 81 with the CVD oxide film 86. Then, the CVD oxide film 86 is flattened by etching back or CMP. Further, as shown in FIG. 14B, the oxide film inside the drain region trench 83 (the same applies to the collector region trench) is removed by wet etching. Then, as shown in FIG. 14C, a metal film (electrode material film) 87 is filled in the drain region trench 83 (the same applies to the collector region trench). That is, the metal film 87 is embedded to form a drain / collector electrode.

As described above, according to this embodiment, the element isolation trench 81, the gate trench 82, the drain region trench 83, and the collector region trench can be simultaneously formed.

The present embodiment may also be applied to the case where the element isolation trench, the gate trench and the drain region of the trench gate type MOS transistor are to be formed more simply (for example, the bipolar transistor is integrated. If not). (Sixth Embodiment) Next, a sixth embodiment will be described.
The differences from the fifth embodiment will be mainly described.

In this embodiment, in addition to the manufacturing methods of the first to fifth embodiments, the trench gate type M shown in FIG.
The method of manufacturing the channel region and the source region of the OS transistor is characterized. A semiconductor device according to the present embodiment, which is an alternative to FIG. 1, is shown in FIG. The trench gate type MOS transistor in the semiconductor device of FIG. 15 has the structure shown in FIG.

In FIG. 16, the channel P region 92 is formed in the N-type silicon layer (thickness 1 to 100 μm) 3 having the (110) plane as the main surface, and the channel P region 92 is formed.
The N ⁺ source region 93 is formed on the front surface side (inner side). This channel P region 92 and N ⁺ source region 93
For this, an impurity-doped silicon layer formed by epitaxial growth is used. Further, a P ⁺ contact region 94 is formed in the surface layer portion of the channel P region 92. Furthermore, a gate trench 95 is formed in the N-type silicon layer 3 (and the buried epi layer), a gate oxide film 96 is formed on the side surface of the gate trench 95, and a poly-silicon film is formed inside the gate oxide film 96. The silicon gate electrode 97 is filled. Channel P region 9 in N-type silicon layer 3
An N ⁺ drain region 91 is formed in a portion separated from 2.

Next, the manufacturing method will be described. FIG. 17
As shown in (a), the i layer 101 is formed on the surface layer portion of the N ⁻ silicon substrate 100. Then, as shown in FIG. 17B, the silicon substrate 100 is formed by ion implantation and thermal diffusion.
A deep diffusion region (dopant concentration of 1 × 10 ¹⁸ cm ⁻³ or more) 102 is formed at the same time, and a shallow diffusion region (embedded N ⁺ layer) 103 is formed at a predetermined region. Furthermore, FIG.
As shown in (c), the substrate 100 is turned upside down,
The silicon substrate 100 is attached onto the silicon substrate 104 with the insulating film 105 interposed therebetween. And the silicon substrate 1
An SOI substrate is obtained by thinning 00.

Subsequently, as shown in FIG. 18A, S
The trench 106 is formed by performing anisotropic wet etching (for example, TMAH etching) or dry etching on the OI layer 100. The region where the trench 106 is formed is a portion that will be a channel region and a source region of the trench gate type MOS transistor. Furthermore, FIG.
As shown in (b), the channel P region (epi diffusion layer) 10 is formed in the trench 106 by continuous epitaxial growth.
7 and N ⁺ source region (epi diffusion layer) 108 are formed, and then the surface is flattened by CMP (polishing).

Then, as shown in FIG. 18C, deep N ^{+ is formed in the} silicon layer 100 by ion implantation and thermal diffusion.
A diffusion region 110 that reaches the diffusion region 102 is formed. Further, as shown in FIG. 19A, each trench (element isolation trench 111a, gate trench 111b) is formed, and each trench is filled with a polysilicon film 113 via an oxide film 112. That is, the element isolation trench 1 whose side surface is (111) from the main surface of the SOI substrate
11a and the gate trench 11 whose side surface is (100)
1b is formed at the same time by anisotropic dry etching, and the side surface of the trench is removed by light etching or sacrificial oxidation to remove the damaged layer, and then gate oxidation is performed to form an oxide film on the element isolation trench side from 100 nm to 30 nm.
0 nm thick, and at the same time 50 nm oxide film on the gate trench side.
-150 nm is formed. Then, an impurity-doped polysilicon film is buried in the trench, and a gate electrode is formed by etching back and patterning.

Then, as shown in FIG. 19B, a desired diffusion process is performed. That is, the diffusion layer of the CMOS, the bipolar transistor, and the trench gate LDMOS is formed by ion implantation and diffusion from the surface. This FIG. 19 (b)
And the bipolar transistor and the CM in the SOI layer 3
At the bottom of the OS, there are regions 101 and 103 having a dopant concentration of 1 × 10 ¹⁸ cm ⁻³ or more.

As described above, in addition to the manufacturing methods of the first to fifth embodiments, before forming the element isolation trench and the gate trench, the trench gate type MOS transistor in the single crystal semiconductor layer 3 is formed. Another trench 106 is formed by anisotropic wet etching or dry etching in the portions to be the channel region and the source region,
Impurity-doped silicon layer (impurity-doped semiconductor layer) is formed in the trench 106 by continuous epitaxial growth.
107 and 108 were formed as a channel region and a source region. Therefore, the source region of the trench gate type MOS transistor (lateral trench gate power MOS),
As a method for forming the channel region, a trench is dug and a semiconductor layer is epitaxially grown, whereby a uniform concentration distribution can be formed in the depth direction with respect to the impurity concentration distribution, and a low on-resistance power MOS with no current bias is obtained. Is possible. Further, when the channel region and the source region are formed by the impurity diffusion layer by ion implantation, the occupied area tends to be large due to the lateral expansion of the diffusion layer,
If the epi layer is used, the size can be reduced.

As another example, as shown in FIG. 20, the drain region 150 in the trench gate LDMOS is
Using the method described with reference to FIGS. 10 and 11, the impurity-doped polysilicon film 15 in the trench 151 of FIG. 20 is used.
It may be formed by diffusing the impurities in 2 by heat treatment. By doing so, compared to the case where the drain region 91 is formed by ion implantation from both the upper and lower surfaces in FIG. 15, it is possible to suppress the expansion of the drain region in the lateral direction, and it is possible to reduce the size of the element.

As another example, as shown in FIG. 21, before forming the element isolation trench and the gate trench, S
Anisotropic wet is applied to a part of the drift region of the trench gate type MOS transistor in the OI layer 3 (the portion indicated by the reference numeral 120), the channel region (the portion indicated by the reference numeral 92) and the source region (the portion indicated by the reference numeral 93). Another trench 121 by etching or dry etching
And the impurity-doped semiconductor layers 120, 92, 93 are formed in the trench 121 by continuous epitaxial growth.
May be formed as a part of the drift region, the channel region and the source region. After the epitaxial growth, the surface is flattened by CMP.

Alternatively, as shown in FIG. 22, before forming the element isolating trench and the gate trench, the drain region (the place indicated by the reference numeral 130) and the drift region (the reference numeral 130) of the trench gate type MOS transistor in the single crystal semiconductor layer. 131), a channel region (a place indicated by a reference numeral 92) and a source region (a place indicated by a reference numeral 93), another trench 132 is formed by anisotropic wet etching or dry etching, and a continuous epitaxial growth is performed. The impurity-doped semiconductor layers 130, 131, 92, 93 may be formed in the trench 132 to serve as a drain region, a drift region, a channel region and a source region. After the epitaxial growth, the surface is flattened by CMP.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view of a semiconductor device according to an embodiment.

FIG. 2 is a detailed view of a power transistor.

FIG. 3 is a diagram for explaining the operation of a power transistor.

FIG. 4 is a vertical cross-sectional view for explaining the manufacturing process in the first embodiment.

FIG. 5 is a diagram for explaining plane orientations.

FIG. 6 is a diagram for explaining plane orientations.

FIG. 7 is a vertical cross-sectional view for explaining a manufacturing process in the second embodiment.

FIG. 8 is a vertical cross-sectional view for explaining the manufacturing process in the third embodiment.

FIG. 9 is a vertical cross-sectional view for explaining the manufacturing process in the third embodiment.

FIG. 10 is a vertical cross-sectional view for explaining the manufacturing process in the fourth embodiment.

FIG. 11 is a vertical cross-sectional view for explaining the manufacturing process in the fourth embodiment.

FIG. 12 is a vertical sectional view for explaining another manufacturing process.

FIG. 13 is a vertical cross-sectional view for explaining the manufacturing process in the fifth embodiment.

FIG. 14 is a vertical cross-sectional view for explaining the manufacturing process in the fifth embodiment.

FIG. 15 is a vertical cross-sectional view of a semiconductor device in an embodiment.

FIG. 16 is a detailed view of a power transistor.

FIG. 17 is a vertical cross-sectional view for explaining the manufacturing process in the sixth embodiment.

FIG. 18 is a vertical cross-sectional view for explaining the manufacturing process in the sixth embodiment.

FIG. 19 is a vertical cross-sectional view for explaining the manufacturing process in the sixth embodiment.

FIG. 20 is a vertical cross-sectional view of a semiconductor device of another example.

FIG. 21 is a vertical cross-sectional view of the power transistor according to the embodiment.

FIG. 22 is a vertical cross-sectional view of the power transistor according to the embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Silicon oxide film, 3 ... Single crystal silicon layer, 40 ... High concentration layer, 41 ... High concentration layer, 42 ... Element isolation trench, 43 ... Gate trench, 44 ... Oxide film, 45 ... Gate Oxide film, 50 ... Trench, 51 ... Gate trench, 52 ... Oxide film, 53 ... Gate oxide film, 60
... Element isolation trenches, 61 ... Gate trenches, 62 ...
Oxide film, 63 ... Polysilicon film, 71 ... Element isolation trench, 72 ... Gate trench, 73 ... Drain region trench, 74 ... Oxide film, 75 ... Impurity-doped polysilicon film, 81 ... Element isolation trench, 82 ... Gate trench, 83 ... Drain region trench, 84 ... Oxide film,
85 ... Impurity-doped polysilicon film, 87 ... Metal electrode film, 92 ... Channel region, 93 ... Source region, 106 ...
Trench, 107 ... Epi layer (channel region), 108 ...
Epi layer (source region), 120 ... Epi layer (part of drift region), 121 ... Trench, 130 ... Epi layer (drain region), 131 ... Epi layer (drift region), 132 ...
Trench.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/8249 H01L 29/78 613A 27/06 620 27/08 331 21/76 L 27/06 321C 29 / 732 101U 29/786 29/72 P 21/76 D (72) Inventor Ritaka Noda 1-1, Showa-cho, Kariya city, Aichi prefecture F-term in DENSO stock company (reference) 5F003 AZ03 BA25 BA27 BC08 BJ15 BP11 5F032 AA01 AA35 AA45 AA47 CA03 CA17 CA18 CA20 DA25 DA43 DA47 DA53 5F048 AA04 AA05 AA09 AC03 AC05 AC06 BA10 BA16 BB05 BB19 BB20 BC03 BE01 BE03 BG14 CA03 CA04 CA07 DA06 5F082 CC10 A02 BB15A10 A02 BC15 CA06 A04 A15 A06A06 A15A06 CA12 CA04 EA12 A15A06 CA12 AA5A08A15 AA5 A4 A5 A4 A5 A4 A5 A4 A5 A4 A5 A4 A5 A4 A5 A4 A4 A5 A5 A4 DD13 EE09 EE22 FF02 GG02 GG12 GG22 GG34 GG52 GG53 HM12 NN62

Claims (14)

[Claims] 1. A single crystal semiconductor layer is formed on a substrate via an insulating film, and an element isolation trench reaching the insulating film is formed in the single crystal semiconductor layer, and an element partitioned by the trench is formed. Trench gate type MO on formation island
A method of manufacturing a semiconductor device in which an S transistor is formed, wherein an impurity concentration of a planned formation region of a side surface of the element isolation trench in a single crystal semiconductor layer arranged on a substrate with an insulating film interposed therebetween is 1 × 10 ¹⁸ cm 2. ^-3 or more, and the impurity concentration of the region to be formed on the side surface of the gate trench in the trench gate type MOS transistor is 1 × 10 ¹⁸ cm ^-3.
And a step of simultaneously etching the single crystal semiconductor layer to form the element isolation trench and the gate trench of the trench gate type MOS transistor, and a thick oxide film is formed on the side surface of the element isolation trench by thermal oxidation. A semiconductor device comprising: a step of simultaneously forming a thin gate oxide film on a side surface of the gate trench; and a step of forming a gate electrode material film inside the gate oxide film in the gate trench. Manufacturing method. 2. A single crystal semiconductor layer is formed on a substrate via an insulating film, and an element isolation trench reaching the insulating film is formed in the single crystal semiconductor layer, and an element partitioned by the trench is formed. Trench gate type MO on formation island
A method for manufacturing a semiconductor device in which an S transistor is formed, wherein a side surface is a (111) plane or a (110) plane by etching a single crystal semiconductor layer arranged on a substrate with an insulating film interposed therebetween. A step of simultaneously forming a trench and a gate trench of a trench gate type MOS transistor whose side surface is a (100) plane, and a thick oxide film on the side surface of the element isolation trench and a thin film on the side surface of the gate trench by thermal oxidation. A method of manufacturing a semiconductor device, comprising: a step of simultaneously forming a gate oxide film; and a step of forming a gate electrode material film inside a gate oxide film in a gate trench. 3. A single crystal semiconductor layer is formed on a substrate via an insulating film, and an element isolation trench reaching the insulating film is formed in the single crystal semiconductor layer, and an element partitioned by this trench is formed. Trench gate type MO on formation island
A method of manufacturing a semiconductor device in which an S transistor is formed, wherein an impurity concentration of a planned formation region of a side surface of the element isolation trench in a single crystal semiconductor layer arranged on a substrate with an insulating film interposed therebetween is 1 × 10 ¹⁸ cm 2. ^-3 or more, and the impurity concentration of the region to be formed on the side surface of the gate trench in the trench gate type MOS transistor is 1 × 10 ¹⁸ cm ^-3.
And a step of etching the single crystal semiconductor layer so that the side surface has (11
1) or (110) plane element isolation trenches and trench gate type MOS whose side surfaces are (100) planes
The process of simultaneously forming the gate trench of the transistor, the process of forming a thick oxide film on the side face of the isolation trench by thermal oxidation, and the process of forming the thin gate oxide film on the side face of the gate trench at the same time, And a step of forming a gate electrode material film inside the gate oxide film. 4. A single crystal semiconductor layer is formed on a substrate via an insulating film, and an element isolation trench reaching the insulating film is formed in the single crystal semiconductor layer, and an element partitioned by this trench is formed. Trench gate type MO on formation island
A method of manufacturing a semiconductor device in which an S transistor is formed, wherein a single crystal semiconductor layer disposed on a substrate via an insulating film is etched to form a single trench in a gate trench formation region of a trench gate type MOS transistor. Also, a step of simultaneously forming a plurality of trenches in the element isolation trench formation region, an oxide film on the side surfaces of the plurality of trenches formed in the element isolation trench formation region, and a trench formed in the gate trench formation region A step of simultaneously forming a gate oxide film on the side surface of the gate electrode, and a step of forming a gate electrode material film inside the gate oxide film in the trench formed in the gate trench formation region,
A method of manufacturing a semiconductor device, comprising: 5. A single crystal semiconductor layer is formed on a substrate via an insulating film, and an element isolation trench reaching the insulating film is formed in the single crystal semiconductor layer, and an element partitioned by the trench is formed. Trench gate type MO on formation island
A method of manufacturing a semiconductor device in which an S transistor is formed, wherein an impurity concentration of a formation planned region on a side surface of the element isolation trench in a single crystal semiconductor layer arranged on a substrate with an insulating film interposed therebetween is 1 × 10 ¹⁸ cm 2. ^-3 or more, and the impurity concentration of the region to be formed on the side surface of the gate trench in the trench gate type MOS transistor is 1 × 10 ¹⁸ cm ^-3.
And a step of making the single crystal semiconductor layer into a trench gate type M
A single trench whose side surface is a (100) plane is formed in the gate trench formation region of the OS transistor, and a side surface is a (111) plane or (11) plane in the element isolation trench formation region.
The step of simultaneously forming a plurality of trenches to be the (0) plane, and a thick oxide film on the side surfaces of the plurality of trenches formed in the element isolation trench formation region by thermal oxidation, and the gate trench formation region. A step of simultaneously forming a thin gate oxide film on the side surface of the trench formed in, and a step of forming a gate electrode material film inside the gate oxide film in the trench formed in the gate trench formation region,
A method of manufacturing a semiconductor device, comprising: 6. A single crystal semiconductor layer is formed on a substrate via an insulating film, and an element isolation trench is formed in the single crystal semiconductor layer to reach the insulating film, and the element is divided by this trench. Trench gate type MO on formation island
A method of manufacturing a semiconductor device in which an S transistor is formed, wherein a trench for element isolation and a trench gate type M are formed by etching a single crystal semiconductor layer disposed on a substrate via an insulating film.
The step of simultaneously forming the gate trench of the OS transistor, and the oxide film on the side surface of the trench so as to completely fill the gate trench side with respect to the element isolation trench and the gate trench of the trench gate type MOS transistor and not to fill the element isolation trench side. A step of forming an inner electrode material film, and a step of etching back the electrode material film to remove the electrode material film inside the element isolation trench and leave the electrode material film inside the gate trench. A method of manufacturing a semiconductor device, comprising: 7. A single crystal semiconductor layer is formed on a substrate via an insulating film, and an element isolation trench reaching the insulating film is formed in the single crystal semiconductor layer, and an element partitioned by the trench is formed. Trench gate type MO on formation island
A method of manufacturing a semiconductor device in which an S transistor is formed, wherein a trench for element isolation and a trench gate type M are formed by etching a single crystal semiconductor layer disposed on a substrate via an insulating film.
A step of simultaneously forming a gate trench and a drain region trench of an OS transistor, and an element isolation trench after an oxide film is formed on the side surface of the device isolation trench and the trench gate type drain transistor trench of the gate type MOS transistor. Wet etching solution wraps around the oxide film inside and inside the drain region trench, and prevents wet etching liquid from wrapping around the oxide film inside the gate trench. A method of manufacturing a semiconductor device, comprising: a removing step; and a step of forming an electrode material film inside a gate trench and inside a drain region trench. 8. A single crystal semiconductor layer is formed on a substrate via an insulating film, and an element isolation trench reaching the insulating film is formed in the single crystal semiconductor layer, and an element partitioned by the trench is formed. Trench gate type MO on formation island
A method for manufacturing a semiconductor device in which an S transistor is formed and a bipolar transistor is formed on another element formation island, wherein a single crystal semiconductor layer disposed on a substrate with an insulating film interposed therebetween is etched to form a trench for element isolation. Trench gate type M
A step of simultaneously forming a gate trench and a drain region trench of an OS transistor, and a collector region trench of a bipolar transistor, an element isolation trench, a gate trench and a drain region trench of a trench gate type MOS transistor, and a bipolar transistor collector region After the oxide film is formed on the side surface of the trench, the wet etching solution wraps around the oxide film in the element isolation trench, the drain region trench, and the collector region trench, and wet etches the oxide film in the gate trench. The process of removing the oxide film in the element isolation trench, the drain region trench, and the collector region trench so that the liquid does not flow around, and the inside of the gate trench, the inside of the drain region trench, and the inside of the trench. The method of manufacturing a semiconductor device characterized by comprising: a step of forming an internal electrode material film Kuta area trenches, the. 9. A single crystal semiconductor layer is formed on a substrate via an insulating film, and an element isolation trench reaching the insulating film is formed in the single crystal semiconductor layer, and an element partitioned by the trench is formed. Trench gate type MO on formation island
A method of manufacturing a semiconductor device in which an S transistor is formed, wherein a trench for element isolation and a trench gate type M are formed by etching a single crystal semiconductor layer disposed on a substrate via an insulating film.
A step of simultaneously forming a gate trench and a drain region trench of an OS transistor, and a trench side surface so that only the inside of the drain region trench is filled with respect to an element isolation trench and a trench gate type drain transistor trench and a drain region trench. A step of forming an oxide film on the gate trench, and a step of forming a gate electrode material film inside the gate trench and removing the oxide film inside the drain region trench before filling the electrode material film. A method for manufacturing a semiconductor device, comprising: 10. A single crystal semiconductor layer is formed on a substrate via an insulating film, and an element isolation trench reaching the insulating film is formed in the single crystal semiconductor layer, and an element partitioned by the trench is formed. Trench gate type M on formation island
A method for manufacturing a semiconductor device in which an OS transistor is formed and a bipolar transistor is formed on another element formation island, wherein a single crystal semiconductor layer arranged on a substrate with an insulating film interposed therebetween is etched to form a trench for element isolation. Trench gate type M
A step of simultaneously forming a gate trench and a drain region trench of an OS transistor, and a collector region trench of a bipolar transistor, an element isolation trench, a gate trench and a drain region trench of a trench gate type MOS transistor, and a bipolar transistor collector region The process of forming an oxide film on the side surface of the trench so that only the inside of the drain region trench and the collector region trench is filled with the trench, and the gate electrode material film is formed inside the gate trench and the inside of the drain region trench. And a step of removing an oxide film inside the collector region trench and then filling the electrode material film with the oxide film, and a method of manufacturing a semiconductor device. 11. The method for manufacturing a semiconductor device according to claim 1, wherein a channel region and a source region of a trench gate type MOS transistor in a single crystal semiconductor layer are formed before forming the trench. Another trench by anisotropic wet etching or dry etching in the area where
A method of manufacturing a semiconductor device, wherein an impurity-doped semiconductor layer is formed in the another trench by epitaxial growth to form a channel region and a source region. 12. The method of manufacturing a semiconductor device according to claim 1, wherein a part of a drift region of a trench gate type MOS transistor in the single crystal semiconductor layer is formed before forming the trench. Another trench is formed by anisotropic wet etching or dry etching in a portion to be a channel region and a source region, and an impurity-doped semiconductor layer is formed in the another trench by epitaxial growth to form a part of the drift region, the channel region, and A method of manufacturing a semiconductor device, characterized in that the source region is used. 13. The method of manufacturing a semiconductor device according to claim 1, wherein the drain region of the trench gate type MOS transistor in the single crystal semiconductor layer is formed before forming the trench.
Drift region, channel region and another region is formed by anisotropic wet etching or dry etching in a portion to be a source region, and an impurity-doped semiconductor layer is formed in the other trench by epitaxial growth to form a drain region, a drift region, A method of manufacturing a semiconductor device, characterized in that a channel region and a source region are used. 14. A single crystal semiconductor layer is formed on a substrate via an insulating film, and an element isolation trench reaching the insulating film is formed in the single crystal semiconductor layer, and an element partitioned by the trench is formed. Trench gate type M on formation island
In a semiconductor device in which an OS transistor is formed, a plurality of trenches are arranged in parallel in an element isolation trench formation region, and the same oxide film as the gate oxide film formed on the side surface of the gate trench is formed on the side surface of each element isolation trench. And further, inside each trench for element isolation,
A semiconductor device characterized by being filled with the same film as a gate electrode material film inside a gate trench.