JP2011243654A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which suppresses noise transmitted between first and second element forming regions.SOLUTION: A semiconductor element formed in a first element forming region 20, out of semiconductor elements formed in the first and second element forming regions 20 and 30, is connected with an external device. First conductivity type layers 60 and a second conductivity type layer 61, which is sandwiched between the first conductivity type layers 60, are arranged between the first element forming region 20 and the second element forming region 30. Depletion layers 63 and 64, which respectively reach a buried insulating layer 11 from the surface of a semiconductor layer 12 when the semiconductor device is turned off and separates between the first element forming region 20 and the second element forming region 30, are formed between the first and second conductivity type layers 60 and 61.

Description

  The present invention relates to a semiconductor device having first and second element formation regions, in which the first and second element formation regions are insulated and isolated by insulating isolation trenches.

  2. Description of the Related Art Conventionally, a semiconductor device in which first and second element formation regions are insulated and isolated from each other by an insulating isolation trench formed in a semiconductor substrate is known (see, for example, Patent Document 1).

  Such a semiconductor device includes, for example, an SOI (Silicon on Insulator) having a support substrate, an insulating film disposed on the surface of the support substrate, and a semiconductor layer disposed on the opposite side of the support substrate with the insulating film interposed therebetween. ) It is configured using a substrate. In the semiconductor layer, a trench surrounding the first and second element formation regions is formed, and the trench is filled with an insulator so that the first and second element formation regions are insulated and separated from each other. A trench is formed. Also, semiconductor elements such as diodes and transistors are formed in the first and second element formation regions.

  For example, such a semiconductor device is configured such that, among the semiconductor elements formed in the first and second element formation regions, the semiconductor element formed in the first element formation region is connected to the external device, thereby The signal can be transmitted and received.

Japanese Patent Laid-Open No. 08-130243

  However, in such a semiconductor device, when a predetermined signal is output to the external device from the semiconductor element formed in the first element formation region, or when a potential fluctuation occurs in the external device, the first Noise may be applied to a semiconductor element formed in one element formation region. Then, the noise is capacitively coupled between the first and second element formation regions via the insulating isolation trench, and thus there is a problem that the noise propagates to the semiconductor element formed in the second element formation region.

  For this reason, for example, by increasing the width of the insulating isolation trench, in other words, by increasing the thickness of the insulator embedded in the trench, the capacitance between the first and second element formation regions is reduced. It is conceivable to suppress noise propagation. However, in such a semiconductor device, by increasing the thickness of the insulator, the stress applied from the insulator to the first element formation region and the second element formation region increases, and the first and second element formations are increased. There is a problem that the characteristics of the semiconductor element formed in the region are deteriorated.

  In view of the above points, the present invention provides a semiconductor device capable of suppressing the propagation of noise between first and second element formation regions without increasing the thickness of an insulator embedded in a trench. For the purpose.

  In order to achieve the above object, according to the first aspect of the present invention, of the semiconductor elements formed in the first and second element formation regions (20, 30), the first element formation region (20) is formed. The semiconductor element is connected to an external device. Between the first element formation region (20) and the second element formation region (30), the first conductivity type layer (60) and the first conductivity type layer ( 60) and a second conductivity type layer (61) sandwiched between the first and second conductivity type layers (60, 61) from the surface of the semiconductor layer (12) when turned off. Depletion layers (63, 64) that reach the film (11) and partition the first and second element formation regions (20, 30) are formed.

  In such a semiconductor device, for example, when the first conductivity type layer (60) is a P-type layer and the second conductivity type layer (61) is an N-type layer, the first and second element formation regions are formed. A PNP junction is formed between (20, 30).

  Therefore, when a positive voltage noise is applied to the first element formation region (20), the first conductivity type layer (60) and the second conductivity type layer (61) on the second element formation region (30) side. ), A depletion layer (63) formed between the first and second conductivity type layers (60, 61) spreads. For this reason, the capacity | capacitance between 1st, 2nd element formation area (20, 30) is reduced, and it is suppressed that the said noise propagates to 2nd element formation area (30).

  When negative voltage noise is applied to the first element formation region (20), the first conductivity type layer (60) and the second conductivity type layer (61) on the first element formation region (20) side. A reverse bias voltage is applied between the first and second conductivity type layers (60, 61), and the depletion layer (64) is expanded. For this reason, the capacity | capacitance between 1st, 2nd element formation area (20, 30) is reduced, and it is suppressed that the said noise propagates to 2nd element formation area (30).

  For example, as in the invention described in claim 2, each of the semiconductor layers (12) surrounds the insulating isolation trench (40) and reaches the buried insulating film (11) from the surface of the semiconductor layer (12), and The first conductivity type layer (60) which is in a separated state can be formed, and the second conductivity type layer (61) can be disposed between the first conductivity type layers (60).

  Further, as in the third aspect of the invention, the first conductivity type layer (60) is disposed between the first and second element formation regions (20, 30), and the first conductivity type layer (60 ) To form a trench (70), and the second conductivity type layer (61) can be embedded in the trench (70).

  Further, as in the invention described in claim 4, in the invention described in claim 3, an insulating film is disposed on the side wall of the trench (70), and the second conductivity type layer (61) is interposed through the insulating film. Can be embedded.

  Further, as in the invention described in claim 5, in the invention described in claims 3 and 4, a semiconductor having a trench gate structure in at least one of the first and second element formation regions (20, 30). An element can be formed.

  In such a semiconductor device, when forming the trench constituting the trench gate structure, the trench (70) formed between the first and second element formation regions (20, 30) can be formed simultaneously. The step of forming only the trench (70) formed in the first and second element formation regions (20, 30) can be eliminated.

  In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim shows the correspondence with the specific means as described in embodiment mentioned later.

(A) is a figure which shows the cross-sectional structure of the semiconductor device in 1st Embodiment of this invention, (b) is a schematic plan view of the semiconductor device shown to (a). (A) is a figure which shows the state of a semiconductor device when the noise of a positive voltage is applied to a diode with respect to an NPN transistor, (b) is a noise of a negative voltage to a diode with respect to an NPN transistor. It is a figure which shows the state of a semiconductor device when is applied. (A) is a figure which shows the cross-sectional structure of the semiconductor device in 2nd Embodiment of this invention, (b) is a schematic plan view of the semiconductor device shown to (a). (A) is a figure which shows the state of a semiconductor device when the noise of a positive voltage is applied to a diode with respect to an NPN transistor, (b) is a noise of a negative voltage to a diode with respect to an NPN transistor. It is a figure which shows the state of a semiconductor device when is applied. (A) is a figure which shows the cross-sectional structure of the semiconductor device in 3rd Embodiment of this invention, (b) is a schematic plan view of the semiconductor device shown to (a). (A) is a figure which shows the cross-sectional structure of the semiconductor device in 4th Embodiment of this invention, (b) is a back view on the opposite side to the embedded insulating film side among the support substrates shown to (a). (A) is a figure which shows the cross-sectional structure of the semiconductor device in 5th Embodiment of this invention, (b) is a schematic plan view of the semiconductor device shown to (a). It is a schematic plan view of the semiconductor device in 6th Embodiment of this invention.

(First embodiment)
A first embodiment of the present invention will be described. FIG. 1A is a diagram illustrating a cross-sectional configuration of the semiconductor device according to the present embodiment, and FIG. 1B is a schematic plan view of the semiconductor device illustrated in FIG.

As shown in FIG. 1, the semiconductor device of the present embodiment sandwiches a P-type support substrate 10 having one surface, a buried insulating film 11 disposed on one surface of the support substrate 10, and the buried insulating film 11. And an SOI substrate 13 having an N ⁻ type semiconductor layer 12 disposed on the opposite side of the support substrate 10.

  The semiconductor layer 12 includes an isolation trench 40 that surrounds the first and second element formation regions 20 and 30 in the semiconductor layer 12 and that isolates and isolates the first and second element formation regions 20 and 30 from each other. Has been. In the present embodiment, the insulating isolation trench 40 is configured by embedding an insulator 42 such as an oxide or nitride in a trench 41 reaching the buried insulating film 11 from the surface of the semiconductor layer 12.

Further, predetermined semiconductor elements are respectively formed in the first and second element formation regions 20 and 30 in the semiconductor layer 12. In the present embodiment, a diode is formed in the first element formation region 20. Specifically, this diode includes a P-type layer 21 and an N ⁺ -type layer 22 selectively formed on the surface layer portion of the semiconductor layer 12, and a contact hole of the insulating film 50 disposed on the surface of the semiconductor layer 12. An anode electrode 23 that is electrically connected to the P-type layer 21 and a cathode electrode 24 that is electrically connected to the N ⁺ -type layer 22 via 51 are provided. Connected.

An NPN transistor is formed in the second element formation region 30. Specifically, the NPN transistor includes a P-type base region 31 formed in the surface layer portion of the semiconductor layer 12, an N ⁺ -type emitter region 32 formed in the surface layer portion of the base region 31, and a base region 31. A base electrode electrically connected to the base region 31 via an N ⁺ -type collector region 33 formed at a position spaced apart from the base region 31 and a contact hole 51 of the insulating film 50 disposed on the surface of the semiconductor layer 12 34, an emitter electrode 35 electrically connected to the emitter region 32, and a collector electrode 36 electrically connected to the collector region 33.

A P-type layer 60 and an N ⁻ -type layer 61 sandwiched between the P-type layers 60 are disposed between the first element forming region 20 and the second element forming region 30 in the semiconductor layer 12. A PNP junction is configured. In addition, a depletion layer between the P-type layer 60 and the N ⁻ -type layer 61 reaches the buried insulating film 11 from the surface of the semiconductor layer 12 when it is off, and partitions the first and second element formation regions 20 and 30. Is configured. In this embodiment, the P-type layer 60 corresponds to the first conductivity type layer of the present invention, and the N ⁻ -type layer 61 corresponds to the second conductivity type layer of the present invention.

In the present embodiment, the P-type layer 60 is formed so as to surround the first and second element formation regions 20 and 30, in other words, the insulating isolation trench 40, and reach the buried insulating film 11 from the surface of the semiconductor layer 12. Has been. The P-type layers 60 are separated from each other, and the semiconductor layer 12 constituting the N ⁻ -type layer 61 is positioned between the P-type layers 60, so that a PNP junction is formed. It is configured.

Further, in the present embodiment, the N ⁻ type layer 61 is interposed between the first and second element formation regions 20 and 30 via the contact hole 51 of the insulating film 50 disposed on the surface of the semiconductor layer 12. An electrically connected electrode 62 is provided. The electrode 62 is for emitting noise to the outside when noise is applied to the first element formation region 20.

Next, the operation when noise is applied to such a semiconductor device will be described. In the semiconductor device, a diode formed in the first element formation region 20 is connected to an external device, and a predetermined signal is output from the diode to the external device or connected to the diode. Noise is applied, for example, when potential fluctuation occurs. In this case, the noise is suppressed from propagating to the second element formation region 30 as follows. FIG. 2A is a diagram illustrating a state of the semiconductor device when a positive voltage noise is applied to the diode with respect to the NPN transistor, and FIG. 2B is a diagram illustrating the diode with respect to the NPN transistor. It is a figure which shows the state of a semiconductor device when the noise of a negative voltage is applied. In FIG. 2, a depletion layer formed between the P-type layer 60 on the NPN transistor side and the N ⁻ -type layer 61 is indicated by a broken line as a depletion layer 63, and the P-type layer 60 on the diode side and N ^A depletion layer formed between the −-type layer 61 and the depletion layer 64 is indicated by a broken line.

  Further, the fact that a positive voltage noise is applied to the diode with respect to the NPN transistor means that the isolation trench surrounding the first element formation region 20 with respect to the potential of the isolation trench 40 surrounding the second element formation region 30. That is, noise that increases the potential of 40 is applied. Similarly, when a negative voltage noise is applied to the diode with respect to the NPN transistor, the insulation isolation surrounding the first element formation region 20 with respect to the potential of the insulation isolation trench 40 surrounding the second element formation region 30. That is, noise that lowers the potential of the trench 40 is applied.

As shown in FIG. 2A, when a positive voltage noise is applied to the diode, the noise applied to the diode tends to propagate to the NPN transistor through the isolation trench 40. At this time, a reverse bias voltage is applied between the P-type layer 60 and the N ⁻ -type layer 61 on the NPN transistor side, and is formed between the P-type layer 60 and the N ⁻ -type layer 61. The depletion layer 64 is expanded. For this reason, the capacitance between the first and second element formation regions 20 and 30 is reduced, and noise is suppressed from propagating from the diode to the NPN transistor. That is, the propagation of noise between the first and second element formation regions 20 and 30 is suppressed. Then, noise remaining in the N ⁻ type layer 61 is emitted through the electrode 62.

Similarly, as shown in FIG. 2B, if negative voltage noise is applied to the diode, a reverse bias voltage is applied between the P-type layer 60 and the N ⁻ -type layer 61 on the diode side. As a result, the depletion layer 64 formed between the P-type layer 60 and the N ⁻ -type layer 61 spreads. For this reason, the capacitance between the first and second element formation regions 20 and 30 is reduced, and noise is suppressed from propagating from the diode to the NPN transistor. That is, the propagation of noise between the first and second element formation regions 20 and 30 is suppressed. Then, noise remaining in the N ⁻ type layer 61 is emitted through the electrode 62.

  Such a semiconductor device is manufactured as follows, for example. That is, first, the SOI substrate 13 is prepared, and the above diodes and NPN transistors are formed in the first and second element formation regions 20 and 30. Thereafter, trenches 41 surrounding the first and second element formation regions 20 and 30 are formed by etching or the like. Subsequently, a P-type layer 60 surrounding the trench 41 is formed by vapor phase diffusion or ion implantation. After that, the insulating isolation trench 40 is formed by embedding the insulator 42 in the trench 41, and the insulating film 50 and the electrodes 23, 24, 34 to 36, 62 are formed by a predetermined semiconductor manufacturing process. The device is manufactured. Of course, a diode or an NPN transistor can be formed in the first and second element formation regions 20 and 30 after the insulating isolation trench 40 is formed.

As described above, in the semiconductor device of this embodiment, the semiconductor layer 12 surrounds the first and second element formation regions 20 and 30, and reaches the buried insulating film 11 from the surface of the semiconductor layer 12. Layer 60 is formed. The N ⁻ -type layer 61 is positioned between the P-type layers 60, and a PNP junction is formed between the first and second element formation regions 20 and 30.

For this reason, when a positive voltage noise is applied to the diode, a reverse bias voltage is applied between the P-type layer 60 and the N ⁻ -type layer 61 on the NPN transistor side. And the depletion layer 63 formed between the N ⁻ type layer 61 spreads. Therefore, the capacitance between the first and second element formation regions 20 and 30 is reduced, and noise is suppressed from propagating to the NPN transistor. Further, when negative voltage noise is applied to the diode, a reverse bias voltage is applied between the P-type layer 60 and the N ⁻ -type layer 61 on the diode side. ^The depletion layer 64 formed between the negative electrode 61 and the mold layer 61 will spread. Therefore, the capacitance between the first and second element formation regions 20 and 30 is reduced, and noise is suppressed from propagating to the NPN transistor. As described above, in the semiconductor device of this embodiment, it is possible to suppress the propagation of noise between the first and second element formation regions 20 and 30.

(Second Embodiment)
A second embodiment of the present invention will be described. The semiconductor device of this embodiment is different from the first embodiment in that a trench is formed between the first and second element formation regions 20 and 30, a sidewall insulating film is disposed in the trench, and a P-type is formed in the trench. Since the layers are embedded and the other aspects are the same as in the first embodiment, the description thereof is omitted here. FIG. 3A is a diagram illustrating a cross-sectional configuration of the semiconductor device according to the present embodiment, and FIG. 3B is a schematic plan view of the semiconductor device illustrated in FIG.

As shown in FIG. 3, in the semiconductor device of the present embodiment, an N ⁻ type layer 60 is disposed between the first and second element formation regions 20 and 30, and a trench is formed in the N ⁻ type layer 60. 70 is formed. In the present embodiment, the trench 70 is formed so as to surround the first element formation region 20, and does not reach the buried insulating film 11, that is, the bottom surface of the trench 70 is located in the N ⁻ -type layer 60. It is configured. In the trench 70, a sidewall insulating film (not shown) is disposed on the sidewall, and a P-type layer 61 is embedded inside through the sidewall insulating film.

  That is, a NIPIN junction is formed between the first and second element formation regions 20 and 30 in the portion where the trench 70 is formed. The depletion layer formed between the PIN junctions reaches the buried insulating film 11 when the semiconductor device is off. Further, an electrode 62 electrically connected to the P-type layer 61 is provided on the surface of the semiconductor layer 12 through a contact hole 51 of the insulating film 50.

The depth of the P-type layer 61, i.e. the depth of the trench 70 is not limited as long as a depletion layer formed between the PIN junction reaches the buried insulating film 11, P-type layer 61 and the N ^- type The relationship with the impurity concentration of the layer 61 can be changed as appropriate. In the present embodiment, the N ⁻ type layer 60 corresponds to the first conductivity type layer of the present invention, and the P type layer 61 corresponds to the second conductivity type layer of the present invention.

  Even in such a semiconductor device, when noise is applied to the diode, the noise can be prevented from propagating to the NPN transistor. FIG. 4A is a diagram illustrating a state of the semiconductor device when a positive voltage noise is applied to the diode with respect to the NPN transistor. FIG. 4B is a diagram illustrating the state of the diode with respect to the NPN transistor. It is a figure which shows the state of a semiconductor device when the noise of a negative voltage is applied.

As shown in FIG. 4A, when a positive voltage noise is applied to the diode, the noise applied to the diode is reversed between the N ⁻ type layer 61 and the P type layer 60 on the NPN transistor side. A bias voltage will be applied, and the depletion layer 63 will spread. For this reason, it is suppressed that noise propagates from the diode to the NPN transistor. That is, the propagation of noise between the first and second element formation regions 20 and 30 is suppressed. Then, noise remaining in the P-type layer 61 is emitted through the electrode 62.

Similarly, as shown in FIG. 4B, if negative voltage noise is applied to the diode, a reverse bias voltage is applied between the N ^- type layer 61 and the P-type layer 60 on the diode side. As a result, the depletion layer 64 spreads. For this reason, it is suppressed that noise propagates from the diode to the NPN transistor. That is, the propagation of noise between the first and second element formation regions 20 and 30 is suppressed. Then, noise remaining in the P-type layer 61 is emitted through the electrode 62.

  Even in such a semiconductor device, since the NIPIN junction is formed between the first and second element formation regions 20 and 30, the same effects as those of the first embodiment can be obtained.

  Furthermore, in the present embodiment, by making the trench 70 a semiconductor device that does not reach the buried insulating film 11, the following effects can be obtained as compared with a semiconductor device in which the trench reaches the buried insulating film. That is, when a trench reaching the buried insulating film is formed, stress is applied to the buried insulating film by the trench, so that the life of the buried insulating film is reduced. However, in this embodiment, the trench 70 has a structure that does not reach the buried insulating film 11, and only the depletion layer formed between the PIN junctions reaches the buried insulating film 11. It is possible to suppress the propagation of noise between the first and second element formation regions 20 and 30 while suppressing the life of the eleventh element from decreasing.

(Third embodiment)
A third embodiment of the present invention will be described. The semiconductor device of this embodiment is obtained by forming a semiconductor element having a trench gate structure in the second element formation region 30 with respect to the second embodiment, and is otherwise the same as the second embodiment. The description is omitted here. FIG. 5A is a diagram illustrating a cross-sectional configuration of the semiconductor device according to the present embodiment, and FIG. 5B is a schematic plan view of the semiconductor device illustrated in FIG.

  As shown in FIG. 5, the semiconductor device of this embodiment includes a trench gate in the second element formation region 30 opposite to the second element formation region 30 where the diode is formed with the first element formation region 20 interposed therebetween. A semiconductor element having a structure is formed. In the present embodiment, this semiconductor element is configured as follows.

That is, in the semiconductor layer 12, a P-type channel formation region 81 is formed in the surface layer portion, and an N ⁺ -type source region 82 is adjacent to the N ⁺ -type source region 82 in the surface layer portion in the channel formation region 81. Thus, a P ⁺ -type contact region 83 is formed. Further, an N ⁺ type drain region 84 is formed in a surface layer portion of the semiconductor layer 12 at a position separated from the channel formation region 81. Furthermore, a trench 85 is formed in the semiconductor layer 12 so as to penetrate the channel formation region 81 located between the N ⁺ type source region 82 and the N ⁺ type drain region 84, and a gate (not shown) is formed on the side wall of the trench. An insulating film is disposed, and a gate electrode 86 is formed through the gate insulating film.

On the surface of the semiconductor layer 12, a source electrode (not shown) electrically connected to the N ⁺ type source region 82 and a P ⁺ type contact region 83 are electrically connected via a contact hole 51 formed in the insulating film 50. An electrode 87 to be connected and a drain electrode 88 electrically connected to the N ⁺ type drain region 84 are provided. Further, a planar gate electrode 89 connected to the gate electrode 86 is provided on the surface of the semiconductor layer 12 through a gate insulating film (not shown). A LOCOS oxide film 90 is formed between the channel formation region 81 and the N ⁺ type drain region 84.

In such a semiconductor element, when a positive voltage is applied to the gate electrodes 86 and 89, an inversion layer is formed in a portion facing the gate electrode 86 and a portion facing the planar gate electrode 89 in the P-type channel formation region 81. A current flows between the N ⁺ -type drain region 84 and the N ⁺ -type source region 82 through the inversion layer.

  In such a semiconductor device, when forming the trench 86 constituting the trench gate structure, the trench 70 formed between the first and second element formation regions 20 and 30 can be formed simultaneously. The effect similar to the said 2nd Embodiment can be acquired, without the process of forming only this.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. The semiconductor device of the present embodiment is obtained by forming a PNP junction on the support substrate 10 with respect to the first embodiment, and the other aspects are the same as those of the first embodiment, and thus description thereof is omitted here. FIG. 6A is a diagram showing a cross-sectional configuration of the semiconductor device according to the present embodiment, and FIG. 6B is a schematic back side view of the support substrate 10 shown in FIG. 6A on the side opposite to the buried insulating film 11 side. FIG. Although FIG. 6B is not a cross section, the P-type layer 10a is hatched for easy understanding.

  As shown in FIG. 6, in the semiconductor device of this embodiment, a PNP junction is formed on the support substrate 10. Specifically, on the support substrate 10, P-type layers 10 a reaching the buried insulating film 11 from the back surface and N-type layers 10 b reaching the buried insulating film 11 from the back surface are alternately arranged. The planar patterns of the P-type layer 10a and the N-type layer 10b are each square, and the P-type layer 10a and the N-type layer 10b form a checkered pattern. Further, one side of the P-type layer 10a and the N-type layer 10b is set to be equal to or smaller than the interval between the insulating isolation trenches 40 surrounding the first and second element formation regions 20 and 30, respectively. That is, a PNP junction is formed at a position facing the portion between the first and second element formation regions 20 and 30 in the support substrate 10.

  In such a semiconductor device, for example, when a positive voltage noise is applied to the diode, the noise may propagate to the support substrate 10 through the embedded insulating film 11. Is suppressed from being propagated from the N-type layer 10b to the P-type layer 10a by the depletion layer formed between the N-type layer 10b and the P-type layer 10a. Similarly, when a negative voltage noise is applied to the diode, the noise propagated to the support substrate 10 is changed from the P-type layer 10a to the N-type by the depletion layer formed between the P-type layer 10a and the N-type layer 10b. Propagation to the layer 10b is suppressed. Therefore, in such a semiconductor device, when noise is applied to the diode, the noise propagates to the NPN transistor through the support substrate 10, in other words, the noise flows from the first element formation region 20 to the support substrate 10. The effect similar to the said 1st Embodiment can be acquired, suppressing propagating to the 2nd element formation area 30 via.

  Note that the support substrate 10 of such a semiconductor device, for example, forms an N-type layer 10b in the support substrate 10 by ion implantation, forms a trench in the support substrate 10, and embeds the N-type layer 10b in the trench. It is manufactured by.

(Fifth embodiment)
A fifth embodiment of the present invention will be described. The semiconductor device of this embodiment is different from that of the first embodiment in that the pad is provided at a position adjacent to the first element formation region 20 and the other parts are the same as those of the first embodiment. Description is omitted. FIG. 7A is a diagram illustrating a cross-sectional configuration of the semiconductor device according to the present embodiment, and FIG. 7B is a schematic plan view of the semiconductor device illustrated in FIG.

  As shown in FIG. 7, the semiconductor device of this embodiment includes a pad 100 at a position adjacent to the first element formation region 20. The PNP junction is not present between the first element formation region 20 and the pad 100. Specifically, the P-type layer 60 is not formed outside the portion of the insulating isolation trench 40 located on the pad 100 side. When the pad 100 is disposed at a position adjacent to the first element formation region 20 as in the semiconductor device of this embodiment, a PNP junction should not be formed between the first element formation region 20 and the pad 100. You can also.

(Sixth embodiment)
A sixth embodiment of the present invention will be described. The semiconductor device of this embodiment is provided with a plurality of first element formation regions 20 adjacent to each other and a plurality of second element formation regions 30 adjacent to the first embodiment. Since other aspects are the same as those in the first embodiment, description thereof is omitted here. FIG. 8 is a schematic plan view of the semiconductor device according to the present embodiment.

As shown in FIG. 8, the semiconductor device of this embodiment includes a plurality of first element formation regions 20 adjacent to each other and a plurality of second element formation regions 30 adjacent to each other. . The semiconductor layer 12 is formed with a P-type layer 60 surrounding the entirety of the plurality of first element formation regions 20 and a P-type layer 60 surrounding the entirety of the plurality of second element formation regions 30. An N ⁻ type layer 61 is arranged between the P type layers 60.

  Even in such a semiconductor device, since a PNP junction is formed between the first element formation region 20 and the second element formation region 30, the same effect as in the first embodiment can be obtained.

(Other embodiments)
In each of the embodiments described above, the example in which the diode is formed in the first element formation region 20 and the NPN transistor is formed in the second element formation region 30 has been described. Of course, the first and second element formation regions 20 are formed. , 30 is not limited to this, and for example, elements such as LDMOS, resistors, capacitors, etc. can be formed in the first and second element formation regions 20, 30.

In the first and fourth to sixth embodiments, the first conductivity type layer is described as the P-type layer 60 and the second conductivity type layer is defined as the N ⁻ -type layer 61. The second conductivity type may be a P-type layer as well as a layer (N ⁻ -type layer). Similarly, in the second and third embodiments, the first conductivity type layer is described as the N ⁻ type layer 60 and the second conductivity type layer is defined as the P type layer 61. The second conductivity type layer may be an N-type layer (N ⁻ -type layer).

  Furthermore, in each of the above-described embodiments, the example in which the electrode 62 is provided between the first and second element formation regions 20 and 30 has been described. However, it is possible to adopt a configuration in which the electrode 62 is not provided.

  Moreover, although the said 2nd Embodiment demonstrated the example in which the trench 70 surrounding the 1st element formation area 20 was formed, the trench 70 surrounding the 2nd element formation area 20 may be formed, for example. Even in such a semiconductor device, since the NIPIN junction is formed between the first and second element formation regions 20 and 30, the same effects as those of the second embodiment can be obtained.

  Further, in the second embodiment, the P-type layer 61 can be buried directly in the trench 70 without arranging the sidewall insulating film on the sidewall of the trench 70. Even in such a semiconductor device, since an NPN junction is formed between the first and second element formation regions 20 and 30, the same effect as in the second embodiment can be obtained.

  In the third embodiment, the example in which the semiconductor element having the trench gate structure is formed in the second element formation region 30 has been described. Of course, the semiconductor element having the trench gate structure is formed in the first element formation region 20. You can also.

  Furthermore, in the fifth embodiment, the pad 100 has been described as an example of being disposed adjacent to the first element formation region 20. For example, when the surface of the semiconductor layer 12 includes a polycapacitor or the like. As for PNP junction, a PNP junction may not be formed in a portion between the first element formation region 20 and the polycapacitor. That is, when the pad 100, the element, or the like is disposed on the surface of the semiconductor layer 12, the PNP junction is not formed in the portion of the first element formation region 20 on the side where the pad 100, the element, etc. are disposed. It can be.

  And it can also be set as the semiconductor device which combined said each embodiment. For example, the second embodiment is combined with the fourth to sixth embodiments to form the trench 70 between the first and second element formation regions 20 and 30 and to dispose a sidewall insulating film on the sidewall of the trench 70. The P-type layer 60 can be embedded through the sidewall insulating film. Further, by combining the third embodiment with the fourth to sixth embodiments, a semiconductor element having a trench gate structure in the semiconductor layer 12 can be formed. Further, the PNP junction can be formed on the support substrate 10 by combining the fourth embodiment with the second, third, fifth, and sixth embodiments. When the fifth embodiment is combined with the second to fourth and sixth embodiments and the pad 100 is disposed adjacent to the first element formation region 20, the first element formation region 20 and the pad 100 are A PNP junction may not be formed between the two. Further, the sixth embodiment is combined with the second and third embodiments, and a plurality of first element formation regions 20 are arranged adjacent to each other, and a plurality of second element formation regions 30 are arranged adjacent to each other. In the case of forming the trench 70, the trench 70 surrounding the plurality of first element formation regions 20 is formed, a sidewall insulating film is disposed on the sidewall of the trench 70, and the P-type layer 60 is embedded via the sidewall insulating film. it can. Similarly, combining the sixth embodiment with the fourth and fifth embodiments, a plurality of first element formation regions 20 are arranged adjacent to each other, and a plurality of second element formation regions 30 are arranged adjacent to each other. In this case, the P-type layer 60 surrounding the plurality of first element formation regions 20 can be formed, and the P-type layer 60 surrounding the plurality of second element formation regions 30 can be formed.

  In each of the embodiments described above, the PNP junction is configured between the first and second element formation regions 20 and 30. For example, a PNP junction is configured between the first element formation regions 20. Alternatively, a PNP junction may be formed between the second element formation regions 30. That is, a PNP junction can be formed between two adjacent element formation regions.

DESCRIPTION OF SYMBOLS 13 SOI substrate 20 1st element formation area 30 2nd element formation area 40 Insulation isolation trench 60 P-type layer 61 N ^- type layer 63, 64 Depletion layer

Claims (5)

A support substrate (10) having one surface, a buried insulating film (11) disposed on the one surface of the support substrate (10), and the support substrate (10) sandwiching the buried insulating film (11). Of the semiconductor substrate (13) having the semiconductor layer (12) disposed on the opposite side, the semiconductor layer (12) includes the first and second element formation regions (20, 20) in the semiconductor layer (12). 30) and insulating isolation trenches (40) for insulatingly isolating the first and second element formation regions (20, 30) from each other, and forming the first and second element formation regions (20, 30). In a semiconductor device in which a semiconductor element is formed in
Of the semiconductor elements formed in the first and second element formation regions (20, 30), the semiconductor element formed in the first element formation region (20) is connected to an external device,
Between the first element formation region (20) and the second element formation region (30), a first conductivity type layer (60) and a second conductivity type sandwiched between the first conductivity type layers (60). A layer (61) is disposed between the first and second conductivity type layers (60, 61) and reaches the buried insulating film (11) from the surface of the semiconductor layer (12) when turned off. The semiconductor device is characterized in that a depletion layer (63, 64) for partitioning the first and second element formation regions (20, 30) is formed.   The semiconductor layer (12) surrounds the insulating isolation trench (40), reaches the buried insulating film (11) from the surface of the semiconductor layer (12), and is separated from each other. The semiconductor device according to claim 1, wherein a first conductivity type layer (60) is formed, and the second conductivity type layer (61) is disposed between the first conductivity type layers (60).   The first conductivity type layer (60) is disposed between the first and second element formation regions (20, 30), and a trench (70) is formed in the first conductivity type layer (60). 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed and the second conductivity type layer (61) is embedded in the trench (70). 3.   The trench (70) is provided with an insulating film on a side wall, and the second conductivity type layer (61) is embedded through the insulating film. Semiconductor device.   5. The semiconductor device according to claim 3, wherein a semiconductor element having a trench gate structure is formed in at least one of the first and second element formation regions (20, 30).

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