CN110416302B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN110416302B CN110416302B CN201810403638.8A CN201810403638A CN110416302B CN 110416302 B CN110416302 B CN 110416302B CN 201810403638 A CN201810403638 A CN 201810403638A CN 110416302 B CN110416302 B CN 110416302B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 73
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 66
- 239000002184 metal Substances 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims description 35
- 239000000463 material Substances 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 19
- 238000005468 ion implantation Methods 0.000 claims description 13
- 238000001312 dry etching Methods 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 257
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 19
- 229910052760 oxygen Inorganic materials 0.000 abstract description 19
- 239000001301 oxygen Substances 0.000 abstract description 19
- 239000011229 interlayer Substances 0.000 abstract description 14
- 238000005137 deposition process Methods 0.000 description 9
- 238000002955 isolation Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
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- 230000015572 biosynthetic process Effects 0.000 description 3
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- -1 boron ions Chemical class 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
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- 229910052698 phosphorus Inorganic materials 0.000 description 1
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- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
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Abstract
The invention provides a semiconductor device and a method of manufacturing the same. According to the manufacturing method of the semiconductor device and the semiconductor device, the groove terminal ring structure is adopted to replace field oxygen to carry out terminal protection ring arrangement, so that the electrostatic protection structure can be arranged on the dielectric layer with the reduced thickness to replace the arrangement mode that the electrostatic protection structure carries the field oxygen, the height difference between the top of the electrostatic protection structure and the epitaxial layer is reduced, the damage to the interlayer dielectric layer formed on the electrostatic protection structure in the process of forming the interconnection structure comprising the metal plug and the metal layer is avoided, and the reliability of product parameters and performance is improved.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a manufacturing method thereof.
Background
DMOS is a power MOSFET widely used in the semiconductor field, and its gate breakdown performance when applied in a high voltage environment is a problem of great concern to those skilled in the semiconductor art.
In order to protect the gate oxide layer from electrostatic breakdown, adding an electrostatic discharge (ESD) protection structure to the DMOS device is a widely adopted technical approach. A typical electrostatic protection structure adopts Field Oxide (FOX) as a terminal isolation ring, and carries the field oxide to arrange a polysilicon electrostatic protection structure. The polysilicon electrostatic protection structure is provided with a plurality of diodes which are connected in parallel through an injection process, and in the manufacturing process of the semiconductor device, the N end and the P end of the polysilicon electrostatic protection structure are respectively connected with the DMOS source electrode and the grid electrode, so that the overvoltage protection effect between the source electrode and the grid electrode of the DMOS device is realized.
However, since the polysilicon electrostatic protection structure carries a field oxide arrangement, it requires a special field oxide process. In order to effectively ensure the self-aligned implantation requirement of a well (well) process, the field oxygen thickness has higher requirement, so that the step difference between the electrostatic protection structure and other areas is increased. Referring to fig. 1A and 1B, a schematic structural diagram of a semiconductor device formed by a typical manufacturing process is shown, wherein fig. 1A shows a schematic plan view of the semiconductor device, and the semiconductor device includes a cell region 11, a terminal ring region 12 and an electrostatic protection structure 13. As shown in fig. 1B, which is a cross-sectional view of an electrostatic protection structure, a semiconductor substrate 100 is formed with a field oxide 101, which generally requires a thickness greater than that required for well self-alignment
An electrostatic protection structure 102 is formed in the fieldOn the oxygen 101, a height difference T1 is formed between the top of the electrostatic protection structure 102 and the surface of the semiconductor substrate 100, wherein T1 is
The above. In the subsequent process of forming a contact metal plug on the semiconductor substrate 100, the interlayer dielectric layer on the electrostatic protection structure 13 is thinner than the interlayer dielectric layer on the cell region 11
In the process of forming the metal interconnection structure including the metal plug and the metal layer, the processes of metal chemical mechanical polishing and etching are often involved, so that the interlayer dielectric layer is not sufficiently protected against the electrostatic protection structure, and the polysilicon layer on the electrostatic protection structure 13 is easily lost, thereby reducing the reliability of product parameters and performance.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a semiconductor substrate of a first doping type, and forming an epitaxial layer of the first doping type on the semiconductor substrate of the first doping type, wherein the epitaxial layer of the first doping type comprises a cell region and a terminal region;
forming a patterned dielectric layer on the epitaxial layer of the first doping type, wherein the patterned dielectric layer exposes a region, to be formed with a groove, in the epitaxial layer of the first doping type;
etching the epitaxial layer of the first doping type by taking the patterned dielectric layer as a mask to form the groove, wherein the groove comprises a grid groove positioned in the primitive cell region and a protection ring groove positioned in the terminal region;
forming a gate dielectric layer covering the bottom and the side wall of the groove and a gate material filling the groove, wherein the gate material exposes the patterned dielectric layer;
forming an electrostatic protection structure layer stacked on the patterned dielectric layer, wherein the electrostatic protection structure layer is intended to form an electrostatic protection structure;
removing the patterned dielectric layer outside the lower part of the electrostatic protection structure layer;
and forming a well region of the second doping type, a source region of the first doping type and the electrostatic protection structure in the cell region.
Illustratively, the dielectric layer comprises a silicon oxide layer formed using TEOS deposition.
Illustratively, the electrostatic protection structure layer includes a polysilicon layer.
Illustratively, the step of removing the patterned dielectric layer outside the electrostatic protection structure layer employs a dry etching process, wherein the dry etching process etches the patterned dielectric layer with the electrostatic protection structure layer as a mask.
Illustratively, the electrostatic protection structure includes at least two second doping type layers and at least two first doping type layers, and the first doping type layers and the second doping type layers are alternately arranged in a horizontal direction.
For example, the step of forming the well region of the second doping type and the source region of the first doping type in the cell region and the electrostatic protection structure includes:
performing second doping type ion implantation, forming a well region of a second doping type in the epitaxial layer of the first doping type, and forming a second doping type layer in the electrostatic protection layer;
forming a patterned mask layer, wherein the patterned mask layer exposes a source region of the first doping type to be formed in the epitaxial layer of the first doping type and a region of the electrostatic protection layer to be formed with the first doping type;
performing first doping type ion implantation to form a source region of the first doping type and the first doping type layer;
and removing the patterned mask layer.
After the step of etching the epitaxial layer of the first doping type with the patterned dielectric layer as a mask to form a trench and before the step of forming the electrostatic protection structure layer, a step of thinning the patterned dielectric layer is further included.
Illustratively, after the step of forming the well region and the source region of the first doping type in the cell region and the electrostatic protection structure, a step of forming a metal interconnection structure is further included.
Illustratively, the first doping type is N-type, and the second doping type is P-type.
The present invention also provides a semiconductor device including:
a semiconductor substrate of a first doping type;
the epitaxial layer of the first doping type is positioned on the semiconductor substrate of the first doping type and comprises a cell region and a terminal region;
the grid groove, the well region of the second doping type and the source region of the first doping type are positioned in the primitive cell region;
a guard ring trench in the terminal, the gate and guard ring trenches each including a cover gate dielectric layer at a bottom and sidewalls thereof and being filled with a gate material; and
and the electrostatic protection structure positioned on the epitaxial layer of the first doping type is insulated from the epitaxial layer of the first doping type through a dielectric layer.
According to the manufacturing method of the semiconductor device and the semiconductor device, the groove terminal ring structure is adopted to replace field oxygen to carry out terminal protection ring arrangement, so that the electrostatic protection structure can be arranged on the dielectric layer with the reduced thickness to replace the arrangement mode that the electrostatic protection structure carries the field oxygen, the height difference between the top of the electrostatic protection structure and the epitaxial layer is reduced, the damage to the interlayer dielectric layer formed on the electrostatic protection structure in the process of forming the interconnection structure comprising the metal plug and the metal layer is avoided, and the reliability of product parameters and performance is improved. Meanwhile, in the manufacturing method of the semiconductor device, the terminal protection ring is arranged by adopting the trench terminal ring structure to replace the field oxygen, so that the step of forming the field oxygen is omitted, and the process flow is simplified.
Drawings
The following drawings of the invention are included as part of the present invention to provide an understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
fig. 1A and 1B are schematic structural views of a semiconductor device;
FIGS. 2A-2H are schematic structural views of a semiconductor device formed in a method of fabricating a semiconductor device according to an embodiment of the present invention;
fig. 3 is a schematic flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention.
In the following description, a detailed description is given to illustrate the method and semiconductor device of the present invention in order to provide a thorough understanding of the present invention. It is apparent that the invention is not limited in its application to the details of the particular embodiments known to those skilled in the semiconductor arts. The following detailed description of the preferred embodiments of the invention, however, the invention can be practiced otherwise than as specifically described.
It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular is intended to include the plural unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Exemplary embodiments according to the present invention will now be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity, and the same elements are denoted by the same reference numerals, and thus the description thereof will be omitted.
Example one
A method for manufacturing a semiconductor device according to the present invention is exemplarily illustrated with reference to fig. 2A to 2H and fig. 3, wherein fig. 2A to 2H are schematic structural diagrams of a semiconductor device formed in a method for manufacturing a semiconductor device according to an embodiment of the present invention; fig. 3 is a schematic flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Referring to fig. 2A, a first doping type semiconductor substrate 200 is provided, and a first doping type epitaxial layer 201 is formed on the first doping type semiconductor substrate 200, where the first doping type epitaxial layer 201 includes a cell region and a terminal region, and the terminal region surrounds the cell region.
Specifically, the semiconductor substrate 200 of the first doping type may be at least one of the following materials: si, ge, siGe, siC, siGeC, inAs, gaAs, inP, inGaAs, or other III/V compound semiconductors, as well as multilayer structures comprising these semiconductors, or silicon on dielectric (SOI), silicon on dielectric (SSOI), silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI), and germanium on dielectric (GeOI). In the present embodiment, the semiconductor substrate 200 of the first doping type is silicon.
It should be noted that, in the present specification, the first doping type and the second doping type generally refer to P type or N type, wherein the first doping type and the second doping type are opposite, for example, the first doping type is one of P type, low doping P-type, and high doping P + type, and the second doping type is one of N type, low doping N-type, and high doping N + type. Or conversely, the first doping type is one of an N type, a low-doping N-type and a high-doping N + type, and the second doping type is one of a P type, a low-doping P-type and a high-doping P + type.
Illustratively, the first type of semiconductor substrate is an N-type low-doped substrate, i.e., an N-substrate, with a doping concentration of 1 × 10 14 /cm 3 -2×10 14 /cm 3 。
The method for forming the epitaxial layer 201 of the first doping type on the semiconductor substrate 200 includes any method known to those skilled in the art, such as ion-doped vapor phase epitaxy. In this embodiment, the first type semiconductor substrate is an N-type low-doped substrate, that is, an N-type substrate, and the first type epitaxial layer is an N-type low-doped epitaxial layer, that is, an N-type epitaxial layer. The thickness and the resistivity of the epitaxial layer 201 of the first doping type influence the voltage endurance capability of the device, and the thicker the epitaxial layer 201 of the first doping type is, the higher the resistivity is, and the higher the voltage endurance capability of the device is. Illustratively, in the present embodiment, the voltage resistance of the formed DMOS semiconductor device is required to be between 20V and 150V, and the first doping type epitaxial layer 201 has a thickness of 4 μm to 15 μm and a resistivity of 0.2 ohm-cm to 3 ohm-cm.
Next, with continued reference to fig. 2A, a patterned dielectric layer 202 is formed on the epitaxial layer 201 of the first doping type, the patterned dielectric layer 202 exposing the regions where the trenches are to be formed.
The method of forming the patterned dielectric layer comprises: performing a deposition process, and covering a dielectric material layer on the surface of the epitaxial layer of the first doping type; performing a photoetching process to form a patterned photoresist layer covering the surface of the dielectric material layer; performing an etching process by taking the patterned photoresist layer as a mask to form the patterned dielectric layer; and removing the patterned photoresist layer.
In the invention, a patterned dielectric layer is adopted to cover a region to be formed with an electrostatic protection structure, wherein the formed trench comprises a grid trench and a protection ring trench, the protection ring trench replaces field oxygen in the prior art to arrange a terminal protection ring, so that the electrostatic protection structure carrying dielectric layer formed subsequently replaces the electrostatic protection structure carrying field oxygen in the prior art to form, the thickness of the dielectric layer can be reduced, the height difference between the electrostatic protection structure and the surface of a semiconductor substrate is reduced, and the damage to an ESD structure in the process of forming a metal interconnection structure comprising a metal contact hole and a metal layer subsequently is avoided. Referring to fig. 2B, a schematic plan view is shown after forming a patterned dielectric layer on the epitaxial layer of the first doping type. Dielectric layer 202 formed on the epitaxial layer (not shown) of the first doping type exposes the region where trench 203 (including guard ring trench 2031 and gate trench 2 032) is to be formed, where guard ring trench 2031 is provided as a termination ring structure surrounding the cell region. The formation of the trench 203 will be further illustrated in subsequent process steps.
Meanwhile, the dielectric layer 202 serves as an insulating layer carried by the electrostatic protection structure on one hand and can serve as a mask for etching the epitaxial layer of the first doping type to form the groove on the other hand, so that the existing process step for forming the field oxide is reduced, and meanwhile, the mask forming step for etching the groove and the forming step of the dielectric layer are combined into the same step, and the process flow is greatly simplified.
Illustratively, the patterned dielectric layer is silicon oxide formed using a TEOS deposition process. The method for forming silicon oxide may be a method well known in the art and will not be described herein. It should be understood that the embodiment of using TEOS deposition process to form silicon oxide as the dielectric layer is merely exemplary, and any dielectric layer material with insulating dielectric properties, such as silicon oxide formed by thermal oxidation or silicon oxide formed by other chemical vapor deposition methods, may be used in the present invention.
Next, referring to fig. 2C, the epitaxial layer 201 with the first doping type is etched using the patterned dielectric layer 202 as a mask to form a trench 203, where the trench 203 includes a gate trench 2032 located in the cell region and a guard ring trench 2031 located in the termination region.
The gate trench 2032 located in the cell region is intended to form a gate structure of a transistor of the cell region, and the guard ring trench 2031 located in the terminal region is intended to form a terminal guard ring. The trench protection ring structure is adopted to replace field oxygen in the prior art as a protection ring, so that the field oxygen forming step is omitted, on one hand, the process steps are reduced, on the other hand, the dielectric layer at the bottom of the electrostatic protection structure is minimized under the condition that the terminal region is isolated, the height difference between the electrostatic protection structure and the surface of the semiconductor substrate is reduced, and the damage to the ESD structure in the subsequent metal contact hole and metal layer forming process is avoided. Meanwhile, the forming step of the terminal protection ring is combined with the existing step of forming the grid structure, so that the process steps are further reduced, and the process cost is saved.
For example, the step of etching the epitaxial layer 201 of the first doping type by using the patterned dielectric layer 202 as a mask to form the trench 203 adopts a dry etching process, which is well known to those skilled in the art and will not be described herein again.
Next, referring to fig. 2D, a gate dielectric layer 204 covering the bottom and sidewalls of the trench 203 and a gate material 205 filling the trench 203 are formed, the gate material 205 exposing the patterned dielectric layer 202.
Illustratively, the step of forming the gate dielectric layer and the gate material includes: performing a thermal oxidation process to form a thermal oxide layer on the bottom and the sidewall of the trench 203, where the thermal oxide layer is a gate dielectric layer; performing a deposition process to form a gate material layer covering the first doping type epitaxial layer; and performing a chemical mechanical polishing process to remove the gate material layer beyond the top of the patterned dielectric layer to form a gate material with the top level with the patterned dielectric layer, wherein the gate material exposes the patterned dielectric layer. It should be understood that the method for forming the gate material in the present embodiment is only exemplary, and after covering the first doping type epitaxial layer, other process steps such as an etching step may be performed to form the gate material exposing the patterned dielectric layer; the thickness of the gate material formed for this purpose on the first doping type epitaxial layer may be equal to or less than the thickness of the patterned dielectric layer.
Illustratively, the gate material 205 is polysilicon.
Next, referring to fig. 2E, an electrostatic protection structure layer 206 is formed, the electrostatic protection structure layer 206 is stacked on the patterned dielectric layer 202.
Illustratively, the step of forming the electrostatic protection structure layer 206 includes: performing a deposition process to form an electrostatic protection structure material layer covering the dielectric layer and the gate material; performing a photoetching process to form a patterned photoresist layer covering a region where the electrostatic protection structure is to be formed; and etching the electrostatic protection structure material layer by taking the patterned photoresist layer as a mask to form an electrostatic protection structure layer.
Illustratively, the electrostatic protection structure layer 206 is a polysilicon layer.
Illustratively, after the step of etching the epitaxial layer of the first doping type by using the patterned dielectric layer as a mask to form a trench and before the step of forming the electrostatic protection structure layer, the method further comprises a step of thinning the patterned dielectric layer. Illustratively, the thinning step thins the patterned dielectric layer to
The isolation effect can be satisfied at this thickness. Illustratively, the step of thinning the patterned dielectric layer includes a dry etching process. The dry etching process may be one of ordinary skill in the artThe processes known to the skilled person are not described in detail here.
Before the electrostatic protection structure layer is formed, the patterned dielectric layer is thinned by adopting a dry etching process, so that the height difference between the top of the subsequently formed electrostatic protection structure and the surface of the first doping type epitaxial layer is further reduced, the damage to the ESD structure in the subsequent metal contact hole and metal layer forming process is further avoided, and the reliability of the semiconductor device is improved. In the thinning step, the thinned thickness of the patterned dielectric layer can be any, and can be selected by a person skilled in the art according to needs.
Next, referring to fig. 2F, the patterned dielectric layer 202 outside under the electrostatic protection structure layer 206 is removed.
Illustratively, the step of removing the patterned dielectric layer 202 outside the portion under the electrostatic protection structure layer 206 employs dry etching. The dry etching etches the patterned dielectric layer 202 using the electrostatic protection structure layer 206 as a mask. In the step, a dry etching process is adopted, and the electrostatic protection structure layer is used as a mask, so that the photoetching process can be reduced, the process steps are further reduced, and the process flow is simplified.
Next, referring to fig. 2G, a well region 207 and a source region 208 of the first doping type located in the cell region and an electrostatic protection structure are formed.
Illustratively, the electrostatic protection structure includes two second doping type layers 209 and a first doping type layer 210, wherein the first doping type layer 210 and the second doping type layers 209 are alternately arranged in parallel.
For example, the step of forming the well region 207 and the source region 208 of the first doping type in the cell region and the electrostatic protection structure includes: performing second doping type ion implantation, forming a well region of a second doping type in the epitaxial layer of the first doping type, and doping the electrostatic protection structural layer to form a second doping type layer; forming a patterned mask layer, wherein the patterned mask layer exposes a source region of a first doping type to be formed in the epitaxial layer of the first doping type and an area of the electrostatic protection layer to be formed with the first doping type; performing first doping type ion implantation, forming a source region of a first doping type in the epitaxial layer of the first doping type, and forming a first doping type layer in the electrostatic protection layer; and removing the patterned mask layer. In the step, the second doping type ion implantation is self-aligned ion implantation, and common implantation is performed without a mask, so that one step of photoetching step is reduced; the ion implantation dosage of the first doping type ion implantation is higher than that of the second doping type ion implantation, so that the first doping type layer is directly inverted in the formed second doping type layer after the second doping type ion implantation is performed.
In this embodiment, the first doping type is N-type doping, and the second doping type is P-type doping. The ions implanted by the second doping type ions are boron ions, the implanted energy range is 20 Kev-100 Kev, and the implanted dosage range is 1.0E 13 /cm 2 ～1.0E 14 /cm 2 . The first doping type ion implantation is performed with phosphorus ion or arsenic ion, the implantation energy is 20 Kev-120 Kev, and the implantation dosage is 1.0E 15 /cm 2 ～1.0E 16 /cm 2 。
In the step, the first doping type layer and the second doping type layer in the electrostatic protection structure are formed in the process of forming the source and the drain, so that the process steps are reduced. The first doping type layers and the second doping type layers in the electrostatic protection structure are alternately arranged in parallel, so that a plurality of diodes connected in parallel are formed. It is to be understood that the embodiment using the formation of two first doping type layers and two second doping type layers is merely exemplary, and any arrangement of the first doping type layers and the second doping type layers that form a plurality of parallel diode structures is suitable for the present invention.
Based on the semiconductor manufacturing method, the field oxygen isolation is replaced by the protection ring trench isolation, so that the process steps of forming the field oxygen are reduced; meanwhile, because the protection ring trench isolation is adopted to replace the field oxide isolation, thick field oxide does not need to be arranged in the process of forming the well region and the source drain region, thereby being capable ofThe height difference between the top of the electrostatic protection structure and the surface of the epitaxial layer of the first doping type on the semiconductor substrate is reduced by reducing the thickness of the dielectric layer at the bottom of the electrostatic protection structure, so that the damage to the electrostatic protection structure in the subsequent process of forming a contact metal plug and a metal layer is avoided, and the reliability of product performance and parameters is improved. As shown in fig. 2F, the height difference between the top of the electrostatic protection structure formed according to this embodiment and the surface of the first doping type epitaxial layer is T2 (the sum of the thickness of the electrostatic protection structure layer and the thickness of the patterned dielectric layer), since the terminal trench guard ring (the gate dielectric layer 204 and the gate material 205 filling the guard ring trench 2031) is provided and the electrostatic protection structure (including the first doping type layer 210 and the second doping type layer 209) is provided on the patterned dielectric layer 202, it is not necessary to carry field oxide on the electrostatic protection structure (including the first doping type layer 210 and the second doping type layer 209), and the height difference T2 between the top of the electrostatic protection structure and the surface of the first doping type epitaxial layer can be reduced by reducing the thickness of the dielectric layer 202, so as to avoid damage to the electrostatic protection structure during the subsequent formation of the contact metal plug and the metal layer, and improve the reliability of the product. In one example, the thickness of the patterned dielectric layer is set at
The thickness of the electrostatic protection structure layer is set as
The height difference T2 between the top of the electrostatic protection structure and the surface of the first doping type epitaxial layer is
Compared with the prior art, T1 in figure 1 is
In this way, the height difference between the top of the electrostatic protection structure and the surface of the first doping type epitaxial layer is improved at least
The protection of the interlayer dielectric layer in the subsequent manufacturing process to the electrostatic protection structure is obviously improved.
Referring to fig. 2H, a schematic structural diagram of a semiconductor device forming an interconnect structure over an electrostatic protection structure and a source region in a method of manufacturing a semiconductor device according to an embodiment of the present invention is shown. The interconnect structure includes a contact metal plug and a metal layer. The step of forming an interconnect structure including a contact metal plug 211 and a metal layer 212 located over the contact metal plug 211 over the source region 208 of the first doping type and the electrostatic protection structure (including the first doping type layer 210 and the second doping type layer 209) includes: performing a deposition process to form an interlayer dielectric layer 213 covering the epitaxial layer of the first doping type and the electrostatic protection structure; performing an etching process to form a contact via hole in the interlayer dielectric layer, wherein the contact via hole penetrates through the source region 208 of the first doping type and extends to the second doping type well region 207, and penetrates through the electrostatic protection structure layer 206 (including the first doping type layer 210 and the second doping type layer 209); performing a deposition process to form a metal material for filling the contact through hole and covering the surface of the interlayer dielectric layer; performing a chemical mechanical polishing or etching process to remove the metal material outside the via hole to form a metal plug 211; performing a deposition process to form a metal material covering the surface of the metal plug 211 and the surface of the interlayer dielectric layer 213; an etching process is performed to form a metal layer 212.
In the steps of removing the metal material outside the through hole by performing the chemical mechanical polishing or etching process and forming the metal layer by performing the etching process, damage to the interlayer dielectric layer 213 is often caused, and the invention reduces the height difference T2 between the top of the electrostatic protection structure and the surface of the epitaxial layer of the first doping type, thereby increasing the thickness T3 of the interlayer dielectric layer on the surface of the dielectric protection layer 213, so that the surface chemical continuous polishing or etching process damages the interlayer dielectric layer on the surface of the dielectric layer, and the reliability of the product is improved.
Referring to fig. 3, a schematic flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present invention is shown. Specifically, the step of forming the semiconductor device includes:
executing step S1: providing a semiconductor substrate of a first doping type, and forming an epitaxial layer of the first doping type on the semiconductor substrate of the first doping type, wherein the epitaxial layer of the first doping type comprises a cell region and a terminal region;
executing the step S2: forming a patterned dielectric layer on the epitaxial layer of the first doping type, wherein the patterned dielectric layer exposes a region, to be formed with a groove, in the epitaxial layer of the first doping type;
and executing the step S3: etching the epitaxial layer of the first doping type by taking the patterned dielectric layer as a mask to form the groove, wherein the groove comprises a grid groove positioned in the cell area and a protection ring groove positioned in the terminal area;
and executing the step S4: forming a gate dielectric layer covering the bottom and the side wall of the groove and a gate material filling the groove, wherein the gate material exposes the patterned dielectric layer;
executing the step S5: forming an electrostatic protection structure layer stacked on the patterned dielectric layer, wherein the electrostatic protection structure layer is intended to form an electrostatic protection structure;
step S6 is executed: removing the patterned dielectric layer outside the lower part of the electrostatic protection structure layer;
step S7 is executed: and forming a well region of the second doping type, a source region of the first doping type and the electrostatic protection structure in the cell region.
Example two
The invention also provides a semiconductor device manufactured by the manufacturing method of the semiconductor device according to the first embodiment. A semiconductor device of the present invention is schematically illustrated with reference to fig. 2H.
Referring to fig. 2H, the semiconductor device includes a semiconductor substrate 200 of a first doping type;
an epitaxial layer 201 of the first doping type located on the semiconductor substrate 200 of the first doping type, the epitaxial layer of the first doping type including a cell region and a terminal region, the terminal region surrounding the cell region;
a gate trench 2032, a well region 207 and a source region 208 of the first doping type in the cell region, a guard ring trench 2031 in the termination region, the bottom and sidewalls of the gate trench 2032 and guard ring trench 2031 each comprising a covering gate dielectric layer 204, and the gate trench 2032 and guard ring trench 2031 each being filled with a gate material 205; and
and the electrostatic protection structure is positioned on the epitaxial layer 201 of the first doping type and is insulated from the epitaxial layer 201 of the first doping type by a dielectric layer 202, and the electrostatic protection structure comprises an electrostatic structure layer 206.
Specifically, the semiconductor substrate 200 of the first doping type may be at least one of the following materials: si, ge, siGe, siC, siGeC, inAs, gaAs, inP, inGaAs, or other III/V compound semiconductors, as well as multilayer structures comprising these semiconductors, or silicon on dielectric (SOI), silicon on dielectric (SSOI), silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI), and germanium on dielectric (GeOI). In the present embodiment, the semiconductor substrate 200 of the first doping type is silicon.
It should be noted that, the first doping type and the second doping type in this specification generally refer to P-type or N-type, where the first doping type and the second doping type are opposite, for example, the first doping type is one of P-type, low-doping P-type, and high-doping P + type, and the second doping type is one of N-type, low-doping N-type, and high-doping N + type. Or conversely, the first doping type is one of an N type, a low-doping N-type and a high-doping N + type, and the second doping type is one of a P type, a low-doping P-type and a high-doping P + type.
Illustratively, the first type of semiconductor substrate is an N-type low-doped substrate, i.e., an N-substrate, with a doping concentration of 1 × 10 14 /cm 3 ～2×10 14 /cm 3 。
Illustratively, the first type of semiconductor substrate is an N-type low-doped substrate, i.e., an N-substrate, and the first type-doped first doping type epitaxial layer is an N-type low-doped first doping type epitaxial layer, i.e., an N-first doping type epitaxial layer. The thickness and the resistivity of the epitaxial layer 201 of the first doping type can affect the voltage endurance capability of the device, and the thicker the epitaxial layer 201 of the first doping type is, the higher the resistivity is, and the higher the voltage endurance capability of the device is. Illustratively, in the present embodiment, the formed DMOS semiconductor device withstand voltage requires that the first doping type epitaxial layer 201 has a thickness of 4 μm to 15 μm and a resistivity of 0.2 to 3ohm.
Illustratively, the patterned dielectric layer 202 is a silicon oxide layer formed using a TEOS deposition process.
Illustratively, the electrostatic protection structure layer 206 is a polysilicon layer.
Illustratively, the electrostatic protection structure comprises at least two second doping type layers 209 and at least two first doping type layers 210, wherein the first doping type layers 210 and the second doping type layers 209 are alternately arranged in the horizontal direction.
Illustratively, the semiconductor device further comprises an interconnect structure located over the epitaxial layer 201 of the first doping type forming an electrical connection with the source region 208 of the first doping type and the electrostatic protection structure (comprising the first doping type layer 210 and the second doping type layer 209). The interconnect structure includes a contact metal plug 211 and a metal layer 212 located above the contact metal plug 211.
The terminal protection ring is arranged by adopting the groove terminal ring structure to replace field oxygen, so that the electrostatic protection structure can be arranged on the dielectric layer to replace the mode that the electrostatic protection structure carries the field oxygen, and compared with the field oxygen thickness under the mode that the field oxygen is carried, the dielectric layer thickness is greatly reduced compared with the field oxygen thickness, thereby reducing the height difference between the top of the electrostatic protection structure and the epitaxial layer, avoiding the damage to the interlayer dielectric layer formed on the electrostatic protection structure in the process of forming the interconnection structure comprising the metal plug and the metal layer, and further improving the reliability of product parameters and performance.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, all of which fall within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (7)
1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate of a first doping type, and forming an epitaxial layer of the first doping type on the semiconductor substrate of the first doping type, wherein the epitaxial layer of the first doping type comprises a cell region and a terminal region;
forming a patterned dielectric layer on the epitaxial layer of the first doping type, wherein the patterned dielectric layer exposes a region, to be formed with a groove, in the epitaxial layer of the first doping type, and the dielectric layer comprises a silicon oxide layer formed by TEOS deposition;
etching the epitaxial layer of the first doping type by taking the patterned dielectric layer as a mask to form the groove, wherein the groove comprises a grid groove positioned in the cell area and a protection ring groove positioned in the terminal area;
forming a gate dielectric layer covering the bottom and the side wall of the groove and a gate material filling the groove, wherein the gate material exposes the patterned dielectric layer;
forming an electrostatic protection structure layer stacked on the patterned dielectric layer, wherein the electrostatic protection structure layer is intended to form an electrostatic protection structure;
removing the patterned dielectric layer outside the lower part of the electrostatic protection structure layer;
forming a well region of a second doping type, a source region of a first doping type and the electrostatic protection structure in the cell region;
after the step of etching the epitaxial layer of the first doping type by taking the patterned dielectric layer as a mask to form a groove and before the step of forming the electrostatic protection structure layer, the method also comprises the step of thinning the patterned dielectric layer.
2. The method of claim 1, wherein the electrostatic protection structure layer comprises a polysilicon layer.
3. The method of claim 1, wherein the step of removing the patterned dielectric layer outside of the electrostatic protection structure layer below employs a dry etching process, wherein the dry etching process etches the patterned dielectric layer with the electrostatic protection structure layer as a mask.
4. The method of claim 1, wherein the electrostatic protection structure comprises at least two second doping type layers and at least two first doping type layers, the first and second doping type layers being alternately arranged in a horizontal direction.
5. The method of claim 4, wherein the step of forming the well region of the second doping type and the source region of the first doping type and the electrostatic protection structure in the cell region comprises:
performing second doping type ion implantation, forming a well region of a second doping type in the epitaxial layer of the first doping type, and forming a second doping type layer in the electrostatic protection layer;
forming a patterned mask layer, wherein the patterned mask layer exposes a source region of the first doping type to be formed in the epitaxial layer of the first doping type and an area of the electrostatic protection layer to be formed with the first doping type;
performing first doping type ion implantation to form a source region of the first doping type and the first doping type layer;
and removing the patterned mask layer.
6. The method as claimed in any one of claims 1-5, further comprising a step of forming a metal interconnect structure after the steps of forming the well region of the second doping type and the source region of the first doping type in the cell region and forming the electrostatic protection structure.
7. The method of any of claims 1-5, wherein the first doping type is N-type and the second doping type is P-type.
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