CN104425344A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN104425344A CN104425344A CN201310382881.3A CN201310382881A CN104425344A CN 104425344 A CN104425344 A CN 104425344A CN 201310382881 A CN201310382881 A CN 201310382881A CN 104425344 A CN104425344 A CN 104425344A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000002955 isolation Methods 0.000 claims abstract description 174
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 239000000463 material Substances 0.000 claims description 41
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
- 230000015572 biosynthetic process Effects 0.000 claims description 24
- 238000005468 ion implantation Methods 0.000 claims description 18
- 238000009792 diffusion process Methods 0.000 claims description 17
- -1 SiCN Inorganic materials 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 14
- 229910052719 titanium Inorganic materials 0.000 claims description 12
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 238000000926 separation method Methods 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 9
- 150000002500 ions Chemical class 0.000 description 15
- 229910010271 silicon carbide Inorganic materials 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000005669 field effect Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910001439 antimony ion Inorganic materials 0.000 description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 description 3
- 229910001449 indium ion Inorganic materials 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 229910004541 SiN Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000002146 bilateral effect Effects 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
Abstract
Provided is a semiconductor structure and a forming method thereof. The semiconductor structure comprises a P-type substrate which is provided with an N-type burying isolation region, a P-type epitaxial layer on the P-type substrate, an LDMOS transistor in the first region of the P-type epitaxial layer, a dielectric layer covering the surface of the P-type epitaxial layer and the LDMOS transistor; an annular conductive plug in the dielectric layer and the second region of the P-type epitaxial layer, an isolation layer on the surface of the side wall of the annular conductive plug, and a first plug and a second plug in the dielectric layer of the first region of the P-type epitaxial layer. The P-type epitaxial layer comprises the first region and a second region. The first region is on the N-type burying isolation region. The second region surrounds the first region. The bottom of the annular conductive plug contacts the N-type burying isolation region. The first plug contacts with a gate structure. The second plug contacts with a source region or a drain region. The semiconductor structure has good isolation effect, and dimensions of the device are relatively small.
Description
Technical field
The present invention relates to field of semiconductor fabrication, particularly a kind of semiconductor structure and forming method thereof.
Background technology
Power field effect pipe mainly comprises vertical bilateral diffusion field-effect pipe VDMOS(VerticalDouble-Diffused MOSFET) and horizontal dual pervasion field effect pipe LDMOS(LateralDouble-Diffused MOSFET) two types.Wherein, compared to vertical bilateral diffusion field-effect pipe VDMOS, horizontal dual pervasion field effect pipe LDMOS has plurality of advantages, such as, the latter has better thermal stability and frequency stability, higher gain and durability, lower feedback capacity and thermal resistance, and constant input impedance and simpler biasing circuit.
In prior art, a kind of N-type LDMOS transistor structure of routine as shown in Figure 1, comprising: Semiconductor substrate (not shown), is arranged in the P trap 100 of Semiconductor substrate; Be positioned at the N-type drift region 101 of P trap 100; Be arranged in the fleet plough groove isolation structure 104 of N-type drift region 101, described fleet plough groove isolation structure 104 for increasing the path of ldmos transistor conducting, to increase the puncture voltage of ldmos transistor; Be positioned at the grid 105 in Semiconductor substrate, described grid is across described P trap and N-type drift region 101, and part is positioned on fleet plough groove isolation structure 104; Be positioned at the source region 102 of the P trap of grid 105 side, and be positioned at the drain region 103 of N-type drift region of opposite side of grid 105, the doping type in source region 102 and drain region 103 is N-type.
But the isolation performance of existing ldmos transistor and other devices is poor and isolation performance between ldmos transistor and Semiconductor substrate is also poor.
Summary of the invention
The problem that the present invention solves improves the isolation performance of ldmos transistor and substrate and other devices.
For solving the problem, the invention provides a kind of formation method of semiconductor structure, comprising: P type substrate is provided, in described P type substrate, being formed with N-type buried isolation regions; Described P type substrate is formed P type epitaxial loayer, and described P type epitaxial loayer comprises first area and second area, and first area is positioned at above N-type buried isolation regions, and second area is around described first area; Form ldmos transistor in the first area of described P type epitaxial loayer, described ldmos transistor comprises: the N-type drift region being positioned at the first area of P type epitaxial loayer; Be arranged in the first fleet plough groove isolation structure of N-type drift region; Be positioned at the grid structure on the first area of P type epitaxial loayer, grid structure covers P type epitaxial loayer, the first fleet plough groove isolation structure, N-type drift region between P type epitaxial loayer and the first fleet plough groove isolation structure; Be positioned at the source region of the P type epitaxial loayer of the side of grid structure; Be positioned at the drain region of the N-type drift region of the opposite side of grid structure; Form the dielectric layer covering described P type epi-layer surface and ldmos transistor, the surface of dielectric layer is higher than the grid structure top surface of ldmos transistor; Dielectric layer on the second area of etching P type epitaxial loayer and the second area of P type epitaxial loayer, form ring-shaped groove, ring-shaped groove is around the first area of P type epitaxial loayer, and described ring-shaped groove bottom-exposed goes out surface, N-type buried isolation regions; Separator is formed in the both sides sidewall surfaces of described ring-shaped groove; Dielectric layer on the first area of etching P type epitaxial loayer, forms the first through hole exposing grid structure top surface in the dielectric layer and exposes second through hole on source region or surface, drain region; In described ring-shaped groove, fill full metal, form ring shaped conductive connector, the bottom of ring shaped conductive connector contacts with N-type buried isolation regions, fills full metal, form the first connector and the second connector in the first through hole and the second through hole.
Optionally, described separation layer thickness is 500 ~ 3000 dusts.
Optionally, the material of described separator is SiO
2, one or more in SiN, SiON, SiCN, SiC.
Optionally, the material of described metal is one or more in W, Al, Cu, Ti, Ag, Au, Pt, Ni.
Optionally, fill full metal in the first through hole, the second through hole and ring-shaped groove before, in the sidewall of described first through hole and the second through hole and ring-shaped groove, insulation surface forms diffusion impervious layer.
Optionally, the material of described diffusion impervious layer is one or more in Ti, Ta, TiN, TaN.
Optionally, the degree of depth of described ring-shaped groove is 3 ~ 6 microns, and the width of ring-shaped groove is 0.6 ~ 1.2 micron.
Optionally, described ring-shaped groove part is arranged in N-type buried isolation regions.
Optionally, the degree of depth being arranged in the part ring-shaped groove of N-type buried isolation regions is 0.5 ~ 1 micron.
Optionally, the formation process of described N-type buried isolation regions is ion implantation, and in N-type buried isolation regions, the concentration of N-type impurity ion is 1E18atom/cm
3~ 2E21atom/cm
3.
Optionally, the second area of described P type epitaxial loayer is also formed with the second fleet plough groove isolation structure, and described ring-shaped groove runs through the second fleet plough groove isolation structure.。
Present invention also offers a kind of semiconductor structure, comprising: P type substrate, there is in described P type substrate N-type buried isolation regions; Be positioned at the P type epitaxial loayer in P type substrate, described P type epitaxial loayer comprises first area and second area, and first area is positioned at above N-type buried isolation regions, and second area is around described first area; Be arranged in the ldmos transistor of the first area of P type epitaxial loayer, described ldmos transistor comprises: the N-type drift region being positioned at the first area of P type epitaxial loayer; Be arranged in the first fleet plough groove isolation structure of N-type drift region; Be positioned at the grid structure on the first area of P type epitaxial loayer, grid structure covers P type epitaxial loayer, the first fleet plough groove isolation structure, N-type drift region between P type epitaxial loayer and the first fleet plough groove isolation structure; Be positioned at the source region of the P type epitaxial loayer of the side of grid structure; Be positioned at the drain region of the N-type drift region of the opposite side of grid structure; Cover the dielectric layer of described P type epi-layer surface and ldmos transistor, the surface of dielectric layer is higher than the grid structure top surface of ldmos transistor; Be arranged in the ring shaped conductive connector of the second area of dielectric layer on the second area of P type epitaxial loayer and P type epitaxial loayer, the bottom of ring shaped conductive connector contacts with N-type buried isolation regions; Be positioned at the separator on ring shaped conductive plug sidewall surface; Be arranged in the first connector and second connector of the dielectric layer on the first area of P type epitaxial loayer, the first connector contacts with grid structure, and the second connector contacts with source region or drain region.
Optionally, described separation layer thickness is 500 ~ 3000 dusts, and the material of described separator is SiO
2, one or more in SiN, SiON, SiCN, SiC.
Optionally, the material of described ring shaped conductive connector, the first connector and the second connector is metal, and described metal is one or more in W, Al, Cu, Ti, Ag, Au, Pt, Ni.
Optionally, described first connector and also there is diffusion impervious layer between the second connector and dielectric layer and between ring shaped conductive connector and separator.
Optionally, the material of described diffusion impervious layer is one or more in Ti, Ta, TiN, TaN.
Optionally, described ring shaped conductive plug section is arranged in N-type buried isolation regions.
Optionally, the degree of depth being arranged in the part ring shaped conductive connector of N-type buried isolation regions is 0.5 ~ 1 micron
Optionally, in N-type buried isolation regions, the concentration of N-type impurity ion is 1E18atom/cm
3~ 1E22atom/cm
3.
Optionally, the second area of described P type epitaxial loayer also has the second fleet plough groove isolation structure, and described ring shaped conductive connector runs through described second fleet plough groove isolation structure.
Compared with prior art, technical scheme of the present invention has the following advantages:
Semiconductor structure of the present invention, there is separator and ring shaped conductive connector, the isolation structure that N-type buried isolation regions is formed, separator realizes the lateral isolation of the semiconductor device outside the ldmos transistor that formed in first area and first area, ring shaped conductive connector contacts with N-type buried isolation regions, positive voltage is applied to N-type buried isolation regions by ring shaped conductive connector, make the PN junction between N-type buried isolation regions and P type substrate reverse-biased, realize the longitudinal direction isolation between ldmos transistor and P type substrate, isolation effect is improve by lateral isolation and longitudinal isolation, and the material of ring shaped conductive connector is metal, its resistance is very little, the efficiency that ring shaped conductive connector absorbs charge carrier improves, effectively prevent crosstalk noise, lateral isolation adopts separator isolation in addition, isolate compared to existing PN junction, it is very little that separator isolates the volume occupied, improve the integrated level of device.
Further, described separation layer thickness is 500 ~ 3000 dusts, and the material of described separator is SiO
2, one or more in SiN, SiON, SiCN, SiC, to make described separator at the small volume occupied simultaneously, better at ldmos transistor work isolation effect under high voltages.
The formation method of semiconductor structure of the present invention, ring shaped conductive plug material is metal, and the making of ring shaped conductive connector can be mutually compatible with the connector manufacture craft of back segment, save processing step, and manufacture craft is simple.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of prior art ldmos transistor;
Fig. 2 ~ Fig. 8 is the cross-sectional view of the forming process of embodiment of the present invention semiconductor structure.
Embodiment
Ldmos transistor is power device, therefore high voltage can be applied during ldmos transistor work, therefore in order to ensure the normal work of other low-voltage devices that Semiconductor substrate is formed, usually need ldmos transistor to isolate with other devices in Semiconductor substrate.Please refer to Fig. 1, existing isolation method normally forms N-type shading ring 106 in P trap 100, N-type shading ring 106 is formed by ion implantation, N-type shading ring 106 applies positive voltage, make to occur between N-type shading ring 106 and P trap 100 reverse-biased, thus the device of ldmos transistor and surrounding is separated, big current horizontal proliferation the having an impact to peripheral devices produced under preventing high voltage.
In order to ensure the isolation effect of N-type shading ring 106, N-type shading ring 106 needs the darker degree of depth and higher doping content, but above-mentioned N-type shading ring 106 is formed by ion implantation, when the degree of depth of N-type shading ring 106 is darker, the method of ion implantation is difficult to ensure concentration higher in darker N-type shading ring 106, this just needs the transverse width increasing N-type shading ring 106 to keep its isolation, the volume that like this N-type shading ring 106 can be made to occupy increases, and is unfavorable for the raising of device integration.
In addition, N-type shading ring 106 is obvious to the isolation effect of transverse direction, but it is very limited to the effect of the isolation of longitudinal direction.
For this reason, the invention provides a kind of semiconductor structure and forming method thereof, the isolation structure that this semiconductor structure adopts ring shaped conductive connector and separator, N-type buried isolation regions to form, realize the lateral isolation of other devices on ldmos transistor and substrate and longitudinally isolate, isolation effect is good, and the volume adopting the lateral isolation mode of ring shaped conductive connector and separator to occupy is smaller.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.When describing the embodiment of the present invention in detail, for ease of illustrating, schematic diagram can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, and it should not limit the scope of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Fig. 2 ~ Fig. 8 is the cross-sectional view of the forming process of embodiment of the present invention semiconductor structure.
First, please refer to Fig. 2, P type substrate 200 is provided, in described P type substrate 200, be formed with N-type buried isolation regions 203; Described P type substrate 200 is formed P type epitaxial loayer 201, and described P type epitaxial loayer 201 comprises first area 21 and second area 22, and first area 21 is positioned at above N-type buried isolation regions 203, and second area 22 is around described first area 21.
The material of described P type substrate 200 is silicon (Si), germanium (Ge) or SiGe (GeSi), carborundum (SiC) or other semi-conducting material, and in the present embodiment, the material of described N-type substrate 201 is silicon.
Doped with the foreign ion of P type in P type substrate 200, described p type impurity ion is one or more in boron ion, gallium ion, indium ion.
N-type buried isolation regions 203 is formed in described P type substrate 200, described N-type buried isolation regions 203 isolates for the longitudinal direction between the ldmos transistor of follow-up formation and P type substrate 200, during ldmos transistor work, when N-type buried isolation regions 203 applies positive voltage, between N-type buried isolation regions 203 and P type substrate 200 substrate, PN junction is reverse-biased, realizes the isolation between N-type buried isolation regions 203 and P type substrate.
Described N-type buried isolation regions 203 is by carrying out N-type ion implantation to P type substrate 200, and described N-type ion is one or more in phosphonium ion, arsenic ion, antimony ion.In N-type buried isolation regions, the concentration of N-type impurity ion is larger, make to be easy to PN junction between N-type buried isolation regions 203 and P type substrate 200 reverse-biased, and junction depth time reverse-biased is comparatively large, and to improve longitudinal isolation performance, the N-type ion concentration in described N-type buried isolation regions 203 is 1E18atom/cm
3~ 2E21atom/cm
3, such as: 1E19atom/cm
3, 2E19atom/cm
3, 1E20atom/cm
3, 9E20atom/cm
3deng.
Described P type substrate 200 is formed with P type epitaxial loayer 201, P type epitaxial loayer 201 comprises first area 21 and second area 22, second area 22 is around described first area 21, namely first area 21 is positioned at centre, second area 22 is positioned at edge, described first area 21 is positioned at directly over N-type mask separator 203, the area of first area 21 is less than or is slightly less than the area of N-type mask separator 203, follow-up formation ldmos transistor in the first area 21 of P type epitaxial loayer 201, the follow-up isolation structure (separator and ring shaped conductive connector) forming annular in second area 22.
Described P type epitaxial loayer 201 is formed by epitaxy technique, and the in-situ doped p type impurity ion when extension forms P type epitaxial loayer, described p type impurity ion is one or more in boron ion, gallium ion, indium ion.
The material of P type epitaxial loayer 201 is identical with the material of P type substrate or not identical, and in the present embodiment, the material of described P type epitaxial loayer 201 is silicon.
Then, please refer to Fig. 3, in the first area 21 of described P type epitaxial loayer 201, form ldmos transistor, described ldmos transistor comprises: the N-type drift region 209 being positioned at the first area 21 of P type epitaxial loayer 201; Be arranged in the first fleet plough groove isolation structure 206 of N-type drift region 209; Be positioned at the grid structure 212 on the first area 21 of P type epitaxial loayer 201, grid structure 212 covers P type epitaxial loayer 201, first fleet plough groove isolation structure 206, N-type drift region 209 between P type epitaxial loayer 201 and the first fleet plough groove isolation structure 206; Be positioned at the source region 213 of the P type epitaxial loayer 201 of the side of grid structure 212; Be positioned at the drain region 214 of the N-type drift region 209 of the opposite side of grid structure 212.
The detailed process that described ldmos transistor is formed is: first in described P type epitaxial loayer 201 first area 21, form the first fleet plough groove isolation structure 206; Then the first N-type ion implantation is carried out to described Semiconductor substrate, form N-type drift region 209, the foreign ion that described N-type drift region 209 surrounds described first fleet plough groove isolation structure 206, first N-type ion implantation is one or more in phosphonium ion, arsenic ion, antimony ion; Then on the first area 21 of P type epitaxial loayer 201, grid structure 212 is formed, grid structure 212 covers P type epitaxial loayer 201, first fleet plough groove isolation structure 206, N-type drift region 209 between P type epitaxial loayer 201 and the first fleet plough groove isolation structure 206, and described grid structure 212 comprises gate dielectric layer 211, be positioned at gate electrode 210 on gate dielectric layer 211 and be positioned at the side wall of gate dielectric layer 211 and gate electrode 210 sidewall; Carry out the second N-type ion implantation, source region 216 in the P type epitaxial loayer 201 of the side of grid structure 212 and side wall, the foreign ion of drain region 214, the second N-type ion implantation in the N-type drift region 209 of the opposite side of grid structure 212 and side wall is one or more in phosphonium ion, arsenic ion, antimony ion; After carrying out N shape ion implantation and P type ion implantation, also need to anneal, to activate Doped ions, the time of described annealing is 20 ~ 30 seconds, and the temperature of annealing is greater than 1000 degrees Celsius.
The material of described gate dielectric layer 211 is silica, and the material of gate electrode 210 is polysilicon.The material of described gate dielectric layer 211 also can be high-k dielectric material, and the material of corresponding described gate electrode 210 is metal.
Described side wall can be the stacked structure of single or multiple lift.
Described first fleet plough groove isolation structure 206 as a part for ldmos transistor, for increasing the path of source and drain circuit produced between source region 213 and drain region 214.Described grid structure 212 can cover the part or all of surface of the first fleet plough groove isolation structure 206, and in the present embodiment, described grid structure 212 covers the surface of at least half of described first fleet plough groove isolation structure 206.
P type isolated area 217 is also formed between described N-type drift region 209 and N shape buried isolation regions 203, described P type separator is used for the electric isolation between N-type drift region 209 and N shape buried isolation regions 203, P type isolated area 217, before or after formation N-type drift region 209, is formed by dark doped p-type ion implantation.
P type tagma 216 is also formed in the P type epitaxial loayer of described grid structure 212 side, source region 213 is positioned at P type tagma 216, described P type tagma 216 for regulating the threshold voltage of ldmos transistor, and can reduce parasitic triode effect, improves the source and drain puncture voltage of ldmos transistor.Described P type tagma 216, after formation grid structure, is formed by P type ion implantation.
The second fleet plough groove isolation structure 204 is formed in described P type epitaxial loayer 201 second area 22, second fleet plough groove isolation structure 204 is around the first area 22 of described P type epitaxial loayer 201, the ring shaped conductive connector of follow-up formation runs through the electric isolation performance that the second fleet plough groove isolation structure 204, second fleet plough groove isolation structure 204 improves the doped region in ring shaped conductive connector and P type epitaxial loayer.Described second fleet plough groove isolation structure 204 can be formed with the same step of the first fleet plough groove isolation structure 206.
The 3rd fleet plough groove isolation structure 207 is also formed in described P type epitaxial loayer 201 first area 21,3rd fleet plough groove isolation structure 207 around described ldmos transistor, the body doping ring 208 that described 3rd fleet plough groove isolation structure 207 is formed for first area 21 and the isolation between the source region 213 of ldmos transistor and drain region 214.Described body doping ring 208 is around described ldmos transistor (or the 3rd fleet plough groove isolation structure 207), described body doping ring 208 is for connecting earth terminal or negative voltage, prevent the generation of latch-up, and the current potential of the channel region bottom grid structure 212 is regulated.In body doping ring 208, the type of foreign ion of doping is P type, and body doping ring 208 is formed by P type ion implantation, and the foreign ion of P type ion implantation is one or more in boron ion, gallium ion or indium ion.Described 3rd fleet plough groove isolation structure 207 can be formed with the same step of the first fleet plough groove isolation structure 206.
P type shading ring 215 is also formed in described P type epitaxial loayer 201 second area 22, P type shading ring 215 is around described second fleet plough groove isolation structure 204, described P type shading ring 215 ground connection, for the electric isolation of the semiconductor device in other regions in the ldmos transistor in the first area 21 of P type epitaxial loayer 201 and P type epitaxial loayer 201.Described P type shading ring 215, body doping ring 208 and P type tagma 216 can be formed by the P type ion implantation technology of same step.It should be noted that, described P type shading ring 215, body doping ring 208 and P type tagma 216 also can be formed by the P type ion implantation technology of different step.
The 4th fleet plough groove isolation structure 205 is also formed in described P type epitaxial loayer 201 second area 22, described 4th fleet plough groove isolation structure 205 around described P type shading ring the 215, four fleet plough groove isolation structure 205 for the isolation of P type shading ring 215 between other active areas of P type epitaxial loayer 201 second area 22.Described 4th fleet plough groove isolation structure 205 can be formed with the same step of the first fleet plough groove isolation structure 206.
The material of described first fleet plough groove isolation structure 206, second fleet plough groove isolation structure 204, the 3rd fleet plough groove isolation structure 207 or the 4th fleet plough groove isolation structure 205 is SiO
2, SiN, SiON, SiCN or SiC.In the present embodiment, the material of described first fleet plough groove isolation structure 206, second fleet plough groove isolation structure 204, the 3rd fleet plough groove isolation structure 207 or the 4th fleet plough groove isolation structure 205 is SiO
2.
With reference to figure 4, form the dielectric layer 218 covering described P type epitaxial loayer 201 surface and ldmos transistor, the surface of dielectric layer 218 is higher than grid structure 210 top surface of ldmos transistor.
The material of described dielectric layer 218 is SiO
2, SiN, SiON, SiCN, SiC or low-K dielectric constant material etc.Dielectric layer 218 can be formed by chemical vapor deposition method.
Described dielectric layer 218 can be single or multiple lift stacked structure.
With reference to figure 5, dielectric layer 218 on the second area 22 of etching P type epitaxial loayer 201 and the second area 22 of P type epitaxial loayer 201, form ring-shaped groove 219, ring-shaped groove 219 is around the first area 21 of P type epitaxial loayer 301, and described ring-shaped groove 219 bottom-exposed goes out surface, N-type buried isolation regions 203.
Needed to form mask layer (not shown) on described dielectric layer 218 before the described dielectric layer 218 of etching, described mask layer has and exposes the opening on dielectric layer 218 surface, and width and the position of the width of described opening and position and ring-shaped groove are corresponding.
Described ring-shaped groove 219 is formed by two step etching technics, comprise the first plasma etching industrial and the second plasma etching industrial, first the first plasma etch process etch media layer 218 and the second fleet plough groove isolation structure 204 is adopted, form the first sub-trenches, first plasma etch process adopts gas to be fluoro-gas, such as CF
4or C
3f
8deng; Then, along the first sub-trenches, adopt the first plasma etch process etching P type epitaxial loayer 201, the second sub-trenches is formed in P type epitaxial loayer 201, first sub-trenches and the second sub-trenches looping groove 219, first plasma etch process adopts gas to be chloride or bromine-containing gas, such as Cl
2or HBr etc.
In other embodiments of the invention, a step etching technics also can be adopted to form described ring-shaped groove.
Ring-shaped groove 219 is formed in the second area 22 of described P type epitaxial loayer 201, ring-shaped groove 219 is around the first area 21 of P type epitaxial loayer 201, and described ring-shaped groove 219 bottom-exposed goes out surface, N-type buried isolation regions 203, follow-uply on the sidewall of ring-shaped groove 219 be formed with separator, the follow-up filling metal of ring-shaped groove 219 forms ring shaped conductive connector, the bottom of ring shaped conductive connector is connected with N-type buried isolation regions 203, positive voltage is applied to N-type buried isolation regions 203 by ring shaped conductive connector, make the PN junction between N-type buried isolation regions 203 and P type substrate 200 reverse-biased, the longitudinal direction realized between ldmos transistor and P type substrate 200 is isolated.
In other embodiments of the invention, described ring-shaped groove part is arranged in N-type buried isolation regions, namely when etching P type epitaxial loayer, N-type buried isolation regions described in over etching, the degree of depth of the ring-shaped groove formed is increased, therefore follow-up when forming ring shaped conductive connector in ring-shaped groove, ring shaped conductive connector fully can be contacted with N-type buried isolation regions, prevent from producing the phenomenons such as loose contact on both contact-making surfaces.
The degree of depth that described ring-shaped groove is arranged in the part of N-type buried isolation regions is 0.5 ~ 1 micron, makes the ring shaped conductive connector formed in formation ring-shaped groove can contact best results with N-type buried isolation regions.
The degree of depth of described ring-shaped groove 219 is 3 ~ 6 microns, the width of ring-shaped groove 219 is 0.6 ~ 1.2 micron, compared to existing PN junction as lateral isolation, the follow-up lateral isolation structure forming separator and ring shaped conductive connector formation in ring-shaped groove 219, it has less device size, is conducive to the integrated level improving device.
Then, please refer to Fig. 6, form separator 220 in the both sides sidewall surfaces of described ring-shaped groove 219.
Separator 220 is formed at both sides, ring-shaped groove 219 side sidewall, make separator 220 also around the first area 21 of P type epitaxial loayer 201, the conductive plunger of described separator 220 for follow-up formation and the electric isolation of P type epitaxial loayer 201, described separator 220 is also for the lateral isolation of semiconductor device outside the ldmos transistor that formed in first area 21 and first area 21.
Described separator 220 thickness is 500 ~ 3000 dusts, and the material of described separator 220 is insulating material, and the material of concrete described separator 220 is SiO
2, one or more in SiN, SiON, SiCN, SiC, to make described separator at the small volume occupied simultaneously, better at ldmos transistor work isolation effect under high voltages.
Described separator 220 can be single or multiple lift stacked structure.
The forming process of described separator 220 is: adopt depositing operation to form spacer material layer at the sidewall of described ring-shaped groove 219 and the surface of lower surface and P type epitaxial loayer 201; Adopt and etch described spacer material layer without mask etching technique, remove the surface of P type epitaxial loayer 201 and the spacer material layer of ring-shaped groove 219 lower surface, form separator 220 at the both sides sidewall of described ring-shaped groove 219.
Then, please refer to Fig. 7, dielectric layer 218 on the first area 21 of etching P type epitaxial loayer 201, forms the first through hole 221 exposing grid structure (gate electrode 210) top surface and exposes second through hole 222 on source region 213 or surface, drain region 214 in dielectric layer 218.
Before the described dielectric layer 218 of etching, form mask layer on described dielectric layer 218 surface, mask material fills ring-shaped groove 219, and described mask layer has the some openings exposing dielectric layer 218 surface.Described mask material can be photoresist.
Etch described dielectric layer 218 and adopt fluorine-containing plasma etching.
In the present embodiment, during etch media layer 218, can also form third through-hole 223 and fourth hole 224 in dielectric layer 218, described third through-hole 223 exposes the surface of body doping ring 208, and described fourth hole 224 exposes the surface of P type shading ring 215.
Finally, please refer to Fig. 8, at described ring-shaped groove 219(with reference to figure 7) the full metal of middle filling, form ring shaped conductive connector 225, the bottom of ring shaped conductive connector 225 contacts with N-type buried isolation regions 203, at the first through hole 221 and the second through hole 222(with reference to figure 7) in fill full metal, form the first connector 226 and the second connector 227, first connector 226 contacts with grid structure (gate electrode 210), and the second connector 227 contacts with source region 213 or drain region 214.
The forming process of described ring shaped conductive connector 225, first connector 226 and the second connector 227 is: on described dielectric layer 218, form metal level (not shown), and described layer fills full ring-shaped groove 219, first through hole 221 and the second through hole 222; Metal level described in planarization, until expose the surface of dielectric layer 218, forms ring shaped conductive connector 204 in ring-shaped groove 219, forms the first connector 226 and the second connector 227 in the first through hole 221 and the second through hole 222.
Formation ring shaped conductive connector 225, first connector 226 and the second connector 227 while, at third through-hole 223 and fourth hole 224(with reference to figure 7) in form the 3rd connector 228 and the 4th connector 229, described 3rd connector 228 and the body ring 208 that adulterates contacts, and described 4th connector 229 contacts with P type shading ring 215.
The material of described metal is one or more in W, Al, Cu, Ti, Ag, Au, Pt, Ni.The metal adopted in the present embodiment is W.
Also comprise: before filling full metal in ring-shaped groove 219, first through hole 221 and the second through hole 222, in the sidewall of described first through hole 221 and the second through hole 222 and ring-shaped groove 219, insulation surface forms diffusion impervious layer (not shown), and described diffusion impervious layer is for preventing the metallic atom diffusion in dielectric layer 218 and in separator 220 in connector.
The material of described diffusion impervious layer is one or more in Ti, Ta, TiN, TaN.Described diffusion impervious layer can be the double-decker of Ti and TiN double-decker or Ta and TaN.
Described ring shaped conductive connector 204 is electrically connected with N-type buried isolation regions 203, positive voltage can be applied to N-type buried isolation regions 203 by ring shaped conductive connector 204, make the PN junction that forms between N-type buried isolation regions 203 and P type substrate 200 reverse-biased, thus realize the longitudinal direction formed between ldmos transistor and P type substrate 200 in follow-up first area 21 to isolate, high voltage when preventing ldmos transistor from working and big current are had an impact by the semiconductor device outside P type substrate 200 pairs of first areas 21.
Ring shaped conductive connector 204 material is metal, the making of ring shaped conductive connector 204 can be mutually compatible with the connector manufacture craft of back segment, save processing step, and manufacture craft is simple, and, because the resistance of metal material is very low, the efficiency that ring shaped conductive connector 204 absorbs charge carrier improves, effectively prevent crosstalk noise, in addition, forming isolation structure by ring shaped conductive connector 204 and separator 220 makes existing lateral isolation become insulating material isolation from PN junction isolation, and the size of device reduces, and improves integrated level.
Above-mentioned ldmos transistor operationally, gate electrode 210 applies operating voltage, and source region 213 and body doping ring 208 ground connection or negative voltage, drain region 214 and ring shaped conductive connector 204 apply positive voltage.
The semiconductor structure that above-mentioned direction is formed, please refer to Fig. 8, comprising:
P type substrate 200, has N-type buried isolation regions 203 in described P type substrate 200;
Be positioned at the P type epitaxial loayer 201 in P type substrate 200, described P type epitaxial loayer 201 comprises first area 21 and second area 22, and first area 21 is positioned at above N-type buried isolation regions 203, and second area 22 is around described first area 21;
Be arranged in the ldmos transistor of the first area 21 of P type epitaxial loayer 201, described ldmos transistor comprises: the N-type drift region 209 being positioned at the first area 21 of P type epitaxial loayer 201; Be arranged in the first fleet plough groove isolation structure 206 of N-type drift region 209; Be positioned at the grid structure on the first area 21 of P type epitaxial loayer 201, grid structure covers P type epitaxial loayer 201, first fleet plough groove isolation structure 206, N-type drift region 209 between P type epitaxial loayer 201 and the first fleet plough groove isolation structure 203; Be positioned at the source region 213 of the P type epitaxial loayer 201 of the side of grid structure; Be positioned at the drain region 214 of the N-type drift region 209 of the opposite side of grid structure;
Cover described P type epitaxial loayer 301 surface and the dielectric layer 218 of ldmos transistor, the surface of dielectric layer 218 is higher than the grid structure top surface of ldmos transistor;
Be arranged in the ring shaped conductive connector 225 of the second area 22 of dielectric layer 218 on the second area 22 of P type epitaxial loayer 201 and P type epitaxial loayer 201, the bottom of ring shaped conductive connector 225 contacts with N-type buried isolation regions 203;
Be positioned at the separator 220 of ring shaped conductive connector 225 sidewall surfaces;
The first connector 226 and the second connector 227, first connector 226 that are arranged in the dielectric layer 218 on the first area 21 of P type epitaxial loayer 201 contact with grid structure, and the second connector 227 contacts with source region 213 or drain region 215.
Concrete, described separator 220 thickness is 500 ~ 3000 dusts, and the material of described separator is SiO
2, one or more in SiN, SiON, SiCN, SiC.
The material of described ring shaped conductive connector 225, first connector 226 and the second connector 227 is metal, and described metal is one or more in W, Al, Cu, Ti, Ag, Au, Pt, Ni.
Described first connector 226 and also there is diffusion impervious layer between the second connector 227 and dielectric layer 218 and between ring shaped conductive connector 225 and separator 220.
The material of described diffusion impervious layer is one or more in Ti, Ta, TiN, TaN.
In other embodiments of the invention, described ring shaped conductive plug section is arranged in N-type buried isolation regions, and the degree of depth being arranged in the part ring shaped conductive connector of N-type buried isolation regions is 0.5 ~ 1 micron.
In N-type buried isolation regions 203, the concentration of N-type impurity ion is 1E18atom/cm
3~ 1E22atom/cm
3.
The second area 22 of described P type epitaxial loayer 20 also has the second fleet plough groove isolation structure 204, and described ring shaped conductive is inserted 225 plugs and run through described second fleet plough groove isolation structure 204.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a formation method for semiconductor structure, is characterized in that, comprising:
P type substrate is provided, in described P type substrate, is formed with N-type buried isolation regions;
Described P type substrate is formed P type epitaxial loayer, and described P type epitaxial loayer comprises first area and second area, and first area is positioned at above N-type buried isolation regions, and second area is around described first area;
Form ldmos transistor in the first area of described P type epitaxial loayer, described ldmos transistor comprises: the N-type drift region being positioned at the first area of P type epitaxial loayer; Be arranged in the first fleet plough groove isolation structure of N-type drift region; Be positioned at the grid structure on the first area of P type epitaxial loayer, grid structure covers P type epitaxial loayer, the first fleet plough groove isolation structure, N-type drift region between P type epitaxial loayer and the first fleet plough groove isolation structure; Be positioned at the source region of the P type epitaxial loayer of the side of grid structure; Be positioned at the drain region of the N-type drift region of the opposite side of grid structure;
Form the dielectric layer covering described P type epi-layer surface and ldmos transistor, the surface of dielectric layer is higher than the grid structure top surface of ldmos transistor;
Dielectric layer on the second area of etching P type epitaxial loayer and the second area of P type epitaxial loayer, form ring-shaped groove, ring-shaped groove is around the first area of P type epitaxial loayer, and described ring-shaped groove bottom-exposed goes out surface, N-type buried isolation regions;
Separator is formed in the both sides sidewall surfaces of described ring-shaped groove;
Dielectric layer on the first area of etching P type epitaxial loayer, forms the first through hole exposing grid structure top surface in the dielectric layer and exposes second through hole on source region or surface, drain region;
In described ring-shaped groove, fill full metal, form ring shaped conductive connector, the bottom of ring shaped conductive connector contacts with N-type buried isolation regions, fills full metal, form the first connector and the second connector in the first through hole and the second through hole.
2. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, described separation layer thickness is 500 ~ 3000 dusts.
3. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, the material of described separator is SiO
2, one or more in SiN, SiON, SiCN, SiC.
4. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, the material of described metal is one or more in W, Al, Cu, Ti, Ag, Au, Pt, Ni.
5. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, fill full metal in the first through hole, the second through hole and ring-shaped groove before, in the sidewall and ring-shaped groove of described first through hole and the second through hole, insulation surface forms diffusion impervious layer.
6. the formation method of semiconductor structure as claimed in claim 5, is characterized in that, the material of described diffusion impervious layer is one or more in Ti, Ta, TiN, TaN.
7. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, the degree of depth of described ring-shaped groove is 3 ~ 6 microns, and the width of ring-shaped groove is 0.6 ~ 1.2 micron.
8. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, described ring-shaped groove part is arranged in N-type buried isolation regions.
9. the formation method of semiconductor structure as claimed in claim 8, it is characterized in that, the degree of depth being arranged in the part ring-shaped groove of N-type buried isolation regions is 0.5 ~ 1 micron.
10. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, the formation process of described N-type buried isolation regions is ion implantation, and in N-type buried isolation regions, the concentration of N-type impurity ion is 1E18atom/cm
3~ 2E21atom/cm
3.
The formation method of 11. semiconductor structures as claimed in claim 1, is characterized in that, the second area of described P type epitaxial loayer is also formed with the second fleet plough groove isolation structure, and described ring-shaped groove runs through the second fleet plough groove isolation structure.
12. 1 kinds of semiconductor structures, is characterized in that, comprising:
P type substrate, has N-type buried isolation regions in described P type substrate;
Be positioned at the P type epitaxial loayer in P type substrate, described P type epitaxial loayer comprises first area and second area, and first area is positioned at above N-type buried isolation regions, and second area is around described first area;
Be arranged in the ldmos transistor of the first area of P type epitaxial loayer, described ldmos transistor comprises: the N-type drift region being positioned at the first area of P type epitaxial loayer; Be arranged in the first fleet plough groove isolation structure of N-type drift region; Be positioned at the grid structure on the first area of P type epitaxial loayer, grid structure covers P type epitaxial loayer, the first fleet plough groove isolation structure, N-type drift region between P type epitaxial loayer and the first fleet plough groove isolation structure; Be positioned at the source region of the P type epitaxial loayer of the side of grid structure; Be positioned at the drain region of the N-type drift region of the opposite side of grid structure;
Cover the dielectric layer of described P type epi-layer surface and ldmos transistor, the surface of dielectric layer is higher than the grid structure top surface of ldmos transistor;
Be arranged in the ring shaped conductive connector of the second area of dielectric layer on the second area of P type epitaxial loayer and P type epitaxial loayer, the bottom of ring shaped conductive connector contacts with N-type buried isolation regions;
Be positioned at the separator on ring shaped conductive plug sidewall surface;
Be arranged in the first connector and second connector of the dielectric layer on the first area of P type epitaxial loayer, the first connector contacts with grid structure, and the second connector contacts with source region or drain region.
13. semiconductor structures as claimed in claim 12, it is characterized in that, described separation layer thickness is 500 ~ 3000 dusts, and the material of described separator is SiO
2, one or more in SiN, SiON, SiCN, SiC.
14. semiconductor structures as claimed in claim 12, is characterized in that, the material of described ring shaped conductive connector, the first connector and the second connector is metal, and described metal is one or more in W, Al, Cu, Ti, Ag, Au, Pt, Ni.
15. semiconductor structures as claimed in claim 12, is characterized in that, described first connector and also have diffusion impervious layer between the second connector and dielectric layer and between ring shaped conductive connector and separator.
16. semiconductor structures as claimed in claim 15, is characterized in that, the material of described diffusion impervious layer is one or more in Ti, Ta, TiN, TaN.
17. semiconductor structures as claimed in claim 12, it is characterized in that, described ring shaped conductive plug section is arranged in N-type buried isolation regions.
18. semiconductor structures as claimed in claim 17, is characterized in that, the degree of depth being arranged in the part ring shaped conductive connector of N-type buried isolation regions is 0.5 ~ 1 micron.
19. semiconductor structures as claimed in claim 12, it is characterized in that, in N-type buried isolation regions, the concentration of N-type impurity ion is 1E18atom/cm
3~ 1E22atom/cm
3.
20. semiconductor structures as claimed in claim 12, is characterized in that, the second area of described P type epitaxial loayer also has the second fleet plough groove isolation structure, and described ring shaped conductive connector runs through described second fleet plough groove isolation structure.
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| CN111613532A (en) * | 2019-02-25 | 2020-09-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of field effect transistor and field effect transistor |
| CN113990917A (en) * | 2020-07-27 | 2022-01-28 | 格芯(美国)集成电路科技有限公司 | Transistor with embedded isolation layer in bulk substrate |
| US12016177B2 (en) | 2020-08-19 | 2024-06-18 | Samsung Electronics Co., Ltd. | Semiconductor devices, nonvolatile memory devices including the same, electronic systems including the same, and methods for fabricating the same |
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| CN102037562A (en) * | 2008-02-27 | 2011-04-27 | 先进模拟科技公司 | Isolated transistors and diodes and isolation and termination structures for semiconductor die |
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| CN111613532B (en) * | 2019-02-25 | 2023-08-22 | 中芯国际集成电路制造(上海)有限公司 | Forming method of field effect transistor and field effect transistor |
| CN113990917A (en) * | 2020-07-27 | 2022-01-28 | 格芯(美国)集成电路科技有限公司 | Transistor with embedded isolation layer in bulk substrate |
| US12016177B2 (en) | 2020-08-19 | 2024-06-18 | Samsung Electronics Co., Ltd. | Semiconductor devices, nonvolatile memory devices including the same, electronic systems including the same, and methods for fabricating the same |
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