US20120199899A1 - Semiconductor device having field plate electrode and method for manufacturing the same - Google Patents
Semiconductor device having field plate electrode and method for manufacturing the same Download PDFInfo
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- US20120199899A1 US20120199899A1 US13/233,981 US201113233981A US2012199899A1 US 20120199899 A1 US20120199899 A1 US 20120199899A1 US 201113233981 A US201113233981 A US 201113233981A US 2012199899 A1 US2012199899 A1 US 2012199899A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Abstract
According to one embodiment, in a semiconductor device, a first semiconductor layer of a first conductivity type has a first impurity concentration. A second semiconductor layer of the first conductivity type is formed on the first semiconductor layer and has a second impurity concentration lower than the first impurity concentration. A field plate electrode is formed in a lower portion of a trench formed in the second semiconductor layer through a first insulating film so as to bury the lower portion of the trench. A second insulating film is formed in the upper portion of the trench so as to be in contact with the top surface of the field plate electrode. A gate electrode is formed in the upper portion of the trench through a gate insulating film so as to bury the upper portion of the trench to sandwich the second insulating film.
Description
- This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2011-025889, filed on Feb. 9, 2011, the entire contents of which are incorporated herein by reference.
- Embodiments described herein relate generally to a semiconductor device having a field plate electrode and a method for manufacturing the semiconductor device.
- A power semiconductor device requires a high withstand voltage and a high figure of merit (FOM: Figure Of Merit). The figure of merit is under the control of a conduction loss due to an on-resistance and a switching loss in a turn-on state, and is expressed by an inverse number of a product of an on-resistance Ron and an input capacitance Ciss (Source Short-circuit Input Capacitance). In general, the on-resistance Ron and the input capacitance Ciss are traded off.
- As a conventional power semiconductor device, an insulating gate field effect transistor of which the electric field concentration is moderated by a vertical field plate structure to achieve a high withstand voltage is known.
- In the semiconductor device, a trench is formed in an N-type semiconductor layer on a drain layer. A field plate electrode is buried into the trench through a thick field plate insulating film. The field plate electrode is electrically connected to a source layer.
- A gate electrode is buried into an upper portion of the trench through a gate insulating film to sandwich the field plate electrode through an insulating film. A P-type base layer is formed on an upper portion of an N-type semiconductor layer adjacent to the trench, and an N-type source layer is formed on the upper portion of the base layer.
- As a result, it is a problem in that an input capacitance Ciss increases due to an increase of an inter-electrode capacitance between the gate electrode and the field plate electrode increases. For this reason, it is a problem that it is impossible to obtain a high figure of merit due to an increase of a product of the on-resistance Ron and the input capacitance Ciss.
-
FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment; -
FIGS. 2A and 2B are cross-sectional images of scanning electron microscope showing the semiconductor device according to the embodiment; -
FIG. 3 is a view to explain an input capacitance of the semiconductor device according to the embodiment; -
FIG. 4 is a diagram showing a simulation result of the input capacitance of the semiconductor device according to the embodiment; -
FIGS. 5A to 10B are cross-sectional views sequentially showing the steps of manufacturing the semiconductor device according to the embodiment; -
FIG. 11 is a diagram showing a relation between a temperature and a relative enhanced oxidation rate; -
FIG. 12 is a cross-sectional view showing a semiconductor device of a comparative example according to the embodiment; -
FIGS. 13A and 13B are cross-sectional images of scanning electron microscope showing the semiconductor device of the comparative example according to the embodiment; - According to one embodiment, in a semiconductor device, a first semiconductor layer of a first conductivity type has a first impurity concentration. A second semiconductor layer of the first conductivity type is formed on the first semiconductor layer and has a second impurity concentration lower than the first impurity concentration. A field plate electrode is formed in a lower portion of a trench formed in the second semiconductor layer on a bottom surface side of the trench through a first insulating film so as to bury the lower portion of the trench. A second insulating film is formed in the upper portion of the trench so as to be in contact with the top surface of the field plate electrode. A gate electrode is formed in the upper portion of the trench on an opening side of the trench through a gate insulating film so as to bury the upper portion of the trench to sandwich the second insulating film. A base layer of a second conductivity type is formed in the upper portion of the second semiconductor layer and has a third impurity concentration. A source layer of the first conductivity type is formed in the upper portion of the base layer and has a fourth impurity concentration higher than the second impurity concentration.
- Hereinafter, embodiments will be described with reference to the drawings. In the drawings, same reference characters denote the same or similar portions.
- A semiconductor device of an embodiment will be described with reference to
FIGS. 1 to 2B .FIG. 1 is a cross-sectional view showing the semiconductor device, andFIGS. 2A and 2B are cross-sectional SEM (Scanning Electron Microscope) images showing the semiconductor device. The semiconductor device of the embodiment is a trench gate field effect transistor having a vertical field plate structure. - As shown in
FIGS. 1 to 2B , in asemiconductor device 10 of the embodiment, asecond semiconductor layer 12 of a first conductivity type (N−-type) having a second impurity concentration lower than a first impurity concentration is formed on afirst semiconductor layer 11 of a first conductivity type (N++-type) having the first impurity concentration. - The
first semiconductor layer 11 serves as a drain layer and is a silicon substrate, for example. The first impurity concentration and the thickness of thefirst semiconductor layer 11 are about 2E19 cm−3 and about 100 μm, for example, respectively. - The
second semiconductor layer 12 is a drift layer in which electrons run, and is a silicon layer formed by epitaxial growth on thefirst semiconductor layer 11, for example. The second impurity concentration and the thickness of thesecond semiconductor layer 12 depend on the withstand voltage of thesemiconductor device 10. When a withstand voltage of 100 V, for example, is obtained, the second impurity concentration and the thickness are about 2E16 cm−3 and about 7.5 μm, respectively. - In the
second semiconductor layer 12, a stripe shaped trench having a width of about 1.7 μm and a depth of about 5 μm, for example, is formed in a depth direction (vertical direction to the drawing). The multiple trenches are aligned in a lateral direction (X direction on the drawing) with a predetermined pitch of about 3 μm, for example. - In the trench, a field plate structure is formed in a lower portion of the trench on a bottom surface side of the trench. A trench gate structure is formed in an upper portion of the trench on an opening side of the trench.
- More specifically, a thick first insulating film (field plate insulating film) 13 is formed on an inner surface of the lower portion of the trench. A
field plate electrode 14 is formed to bury the lower portion of the trench through the first insulatingfilm 13. - The first insulating
film 13 is a silicon oxide film having a thickness of about 0.67 μm, for example. Thefield plate electrode 14 is a polysilicon film having a width W1 of about 0.42 μm for example and doped with a phosphorous (P), for example, serving as an impurity at about 1E18 cm−3. The first insulatingfilm 13 and thefield plate electrode 14 are formed from a bottom surface of the trench at a height of about 4.5 μm, for example. - In the field plate structure, a thick insulating film is formed in the trench to make it possible to keep an electric field in a breakdown state from a junction to the bottom of the trench to moderate the electric field acting on the junction.
- Furthermore, a
gate insulating film 15 is formed on a side surface of the upper portion of the trench. Agate electrode 17 is formed through thegate insulating film 15 so as to bury the upper portion of the trench to sandwich a second insulatingfilm 16. - An upper surface of the first insulating
film 13 and a lower surface of thegate electrode 17 are in contact with each other. An upper surface of thefield plate electrode 14 and a lower surface of the second insulatingfilm 16 are in contact with each other. An upper surface of the second insulatingfilm 16 and an upper surface of thesecond semiconductor layer 12 are substantially on the same plane. A width W2 of the secondinsulating film 16 is larger than a width W1 of thefield plate electrode 14, and is about 0.6 μm for example (W1<W2). - The
gate insulating film 15 is a thin silicon oxide film having a thickness of about 75 nm and obtained by thermally oxidizing side surfaces of the upper portion of the trench as will be described later. Thegate electrode 17 is a polysilicon film doped with P, for example. - The second insulating
film 16 is a silicon oxide film obtained by thermally oxidizing an entire area of the upper portion of thefield plate electrode 14. Therefore, in the second insulatingfilm 16, as in thefield plate electrode 14, P is doped in the polysilicon film. However, a concentration of P in the second insulatingfilm 16 lower than a concentration of P in thefield plate electrode 14 depending on an increase in volume by oxidation. - Since thermal oxidation also extends to the
field plate electrode 14 that is not exposed from the first insulatingfilm 13, an interface between the second insulatingfilm 16 and thefield plate electrode 14 is present to be slightly closer to thefirst semiconductor layer 11 than the upper surface of the first insulatingfilm 13. - A
base layer 18 of a second conductivity type (P-type) having a third impurity concentration is formed on an upper portion of thesecond semiconductor layer 12 adjacent to the trench. - A
source layer 19 of a first conductivity type (N+-type) having a fourth impurity concentration higher than the second impurity concentration is formed on the upper portion of thebase layer 18. - A voltage is applied to the
gate electrode 17 to form a channel in thebase layer 18 immediately under thegate electrode 17, so that thesource layer 19 and thefirst semiconductor layer 11 are electrically connected to each other. - A
third semiconductor layer 20 of a second conductivity type (P+-type) having a fourth impurity concentration higher than the third impurity concentration is formed at a central portion of thesource layer 19 to reach thebase layer 18 through thesource layer 19. - The
third semiconductor layer 20 is a carrier discharging layer that is formed to discharge carriers (holes) generated in thesecond semiconductor layer 12 when a PN junction between thebase layer 18 and thesecond semiconductor layer 12 breaks down during operation. - When the junction is broken down and carriers are not well discharged, heat is generated with movement of the carriers, and the
semiconductor device 10 may be thermally broken. For this reason, in addition to thesource layer 19, thethird semiconductor layer 20 to discharge carriers is formed on an upper portion of thebase layer 18 to make it difficult to thermally break thesemiconductor device 10. More specifically, an avalanche resistance is improved. - An interlayer insulating
film 21, a silicon oxide film, for example, is formed on portions of the second insulatingfilm 16, thegate electrode 17, and thesource layer 19. - A
source metal 22, aluminum (Al), for example, that is in contact with thesource layer 19 and thethird semiconductor layer 20 is formed on theinterlayer insulating film 21 to cover theinterlayer insulating film 21. - In the
first semiconductor layer 11, adrain metal 23, a gold-germanium alloy (AuGe), for example, is formed on a surface side facing thesecond semiconductor layer 12. - The
semiconductor device 10 of the embodiment is configured to moderate electric field concentration in thesecond semiconductor layer 12 with a vertical field plate structure including the first insulatingfilm 13 and thefield plate electrode 14 to obtain a high withstand voltage and to reduce a naturally increasing capacitance between thegate electrode 17 and thefield plate electrode 14 with the field plate structure. - Accordingly, since an input capacitance Ciss decreases, a product of an on-resistance Ron and the input capacitance Ciss decreases to make it possible to increase a figure of merit.
-
FIG. 12 is a cross-sectional view of asemiconductor device 50 of a comparative example, andFIG. 13 is a cross-sectional SEM image of thesemiconductor device 50 of the comparative example. - As shown in
FIGS. 12 and 13 , in thesemiconductor device 50 of the comparative example, afield plate electrode 51 is formed from a lower portion of a trench to an upper portion of the trench. Thegate electrode 17 is formed on the upper portion of the trench through thegate insulating film 15 to sandwich the upper portion of thefield plate electrode 51 through an insulatingfilm 52. -
FIG. 3 shows an inter-electrode capacitance generated in thesemiconductor device 50 of the comparative example, i.e., the input capacitance Ciss. In general, inter-electrode capacitances include a capacitance Cgd between thegate electrode 17 and thesecond semiconductor layer 12, a capacitance Cgs between thegate electrode 17 and thesource metal 22, a capacitance Cds between thefield plate electrode 51 and thesecond semiconductor layer 12, a capacitance Cgs1 of an inversion layer of a channel, and a capacitance Cgs2 between thegate electrode 17 and thefield plate electrode 51. - At this time, the input capacitance Ciss is expressed by a sum of the capacitance Cgd, the capacitance Cgs, the capacitance Cgs1, and the capacitance Cgs2, and given by Ciss=Cgd+Cgs+(Cgs1+Cgs2).
- The capacitance Cgs1 and the capacitance Cgd depend on the thickness of the
gate insulating film 15. Since the thickness of thegate insulating film 15 is uniquely determined in accordance with a threshold value, the capacitance Cgs1 and the capacitance Cgd cannot be set up arbitrarily, but take constant values. - The capacitance Cgs depends on a thickness of the
interlayer insulating film 21. Since the thickness of theinterlayer insulating film 21 is sufficiently larger than that of thegate insulating film 15, the capacitance Cgs is sufficiently small. Subsequently, it is assumed that the capacitance Cgs can be neglected. - The capacitance Cgs2 depends on a thickness of the insulating
film 52. When the insulatingfilm 52 is increased in thickness, the capacitance Cgs2 decreases.FIG. 4 is a diagram showing a result obtained by simulating a relationship between the input capacitance Ciss and the thickness of the insulatingfilm 52. - As shown in
FIG. 4 , ratios of the capacitance Cgs1 and the capacitance Cgs2 to the input capacitance Ciss are large, and a ratio of the capacitance Cgd to the input capacitance Ciss is small. When the thickness of the insulatingfilm 52 is increased to 85 nm, 145 nm, and 250 nm in the order, the capacitance Cgs2 decreases. However, as described above, the capacitance Cgs1 and the capacitance Cgd do not change. This is because the thickness of thegate insulating film 15 is constant. - Therefore, in order to improve the figure of merit, the thickness of the insulating
film 52 is desirably increased in thickness as much as possible to reduce the capacitance Cgs2. This is because the thickness of the insulatingfilm 52 does not influence a withstand voltage and the on-resistance Ron. - In order to increase the insulating
film 52 in thickness, the upper portion of thefield plate electrode 51 facing thegate electrode 17 is desirably thinned to be zero in the ultimate sense. This is because, since thefield plate electrode 51 is continuously electrically connected to thesource layer 19 without the upper portion, thefield plate electrode 51 cannot disturb the function of the field plate structure. On the other hand, a decrease in thickness of thegate electrode 17 is not desired because the gate resistance increases. - Since the capacitance Cds between the
field plate electrode 51 and thesecond semiconductor layer 12 does not directly influence the figure of merit, a description of the capacitance Cds will be omitted. - In the
semiconductor device 10 of the embodiment, since thefield plate electrode 14 of which the upper portion is eliminated is realized, the capacitance Cgs2 can be made a sufficiently small value that is negligible. Accordingly, the input capacitance Ciss decreases, and the product of the on-resistance Ron and the input capacitance Ciss decreases to make it possible to increase the figure of merit. - A method for manufacturing the
semiconductor device 10 will be described.FIGS. 5A to 10B are cross-sectional views sequentially showing the steps of manufacturing thesemiconductor device 10. - As shown in
FIG. 5A , thesecond semiconductor layer 12 is formed on thefirst semiconductor layer 11 by vapor phase growth. More specifically, dichlorosilane (SiH2Cl2) is used as a process gas, for example, a phosphine (PH3) is used as a dopant gas, and hydrogen (H2) is used as a carrier gas. Thesecond semiconductor layer 12 is epitaxially grown on thefirst semiconductor layer 11 at a temperature of 1000° C. - As shown in
FIG. 5B , a mask material (not shown) having a stripe shaped opening is formed on thesecond semiconductor layer 12, and thesecond semiconductor layer 12 is anisotropically etched by a RIE (Reactive Ion Etching) method using a fluorine-based gas, for example, to form atrench 40. - As shown in
FIG. 6A , asilicon oxide film 41 is conformally formed on an internal surface of thetrench 40 by a CVD (Chemical Vapor Deposition) method, for example. Thesilicon oxide film 41 serves as the first insulatingfilm 13 in the subsequent steps. - As shown in
FIG. 6B , apolysilicon film 42 doped with P is formed by a CVD method, for example, to bury thetrench 40 through thesilicon oxide film 41. Thepolysilicon film 42 serves as thefield plate electrode 14 in the subsequent steps. - As shown in
FIG. 7A , thepolysilicon film 42 is anisotropically etched by an RIE method using a chlorine-based gas and fluorine-based gas, for example. The anisotropic etching is performed until the upper surface of thepolysilicon film 42 and the upper surface of thesecond semiconductor layer 12 are at substantially the same level. - As shown in
FIG. 7B , thesilicon oxide film 41 is anisotropically etched by an RIE method using a fluorine-based gas, for example. The anisotropic etching is performed until the upper portion of the trench and the upper portion of thepolysilicon film 42 are exposed. Thesilicon oxide film 41 that is not anisotropically etched serves as the first insulatingfilm 13. - As shown in
FIG. 8A , the upper portion of the exposed trench and the upper portion of the exposedpolysilicon film 42 are thermally oxidized. The thermal oxidization is performed under a condition in which enhanced oxidation of thepolysilicon film 42 easily occurs by low-temperature hydrogen burning oxidation, for example. - The hydrogen burning oxidation is an oxidizing method that performs oxidization in a wet atmosphere containing water vapor generated by burning hydrogen. The hydrogen burning oxidation is advantageously cleaner more than steam oxidation that generates water vapor by using a water bubbler, and advantageously obtains controllability higher than that of the steam oxidation.
- Referring to
FIG. 11 , enhanced oxidation in the hydrogen burning oxidation will be described.FIG. 11 is a diagram showing an example of a relation between a temperature and a relative enhanced oxidation rate (a ratio of an oxidation rate of thepolysilicon film 42 to an oxidation rate of a side surface of the trench 40). - As shown in
FIG. 11 , in the low-temperature hydrogen burning oxidation at a temperature of about 800° C. to about 900° C., polysilicon doped with P at a high concentration is oxidized at a rate about 2.5 to 4.5 times higher than the oxidation rate of silicon. Upper and lower plots show fluctuations in the relative enhanced oxidation rate. On the other hand, when a temperature becomes high, the relative enhanced oxidation rate decreases. At a temperature of 1050° C., the ratio decreases to 1.5 times or less. - The relative enhanced oxidation rate increases at a low temperature because activation energy of silicon to thermal oxidation is higher than activation energy of polysilicon. More specifically, this is because, when the temperature becomes low, an oxidation rate of silicon sharply decreases, and an oxidation rate of polysilicon moderately decreases.
- As a result, the thin
gate insulating film 15 is formed on an upper side surface of the exposed trench. The upper portion of the exposedpolysilicon film 42 is entirely oxidized and modified into the second insulatingfilm 16 having a thickness that is about 1.4 times larger than that of theoriginal polysilicon film 42. The unexposedlower polysilicon film 42 serves as thefield plate electrode 14. - Since the enhanced oxidation extends from the first insulating
film 13 to theunexposed polysilicon film 42, an interface between the second insulatingfilm 16 and thefield plate electrode 14 is present to be slightly closer to the bottom surface side of thetrench 40 than the upper surface of the first insulatingfilm 13. - Therefore, the hydrogen burning oxidation may be performed simultaneously with the oxidation of the entire upper portion of the
polysilicon film 42 or may be performed under an enhanced oxidation condition that obtains thegate insulating film 15 having a target thickness after the oxidation of the entire upper portion of thepolysilicon film 42. In order to obtain the second insulatingfilm 16 having a thickness of about 0.6 μm, for example, and thegate insulating film 15 having a thickness of about 75 nm, the enhanced oxidation condition is set such that the relative enhanced oxidation rate is 4 or more. - Returning to
FIG. 8B , the second insulatingfilm 16 is covered by a CVD method, for example, and apolysilicon film 43 doped with P is formed to bury the upper portion of the exposed trench. Thepolysilicon film 43 serves as thegate electrode 17 in the subsequent steps. - As shown in
FIG. 9A , thepolysilicon film 43 is removed by a CDE (Chemical Dry Etching) method using a fluorine-based gas, for example or a CMP (Chemical Mechanical Polishing) method, until the upper surface of thesecond semiconductor layer 12 is exposed. Thepolysilicon film 43 which is not removed serves as thegate electrode 17. - In this manner, the
gate electrode 17 buried into the upper portion of the trench through thegate insulating film 15 to sandwich the second insulatingfilm 16 is formed. - As shown in
FIG. 9B , after a mask material (not shown) having an opening that exposes thesecond semiconductor layer 12 is formed, boron (B) is ion-implanted in thesecond semiconductor layer 12 to form thebase layer 18 on the upper portion of thesecond semiconductor layer 12. - As shown in
FIG. 10A , after a mask material (not shown) having an opening that exposes thebase layer 18 is formed, P is ion-implanted in thebase layer 18 to form thesource layer 19 on the upper portion of thebase layer 18. - As shown in
FIG. 10B , theinterlayer insulating film 21 having an opening that exposes a central portion of thesource layer 19, a silicon oxide film obtained by a CVD method, for example, is formed. B is ion-implanted in the central portion of thesource layer 19 by using theinterlayer insulating film 21 as a mask, and thethird semiconductor layer 20 that reaches thebase layer 18 through thesource layer 19 is formed. - As the
source metal 22, an Al film that covers theinterlayer insulating film 21 and are in contact with thesource layer 19 and thethird semiconductor layer 20 is formed by a sputtering method, for example. As thedrain metal 23, an AuGe alloy film is formed on a surface of thefirst semiconductor layer 11 facing thesecond semiconductor layer 12 by an evaporation method, for example. In this manner, thesemiconductor device 10 shown inFIG. 1 is obtained. - As described above, in the embodiment, the
field plate electrode 14 buried into the lower portion of the trench through the first insulatingfilm 13 is formed, and thegate electrode 17 buried into the upper portion of the trench through thegate insulating film 15 to sandwich the second insulatingfilm 16 is formed. - As a result, the capacitance Cgs2 between the
field plate electrode 14 and thegate electrode 17 decreases. When the input capacitance Ciss decreases, the product of the on-resistance Ron and the input capacitance Ciss becomes small so as to increase the figure of merit. Therefore, a semiconductor device which reduces a capacitance between a gate electrode and a field plate electrode is and a method for manufacturing the semiconductor device can be obtained. - When the
semiconductor device 10 shown inFIG. 1 is used as a semiconductor device to which a high withstand voltage of 100 V to 200 V, for example, is applied, the following effect can be obtained. Although a trench width of a high-withstand voltage semiconductor device is designed to 1 to 2.5 μm, the trench width is larger than that of a low-withstand voltage semiconductor device. For this reason, in a high-withstand voltage semiconductor device that does not include the second insulatingfilm 16, thepolysilicon film 43 having an overwhelming film thickness needs to be formed on thefield plate electrode 14 to bury the upper portion of the trench with thegate electrode 17. In the embodiment, the upper portion of thefield plate electrode 14 is covered with the second insulatingfilm 16, and thefield plate electrode 14 is formed at a position lower than thegate electrode 17. For this reason, the trench is advantageously buried and filled. - In the specification, the description is given of the case where the first conductive type and the second conductive type are an N type and a P type, respectively. However, the first conductive type and the second conductive type may be a P type and an N type, respectively.
- The description is given of the case where thermal oxidation of the upper portion of the exposed trench and the upper portion of the exposed
poly silicon film 42 is performed by hydrogen burning oxidation. However, any condition in which enhanced oxidation of thepolysilicon film 42 is performed may be used to obtain the targetgate insulating film 15 and the target second insulatingfilm 16. The thermal oxidation can also be performed by another method, steam oxidation, for example. - While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the devices described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Claims (18)
1. A semiconductor device, comprising:
a first semiconductor layer of a first conductivity type having a first impurity concentration;
a second semiconductor layer of the first conductivity type formed on the first semiconductor layer and having a second impurity concentration lower than the first impurity concentration;
a field plate electrode formed in a lower portion of a trench formed in the second semiconductor layer on a bottom surface side of the trench through a first insulating film so as to bury the lower portion of the trench;
a second insulating film formed in the upper portion of the trench so as to be in contact with the top surface of the field plate electrode;
a gate electrode formed in the upper portion of the trench on an opening side of the trench through a gate insulating film so as to bury the upper portion of the trench to sandwich the second insulating film;,
a base layer of a second conductivity type formed in the upper portion of the second semiconductor layer and having a third impurity concentration; and
a source layer of the first conductivity type formed in the upper portion of the base layer and having a fourth impurity concentration higher than the second impurity concentration.
2. The semiconductor device according to claim 1 , wherein the second insulating film is a thermal oxide film of the field plate electrode.
3. The semiconductor device according to claim 1 , wherein the width of the second insulating film is larger than the width of the field plate electrode.
4. The semiconductor device according to claim 1 , wherein the impurity concentration of the second insulating film is lower than the impurity concentration of the field plate electrode.
5. The semiconductor device according to claim 1 , wherein the top surface of the first insulating film is in contact with the bottom surface of the gate electrode.
6. The semiconductor device according to claim 1 , wherein the top surface of the second insulating film is substantially flush with the top surface of the second semiconductor layer.
7. The semiconductor device according to claim 1 , wherein the interface between the second insulating film and the field plate electrode is in the bottom surface side of the trench from the top surface of the first insulating film.
8. The semiconductor device according to claim 1 , wherein the field plate electrode is electrically connected to the source layer.
9. The semiconductor device according to claim 1 , wherein a capacitance between the gate electrode and the field plate electrode is smaller than a capacitance between the gate electrode and the base layer.
10. The semiconductor device according to claim 1 , further comprising:
a third semiconductor layer of the second conductivity type formed in the central portion of the source layer so as to reach the base layer through the source layer, the third semiconductor layer having a fourth impurity concentration larger than the third impurity concentration.
11. The semiconductor device according to claim 10 , wherein a third semiconductor layer discharges a carrier generated in the second semiconductor layer when p-n junction between the base layer and the second semiconductor layer breaks down.
12. A method for manufacturing a semiconductor device, comprising:
forming a second semiconductor layer of a first conductivity type having a second impurity concentration on a first semiconductor layer of the first conductivity type having a first impurity concentration, the second impurity concentration being lower than the first impurity concentration;
forming a trench in the second semiconductor layer;
forming a first conductive film in the trench through a first insulating film so as to bury the trench;
removing the first insulating film of the upper portion of the trench on an opening side of the trench so as to expose the upper portion of the trench and the upper portion of the first conductive film;
oxidizing the side surface of the upper portion of the exposed trench and the upper portion of the exposed first conductive film so as to form a gate insulating film on the side surface of the upper portion of the trench and modify the entire upper portion of the first conductive film into a second insulating film;
forming a gate electrode in the upper portion of the trench through the gate insulating film so as to bury the upper portion of the trench to sandwich the second insulating film;
forming a base layer having a third impurity concentration on the upper portion of the second semiconductor layer; and
forming a source layer of the first conductivity type having a fourth impurity concentration higher than the second impurity concentration on the upper portion of the base layer.
13. The method for manufacturing the semiconductor device according to claim 12 , wherein the gate insulating film of the target thickness is obtained simultaneously with or after the oxidation of the entire upper portion of the first conductive film.
14. The method for manufacturing the semiconductor device according to claim 12 , wherein the side surface of the upper portion of the exposed trench and the upper portion of the exposed first conductive film are thermally oxidized by low-temperature hydrogen burning oxidation.
15. The method for manufacturing the semiconductor device according to claim 14 , wherein low-temperature hydrogen burning oxidation is performed at a temperature of about 800° C. to about 900° C.
16. The method for manufacturing the semiconductor device according to claim 14 , wherein a ratio of an oxidation rate of the first conductive film to an oxidation rate of the second semiconductor layer is 4 or more.
17. The method for manufacturing the semiconductor device according to claim 12 , wherein the side surface of the upper portion of the exposed trench and the upper portion of the exposed first conductive film are thermally oxidized by steam oxidation.
18. The method for manufacturing the semiconductor device according to claim 12 , further comprising:
forming a third semiconductor layer of the second conductivity type having a fourth impurity concentration larger than the third impurity concentration so as to reach the base layer through the source layer.
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US20140179094A1 (en) | 2014-06-26 |
US9184261B2 (en) | 2015-11-10 |
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