JP2020004883A - Semiconductor device, electric device, and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a parasitic capacitance of a gate electrode in a semiconductor device including a gate electrode in a trench and a field plate electrode located on the anti-opening side of the trench with respect to the gate electrode. A semiconductor layer (20) having a trench (25A, 25B), a gate electrode (31a to 31d) arranged in the trench and facing the inner side surface of the trench, and a counter-opening side of the trench with respect to the gate electrode. It is a semiconductor device (10) provided with a field plate electrode (34A, 34B) located at. Then, when viewed in the depth direction of the trench, at least a part of the surface of the field plate electrode (34A, 34B) on the opening side of the trench does not overlap with the surface of the gate electrode (31a to 31d) on the opposite opening side. [Selection diagram] Fig. 1

Description

  The present disclosure relates to a semiconductor device, an electric device, and a method for manufacturing a semiconductor device.

  2. Description of the Related Art A vertical MOSFET (Metal-Oxide Silicon Field-Effect Transmitter) having a gate electrode housed in a trench has been known as a semiconductor device. Patent Document 1 discloses a configuration in which a vertical MOSFET has a field plate electrode (hereinafter, referred to as an “FP electrode”) at a position deeper than a gate electrode.

JP-A-2006-063004

  When the FP electrode is provided below the gate electrode as in the MOSFET of Patent Document 1, a parasitic capacitance is generated at a portion where the gate electrode and the FP electrode face each other. As the parasitic capacitance of the gate electrode increases, the switching speed of the MOSFET decreases.

  An object of the present disclosure is to reduce a parasitic capacitance of a gate electrode in a semiconductor device including a gate electrode in a trench and a field plate electrode located on an opposite side of the trench from the gate electrode. Another object of the present disclosure is to provide an electric device including such a semiconductor device and a method for manufacturing the semiconductor device.

A semiconductor device according to an embodiment of the present disclosure includes:
A semiconductor layer having a trench;
A gate electrode disposed in the trench and facing an inner side surface of the trench;
A field plate electrode located on the side opposite to the opening of the trench than the gate electrode,
When viewed in the depth direction of the trench, at least a part of the surface of the field plate electrode on the opening side of the trench does not overlap with the surface of the gate electrode on the side opposite to the opening.

An electric device according to an embodiment of the present disclosure includes:
A semiconductor layer having a trench;
A gate electrode disposed in the trench and facing an inner side surface of the trench;
A field plate electrode located on the side opposite to the opening of the trench than the gate electrode,
A semiconductor device is provided in which at least a part of a surface of the field plate electrode on the opening side of the trench does not overlap with a surface of the gate electrode on the side opposite to the opening when viewed in a depth direction of the trench.

A method for manufacturing a semiconductor device according to an embodiment of the present disclosure includes:
Forming a trench extending from the first surface toward the second surface in a first semiconductor layer having a first surface and a second surface opposite to the first surface;
Forming a field plate electrode in the trench;
Forming an insulating film on the opening side of the trench relative to the field plate electrode in the trench;
Forming a gate electrode in the trench where the insulating film is formed;
Including
The step of forming the gate electrode includes the step of forming at least a part of the surface of the field plate electrode on the opening side as viewed from the field plate electrode on the opening side and in the depth direction of the trench. Forming a gate electrode at a position where the gate electrode does not overlap the surface on the second surface side of the electrode.

  According to the present disclosure, in a semiconductor device including a gate electrode in a trench and a field plate electrode located on a side opposite to the opening of the trench with respect to the gate electrode, an effect that a parasitic capacitance of the gate electrode can be reduced is obtained. According to the present disclosure, a method for manufacturing such a semiconductor device can be further provided.

1 is a cross-sectional view illustrating a MOSFET according to an embodiment of the present disclosure. It is sectional drawing which shows MOSFET of the comparative example. FIGS. 3A to 3C are cross-sectional views illustrating first to third steps of the method for manufacturing a MOSFET according to the embodiment of the present disclosure. 4A to 4C are cross-sectional views illustrating fourth to sixth steps of the method for manufacturing the MOSFET according to the embodiment of the present disclosure. 5A to 5C are cross-sectional views illustrating seventh to ninth steps of the method for manufacturing the MOSFET according to the embodiment of the present disclosure. 6A to 6C are cross-sectional views illustrating the tenth to twelfth steps of the method for manufacturing a MOSFET according to the embodiment of the present disclosure, respectively. 7A to 7C are cross-sectional views illustrating the thirteenth to fifteenth steps of the method for manufacturing a MOSFET according to the embodiment of the present disclosure.

  Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the embodiment, the first conductivity type will be described as n-type, and the second conductivity type different from the first conductivity type as p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type. The density of the impurity concentration of the n-type semiconductor layer is expressed as “n +, n−” from the darkest one.

  FIG. 1 is a cross-sectional view illustrating a MOSFET according to an embodiment of the present disclosure.

  The MOSFET 10 according to the embodiment includes a semiconductor layer 20, trenches 25A and 25B, gate electrodes 31a to 31d, a source electrode 32, a drain electrode 33, and FP electrodes 34A and 34B. Further, the MOSFET 10 includes insulating films 41a to 41d, 42A, 42B and insulating portions 43A, 43B, 44A, 44B. The MOSFET 10 corresponds to an example of a semiconductor device according to the present disclosure.

  In the present embodiment, the opening side of the trenches 25A and 25B is defined as an upper side, the opposite side is defined as a lower side, and the depth direction of the trenches 25A and 25B is defined as a height direction Z. The direction (left-right direction in the drawing) from one gate electrode 31a, 31c to the other gate electrode 31b, 31d in the trenches 25A, 25B is defined as the width direction X of the trenches 25A, 25B. The upper part of FIG. 1 is the opening side of the trenches 25A and 25B, and the lower part of FIG. 1 is the opposite opening side of the trenches 25A and 25B.

  The semiconductor layer 20 includes a silicon substrate and a thin film epitaxially grown thereon. The semiconductor layer 20 includes an n + type drain layer 23, an n − type drift layer 22, a p type base layer 21, and n + type source regions 24a to 24d. The semiconductor layer 20 does not include a p-type layer between the base layer 21 and the drain electrode 33. Of the two upper and lower surfaces of the semiconductor layer 20, the surface opposite to the drain layer 23 is called a first surface S1, and the side of the drain layer 23 is called a second surface S2.

  The trenches 25A and 25B extend from the first surface S1 of the semiconductor layer 20 toward the second surface S2 to the depth of the drift layer 22. The trenches 25A and 25B extend, for example, linearly in the depth direction (the direction perpendicular to the paper surface). The openings of the trenches 25A and 25B are located on the first surface S1.

  The FP electrodes 34A and 34B are located on the side opposite to the opening in the trenches 25A and 25B, respectively, at the depth of the drift layer 22. That is, the upper end surfaces of the FP electrodes 34A and 34B are located lower than the lower end surfaces of the gate electrodes 31a to 31d. The FP electrodes 34A and 34B are provided at positions overlapping the openings of the trenches 25A and 25B, respectively, when viewed from the height direction Z. The FP electrodes 34A and 34B are supplied with, for example, the same potential as the source electrode 32 via wiring electrodes (not shown). The FP electrodes 34A and 34B alleviate the electric field concentrated on a part of the semiconductor layer 20, and improve the breakdown voltage of the MOSFET 10.

  The insulating portions 43A, 43B and the insulating films 42A, 42B surround the FP electrodes 34A, 34B in the trenches 25A, 25B, respectively, insulate the FP electrodes 34A, 34B and the drift layer 22, and form the insulating layers 43A, 43B with the FP electrodes 34A, 34B. The gate electrodes 31a to 31d are insulated. The insulating films 42A and 42B extend from the upper end surfaces of the FP electrodes 34A and 34B to the height range of the lower end surfaces of the gate electrodes 31a to 31d, and connect the FP electrodes 34A and 34B and the gate electrodes 31a to 31d in the height direction. Separate at Z.

  The gate electrodes 31a to 31d are, for example, polysilicon, and are located closer to the opening than the FP electrodes 34A, 34B in the trenches 25A, 25B. First, the gate electrodes 31a and 31b of one trench 25A will be described. In one trench 25A, the gate electrodes 31a and 31b face one inner surface and the other inner surface in the width direction X of the trench 25A, respectively. One gate electrode 31a and the other gate electrode 31b are separated from each other, and an intermediate region WA where no gate electrode is provided is provided in a separated portion, that is, a middle portion in the width direction X of the trench 25A. The intermediate region WA where no gate electrode exists is a region including the center in the width direction X of the trench 25A. The intermediate area WA may be deviated from a central point in the width direction X of the trench 25A. The gate electrode 31a corresponds to an example of a first gate electrode according to the present disclosure. The gate electrode 31b corresponds to an example of a second gate electrode according to the present disclosure.

  The intermediate region WA where no gate electrode is present has substantially the same width as the FP electrode 34A, and the intermediate region WA and the FP electrode 34A are arranged at approximately the same position in the width direction X. With this configuration, when viewed from the height direction Z, the entire upper surface of the FP electrode 34A does not overlap the lower surfaces of the gate electrodes 31a and 31b. Further, the entire upper surface of the FP electrode 34A and the lower surfaces of the gate electrodes 31a and 31b do not face each other in the height direction Z. These relationships may be established in the width direction X of the trench 25A, or may be established in the entire range of the trench 25A in the width direction X and the depth direction. The upper surface of the FP electrode 34A means, of the upper surface of the FP electrode 34A, a surface whose vertical line is closer to the vertical direction than the horizontal direction. The lower surfaces of the gate electrodes 31a and 31b mean surfaces of the lower surfaces of the gate electrodes 31a and 31b whose vertical lines are closer to the vertical direction than the horizontal direction.

  Note that there may be a difference between the width of the intermediate region WA where no gate electrode is present and the width of the FP electrode 34A, and there is a difference between the positions of the intermediate region WA and the FP electrode 34A in the width direction X. You may. Even in these cases, at least a part of the upper surface of the FP electrode 34A does not overlap with the lower surfaces of the gate electrodes 31a and 31b when viewed from the height direction Z. Further, at least a part of the upper surface of the FP electrode 34A and the lower surfaces of the gate electrodes 31a and 31b do not face each other in the height direction Z.

  In addition, one gate electrode 31b may be omitted, and one gate electrode 31a may be provided in one trench 25A. In this case, the width of the gate electrode 31a is smaller than half of the inner dimension of the trench 25A in the width direction X, and the gate electrode 31a may be arranged to be biased to one side in the width direction X of the trench 25A.

  Similarly, in the other trench 25B, gate electrodes 31c and 31d and intermediate region WB where no gate electrode exists are provided. The relationship between the intermediate region WB and the FP electrode 34B is the same as the relationship between the intermediate region WA and the FP electrode 34A.

  The insulating films 41a to 41d are located on side walls of the trenches 25A and 25B, and insulate the gate electrodes 31a to 31d from the base layer 21, the drift layer 22, and the source regions 24a to 24d.

  The insulating portions 44A and 44B fill the regions where the gate electrodes 31a to 31d are not present in the trenches 25A and 25B, respectively, and are interposed between the gate electrodes 31a to 31d and the source electrode 32 at the openings of the trenches 25A and 25B. And insulate them.

  The source electrode 32 is an electrode layer located above the MOSFET 10 and is in contact with the first surface S1 of the semiconductor layer 20 and the upper surfaces of the insulating portions 44A and 44B, and is electrically connected to the base layer 21 and the source regions 24a to 24d. You.

  The drain electrode 33 is an electrode layer located below the MOSFET 10, contacts the second surface S <b> 2 of the semiconductor layer 20, and is electrically connected to the drain layer 23.

  According to the MOSFET 10 configured as described above, when a voltage is applied between the drain electrode 33 and the source electrode 32 when the voltage between the gate electrodes 31a to 31d and the source electrode 32 is zero, the base layer 21 A depletion layer is formed between and drift layer 22. As a result, no current flows from the drain electrode 33 to the source electrode 32. On the other hand, when a voltage is applied between the gate electrodes 31a to 31d and the source electrode 32, an electric field is applied to the base layer 21 from the gate electrodes 31a to 31d near the outer surfaces of the trenches 25A and 25B. Then, the conductivity type of the portion of the base layer 21 facing the gate electrodes 31a to 31d is reversed, a channel layer is formed, and a current flows from the drain electrode 33 to the source electrode 32 through the channel layer.

  During the operation of the MOSFET 10, the same potential as that of the source electrode 32 is applied to the FP electrodes 34A and 34B, thereby alleviating the concentration of the electric field on a part of the semiconductor layer 20 and improving the breakdown voltage of the MOSFET 10. As described above, the FP electrodes 34A and 34B are provided below the gate electrodes 31a to 31d, but in the width direction X, at least a part of the upper surfaces of the FP electrodes 34A and 34B and the lower surfaces of the gate electrodes 31a to 31d. Do not overlap in the height direction Z.

  FIG. 2 is a cross-sectional view illustrating a MOSFET of a comparative example. In the MOSFET 100 of the comparative example, the gate electrodes 131A and 131B are accommodated in the trenches 125A and 125B, and the FP electrodes 134A and 134B are provided at the bottom of the trenches 125A and 125B. As in the comparative example, when the FP electrodes 134A and 134B and the gate electrodes 131A and 131B face each other, the parasitic capacitance C1A and C1B therebetween increases. However, in the MOSFET 10 of the present embodiment, the above configuration reduces the parasitic capacitance between the FP electrodes 34A and 34B and the gate electrodes 31a to 31d, and improves the switching speed of the MOSFET 10.

<Electric equipment>
The electric device according to the embodiment of the present disclosure includes the MOSFET 10. The electric device may be, for example, a power module having a power supply circuit that performs power conversion. Alternatively, the electrical device may be various electronic devices, automobiles, aircraft, and the like. The electric device may include the MOSFET 10 as a switching device.

<Production method>
3A to 7C are cross-sectional views illustrating the first to fifteenth steps of the method for manufacturing a MOSFET according to the embodiment of the present disclosure. The MOSFET 10 can be manufactured through the following first to fifteenth steps in order.

  In the first step, as shown in FIG. 3A, a trench is formed in the semiconductor layer 20i having the n + layer and the n − layer from the first surface S1 toward the second surface S2 by, for example, reactive ion etching. This is a step of forming 25A and 25B. The n + layer is a semiconductor substrate to be the drain layer 23. The n- layer is an epitaxial layer formed on a semiconductor substrate. The semiconductor layer 20i corresponds to an example of a first semiconductor layer according to the present disclosure.

  In the second step, as shown in FIG. 3B, a field insulating film 43i is formed on the exposed surface on the first surface S1 side by a thermal oxidation method or a CVD (chemical vapor deposition) method. The field insulating film 43i is formed on the inner surfaces of the trenches 25A and 25B and above the first surface S1 of the semiconductor layer 20. The field insulating film 43i is formed at the center in the width direction X of the trenches 25A and 25B so as not to entirely fill the height direction Z. A part of the field insulating film 43i then becomes insulating portions 43A and 43B.

  In the third step, as shown in FIG. 3C, a polysilicon 34i is formed by a CVD method on the upper side of the field insulating film 43i, including the space not filled with the field insulating film 43i in the trenches 25A and 25B. This is the step of doing.

  In the fourth step, as shown in FIG. 4A, a part of the polysilicon 34i disposed below the trenches 25A and 25B is left, and the other polysilicon 34i is removed by etching.

  In the fifth step, as shown in FIG. 4B, the upper part of the polysilicon 34i is oxidized by a thermal oxidation method, and the insulating films 42A and 42B are formed thereon. Since the first surface S1 side of the semiconductor layer 20 and the second surface S2 side of the semiconductor layer 20 are not exposed, they are not oxidized. Here, the lower portions of the unoxidized polysilicon 34i are the FP electrodes 34A and 34B. As a fifth step, a step of forming the insulating films 42A and 42B by a CVD method may be adopted. The insulating films 42A and 42B correspond to an example of a first insulating film according to the present disclosure.

  In a sixth step, as shown in FIG. 4C, the field insulating film 43i on the upper side of the semiconductor layer 20 is removed by etching, and the field insulating film 43i in the trenches 25A and 25B is removed by the insulating films 42A and 42B. This is a step of removing up to the height of the upper surface of. The remaining portions of the field insulating film 43i are the insulating portions 43A and 43B.

  In the seventh step, as shown in FIG. 5A, an insulating film 41i is formed on the exposed inner surfaces of the trenches 25A and 25B and the upper side of the first surface S1 of the semiconductor layer 20 by a thermal oxidation method or a CVD method. This is the step of forming The insulating film 41i is formed thinner than the field insulating film 43i in the second step. Note that when the insulating film 41i is formed by a thermal oxidation method, the insulating film 41i is formed between the upper portions of the insulating portions 43A and 43B and the upper portions of the insulating films 42A and 42B in FIG. It may not be formed. The insulating film 41i corresponds to an example of a second insulating film according to the present disclosure.

  The eighth step is a step of depositing a polysilicon film 31i from the first surface S1 side, as shown in FIG. 5B. The polysilicon film 31i is formed so as not to completely fill the trenches 25A and 25B, but to have a concave portion in the width direction X of the trenches 25A and 25B. The polysilicon film 31i is deposited on a portion including the portion where the field insulating film 43i has been removed in the sixth step.

  In the ninth step, as shown in FIG. 5C, in the polysilicon film 31i formed in the eighth step, the center of the trenches 25A and 25B in the width direction X, the outside of the trenches 25A and 25B, and the trench are formed. This is a step of removing portions above the openings 25A and 25B. As a result, portions of the polysilicon film 31i facing the inner side surfaces of the trenches 25A and 25B are left, and these are the gate electrodes 31a to 31d. At this time, of the upper portions of the gate electrodes 31a to 31d, the sides near the centers of the trenches 25A and 25B may be cut to form inclined surfaces Ra to Rd. This step can be realized by, for example, a photolithography and etching process.

  The tenth step is, as shown in FIG. 6A, a step of removing the insulating film 41i above the first surface S1 of the semiconductor layer 20 by etching. The remaining insulating films 41i are the insulating films 41a to 41d.

  In an eleventh step, as shown in FIG. 6B, an n + conductivity type impurity and a p conductivity type impurity are ion-implanted from the first surface S1 side of the semiconductor layer 20, and further, these are thermally diffused. Forming the base layer 21 and the source regions 24a to 24d. When forming the source regions 24a to 24d, an oxidation process for forming an oxide film may be inserted before ion implantation, so that an n + conductivity type impurity is implanted only in a specific region. Further, the base layer 21 may be implanted with ap + conductivity type impurity. The drift layer 22 is an epitaxial layer to which the diffusion of impurities does not reach. The base layer 21 and the source regions 24a to 24d correspond to an example of a second semiconductor layer and a third semiconductor layer according to the present disclosure.

  In the twelfth step, as shown in FIG. 6C, the interlayer insulating film 44i is formed by CVD on the first surface S1 side of the trenches 25A, 25B and the semiconductor layer 20, including the spaces in the trenches 25A, 25B. This is the step of forming The interlayer insulating film 44i insulates the gate electrodes 31a to 31d from the source electrode 32.

  In a thirteenth step, as shown in FIG. 7A, an interlayer insulating film is formed by etching so that the base layer 21 and a part of the source regions 24a to 24d are exposed outside the trenches 25A and 25B. 44i is a step of removing a part of 44i. The remaining interlayer insulating film 44i is the insulating portions 44A and 44B.

  In a fourteenth step, an Al-Si (aluminum-silicon) alloy film, for example, is formed as a source electrode 32 on the exposed semiconductor layer 20 and the interlayer insulating film 44i by sputtering, as shown in FIG. 7B. This is the step of doing. By adding Si in advance, the AL-Si alloy film also functions as a barrier metal that prevents spikes of the AL into the semiconductor layer 20. The fourteenth step may include a step of forming another barrier metal layer on the exposed semiconductor layer 20 and the interlayer insulating film 44i, and a step of forming a metal film serving as the source electrode 32 thereon. Good.

  The fifteenth step is a step of forming a metal film to be the drain electrode 33 below the second surface S2 of the semiconductor layer 20 by sputtering, as shown in FIG. 7C.

  As described above, according to the MOSFET 10 of the present embodiment, when viewed from the height direction Z of the trenches 25A and 25B, part or all of the upper surfaces of the FP electrodes 34A and 34B overlap the lower surfaces of the gate electrodes 31a to 31d. No. Thereby, the parasitic capacitance generated between them can be reduced, and the switching speed of the MOSFET 10 is improved.

  Further, according to the MOSFET 10 of the present embodiment, the gate electrodes 31a to 31d are arranged except for the central portions of the trenches 25A and 25B in the width direction X. This makes it possible to realize a configuration in which part or all of the upper surfaces of the FP electrodes 34A and 34B do not face the lower surfaces of the gate electrodes 31a to 31d.

  Further, according to the MOSFET 10 of the present embodiment, one trench 25A houses the gate electrode 31a facing one inner surface of the trench 25A and the gate electrode 31b facing the other inner surface of the trench 25A. The gate electrodes 31a and 31b are separated from each other. Thus, a configuration can be realized in which an area where the gate electrodes 31a to 31d face the base layer 21 does not face a part or all of the upper surfaces of the FP electrodes 34A and 34B and the lower surfaces of the gate electrodes 31a to 31d. .

  Further, the MOSFET 10 of the present embodiment does not have a conductive type (p-type) semiconductor layer different from the drift layer 22 below the FP electrodes 34A and 34B. The FP electrodes 34A and 34B located below the gate electrodes 31a to 31d are located below the FP electrodes 34A and 34B with respect to a MOSFET having no conductive (p-type) semiconductor layer different from the drift layer 22. Particularly, the concentration of the electric field in the semiconductor layer 20 can be effectively reduced. Therefore, a configuration in which the parasitic capacitance is reduced is particularly effective for a vertical MOSFET having no different conductivity type (p-type) layer below the drift layer 22.

  The embodiments of the present disclosure have been described above. However, the present disclosure is not limited to the above embodiment. For example, the semiconductor substrate may be a substrate containing various semiconductors such as silicon carbide (SiC), gallium nitride or gallium nitride (GaN), and gallium oxide (Ga2O3) in addition to a silicon substrate. In the above embodiments, the MOSFET has been described as an example of the semiconductor device according to the present disclosure.However, if the semiconductor device has a gate electrode in the trench and an FP electrode located on the opposite side of the trench from the gate electrode, Not limited to MOSFET. All the drawings described in the embodiments are schematic diagrams. The relative dimensions of the illustrated parts may be changed to be larger or smaller as appropriate. The boundaries between the layers and regions illustrated in the drawings may not be clear. The detailed structure and method shown in the embodiment can be appropriately changed without departing from the spirit of the invention.

10 MOSFET (semiconductor device)
Reference Signs List 20 semiconductor layer 21 base layer 22 drift layer 23 drain layer 24a to 24d source region 25A, 25B trench 31a to 31d gate electrode 32 source electrode 33 drain electrode 34A, 34B FP electrode 41a to 41d, 42A, 42B insulating film 43A, 43B, 44A, 44B Insulating part S1 First surface S2 Second surface WA, WB Middle area

Claims (16)

A semiconductor layer having a trench;
A gate electrode disposed in the trench and facing an inner side surface of the trench;
A field plate electrode located on the side opposite to the opening of the trench than the gate electrode,
A semiconductor device in which at least a part of the surface of the field plate electrode on the opening side of the trench does not overlap with the surface of the gate electrode on the side opposite to the opening when viewed in the depth direction of the trench.   2. The semiconductor device according to claim 1, wherein the gate electrode is arranged except for a central portion in a width direction of the trench. 3.   The gate electrode includes a first gate electrode and a second gate electrode facing one inner surface and the other inner surface in the width direction of the trench, respectively, and the first gate electrode and the second gate electrode are connected to each other. The semiconductor device according to claim 1, wherein the semiconductor device is separated. A first conductive type semiconductor layer further on the side opposite to the opening than the field plate electrode;
4. The semiconductor device according to claim 1, wherein a semiconductor layer of a second conductivity type different from the first conductivity type is not provided on the opposite side of the opening from the field plate electrode. 5.   The semiconductor device according to claim 4, wherein the first conductivity type is an n-type.   The semiconductor device according to claim 4, wherein the first conductivity type is a p-type.   The semiconductor device according to claim 1, wherein the semiconductor device is a MOSFET. A semiconductor layer having a trench;
A gate electrode disposed in the trench and facing an inner side surface of the trench;
A field plate electrode located on the side opposite to the opening of the trench than the gate electrode,
An electric device comprising a semiconductor device in which at least a part of a surface of the field plate electrode on the opening side of the trench does not overlap with a surface of the gate electrode on the side opposite to the opening when viewed in a depth direction of the trench. Forming a trench extending from the first surface toward the second surface in a first semiconductor layer having a first surface and a second surface opposite to the first surface;
Forming a field plate electrode in the trench;
Forming an insulating film on the opening side of the trench relative to the field plate electrode in the trench;
Forming a gate electrode in the trench where the insulating film is formed;
Including
The step of forming the gate electrode includes the step of forming at least a part of the surface of the field plate electrode on the opening side as viewed from the field plate electrode on the opening side and in the depth direction of the trench. A method for manufacturing a semiconductor device, comprising: forming the gate electrode at a position that does not overlap with the second surface of the electrode. Forming a field insulating film on the inner surface of the trench before forming the field plate electrode;
After forming the field plate electrode and before forming the gate electrode, removing at least a portion of the field insulating film from the inner side surface of the trench;
Further comprising
10. The method of manufacturing a semiconductor device according to claim 9, wherein the step of forming the gate electrode is a step of forming the gate electrode at a location including a portion where the field insulating film has been removed. The insulating film includes a first insulating film formed on the opening side of the field plate electrode and on the second surface side of the gate electrode,
The method of manufacturing a semiconductor device according to claim 9, wherein the step of forming the insulating film includes a step of forming the first insulating film by a thermal oxidation method. The insulating film includes a first insulating film formed on the opening side of the field plate electrode and on the second surface side of the gate electrode,
The method of manufacturing a semiconductor device according to claim 9, wherein the step of forming the insulating film includes a step of forming the first insulating film by a CVD method. The insulating film includes a second insulating film interposed between the inner surface of the trench and the gate electrode,
The method for manufacturing a semiconductor device according to claim 9, wherein the step of forming the insulating film includes a step of forming the second insulating film by a thermal oxidation method. The insulating film includes a second insulating film interposed between the inner surface of the trench and the gate electrode,
The method of manufacturing a semiconductor device according to claim 9, wherein the step of forming the insulating film includes a step of forming the second insulating film by a CVD method.   Forming a second semiconductor layer and a third semiconductor layer having different conductivity types or impurity concentrations from the first semiconductor layer by performing ion implantation and thermal diffusion on the first semiconductor layer facing the outer surface of the trench. The method of manufacturing a semiconductor device according to claim 9, further comprising:   16. The semiconductor device according to claim 15, wherein forming the second semiconductor layer and the third semiconductor layer includes forming an oxide film on the first surface of the first semiconductor layer before the ion implantation. Production method.

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