JP2001345377A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can prevent fluctuations of the potential of adjacent circuit regions caused by a surge voltage and can hold normal operation of an inner circuit, etc., with an improved reliability. SOLUTION: Regions 7 and 9 having an MOSFET 8 and an LDMOS 10 formed therein are provided in an n-type silicon layer 2 of an SOI substrate 1. A shield region 11 including a drain 10A of the LDMOS 10 and p-type regions 12 and 13 is provided in the region 9, the p-type region 13 of the shield region 11 is connected to a grounding terminal V0, and an output terminal is connected to the drain 10A of the LDMOS 10. As a result, a high-pass filter is formed between the output and a p-type supporting substrate 3 to enable removal of a surge voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOI (Silicon on Insul) having a semiconductor layer dielectrically separated by an insulating film on a main surface (front surface) of a semiconductor supporting substrate.
a) a semiconductor device using a substrate.

[0002]

2. Description of the Related Art Generally, as a semiconductor device, for example, an n-type silicon substrate serving as a semiconductor layer and a p-type silicon substrate serving as a semiconductor support substrate are used.
There is known an SOI substrate in which a silicon substrate is bonded to a silicon substrate via an insulating film such as a silicon oxide film (for example, Japanese Patent Application Laid-Open No. 9-266310).

In such a conventional semiconductor device, an n-type silicon substrate forms an n-type silicon layer, a p-type silicon substrate forms a p-type support substrate, and an n-type silicon substrate on the front side. A frame-shaped trench-shaped insulating region is provided in the silicon layer, and the n-type silicon layer is dielectrically separated into a plurality of regions for forming a circuit or the like by the trench-shaped insulating region. Each region is connected to a power supply terminal or a ground terminal, is held at a constant potential, and is connected to an input terminal and an output terminal.
terrestrial diffused MOS), bipolar transistor, IGBT (insulated gate)
An input circuit and an output circuit including e bipolar transistors are formed, or various operations are performed.
MOS transistors that perform signal processing and the like (hereinafter referred to as MOSF
ET) is formed.

[0004]

In the semiconductor device according to the prior art described above, an input circuit and an output circuit for inputting and outputting a load driving current and the like are formed in one of a plurality of regions. A relatively large voltage of several tens of volts to several hundred volts is applied to the circuit and the output circuit as an input signal and an output signal. On the other hand, an internal circuit for performing signal processing or the like is formed in another area, and a relatively small voltage of about several volts is applied to the internal circuit as a signal for calculation. These regions are provided on one p-type support substrate with the insulating film interposed therebetween.

However, since the insulating film for dielectrically separating each region from the p-type support substrate functions as a capacitor, when a surge voltage of several tens to several hundreds of volts, which changes rapidly with time, is applied to an input circuit or the like. In some cases, a surge voltage acts on a p-type support substrate via an insulating film serving as a capacitor, and the potential of the p-type support substrate fluctuates. The fluctuation in the potential of the p-type support substrate acts on the region where the internal circuit is provided through the insulating film.

For this reason, when a surge voltage is applied to an input circuit or the like, a potential change of about several volts occurs in another area provided on the same p-type support substrate as the area of the input circuit or the like.
In particular, when the internal circuit forms an analog circuit, there is a problem that even if the potential fluctuation in the region where the internal circuit is formed is 1 V or less, the circuit operation is hindered.

In a conventional semiconductor device, a potential fixing region having a high impurity concentration is provided between an LDMOS or the like to which a surge voltage is applied and an insulating film or a trench type insulating region, and the potential of the potential fixing region is reduced. By maintaining the voltage at the ground potential or the power supply voltage, the surge voltage is prevented from acting on other areas.

However, in the conventional semiconductor device,
Since n-type wells, p-type wells, and the like are provided in multiple layers between the drain of the LDMOS to which the surge voltage is applied and the potential fixing region, a depletion layer is formed between these, and A capacitor is formed by the depletion layer. At this time, since the n-type well, the p-type well, and the like have a low impurity concentration, the width of the depletion layer is wide and the capacitance of the capacitor is relatively small. Therefore, the drain and p
Since the impedance between the silicon layer and the silicon layer becomes larger than that of an external parasitic capacitor, in the case of a surge voltage having a sharp time change, a surge voltage acts on the p-type support substrate through the parasitic capacitor, Potential fluctuations in the p-type support substrate and other regions cannot be sufficiently suppressed.

Furthermore, since an n-type well, a p-type well and the like are provided in a multi-layered manner between the drain and the potential fixing region, a parasitic bipolar transistor is formed between them, and a snapback phenomenon (switch Back phenomenon)
Tends to occur. For this reason, there is also a problem that the parasitic bipolar transistor operates due to the surge voltage, and an excessive current flows between the drain and the potential fixing region, which may damage the device.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art. It is an object of the present invention to prevent a potential of an area of an internal circuit from fluctuating due to a surge voltage and to maintain a normal operation of the internal circuit. An object of the present invention is to provide a semiconductor device capable of improving reliability.

[0011]

According to a first aspect of the present invention, there is provided an SOI substrate having a semiconductor layer which is dielectrically separated by an insulating film on a main surface of a semiconductor supporting substrate; In a semiconductor device having a trench-type insulating region provided for dielectrically separating the semiconductor layer into a plurality of regions, the insulating film is formed on a bottom surface of the semiconductor layer inside at least one of the plurality of regions. A first first conductivity type high concentration semiconductor buried region provided in contact with the first first conductivity type high concentration semiconductor buried region provided on the semiconductor layer main surface; Forming a shield region comprising a conductive type high-concentration semiconductor diffusion region and a first second conductive type high-concentration semiconductor diffusion region; and connecting the second first conductivity type high-concentration semiconductor diffusion region to a first constant voltage terminal. And the first second conductivity type. The concentration semiconductor diffusion region second constant voltage terminal is characterized in that the configuration of connecting the input terminal to one of the output terminals.

With this configuration, the first first conductivity type high concentration semiconductor buried region is connected to the first constant voltage terminal through the second first conductivity type high concentration semiconductor diffusion region.
The first second-conductivity-type high-concentration semiconductor diffusion region is connected to a second constant-voltage terminal or the like, and between the first-conductivity-type high-concentration semiconductor buried region and the second-conductivity-type high-concentration semiconductor diffusion region. Diodes and capacitors can be formed. Therefore, when the second conductivity type high-concentration semiconductor diffusion region is the input side and the semiconductor support substrate is the output side, the first conductivity type high-concentration semiconductor buried region is provided between the input side and the output side. A high-pass filter can be constituted by a diode or the like between the second conductive type high-concentration semiconductor diffusion region and the resistance of the first conductive type high-concentration semiconductor buried region connected to the output side of the diode or the like. it can. As a result, when a surge voltage is applied through the second conductivity type high concentration semiconductor diffusion region,
The high-pass filter can prevent the surge voltage from being transmitted to the semiconductor supporting substrate.

On the other hand, the semiconductor support substrate is used as an input side, and the second
When the conductive type high concentration semiconductor diffusion region is the output side,
A high-pass filter can be formed between the input side and the output side by a capacitor made of an insulating film and a resistor such as a first conductivity type high concentration semiconductor buried region connected to the output side of the capacitor. As a result, when the potential of the semiconductor support substrate fluctuates due to a surge voltage or the like, the high-pass filter can prevent the surge voltage from being transmitted to the region.

According to a second aspect of the present invention, a MOSFET or a bipolar transistor provided in a semiconductor layer comprises:
Connected to an input terminal or an output terminal;
The second conductivity type high concentration semiconductor diffusion region is
Or the collector of the bipolar transistor, or the drain of the MOSFET or the collector of the bipolar transistor.

In this case, when the high-concentration semiconductor diffusion region of the first second conductivity type is the input side and the semiconductor support substrate is the output side, the first conductivity type is provided between the input side and the output side. A diode and a capacitor between the high-concentration semiconductor buried region and the second-conductivity-type high-concentration semiconductor diffusion region, and a resistance of the first-conductivity-type high-concentration semiconductor buried region connected to the output side of the diode and the like. A high-pass filter can be configured. For this reason, when a surge voltage is applied to an input terminal or the like, the surge voltage can be prevented from being transmitted to the semiconductor support substrate by the high-pass filter.

According to a third aspect of the present invention, the MOSFET or the bipolar transistor formed in the semiconductor layer inside the region forms an internal circuit, and the first second conductivity type high-concentration semiconductor diffusion region is formed in the semiconductor layer. 2 is connected to the constant voltage terminal.

Thus, when the semiconductor supporting substrate is the input side and the second conductivity type high-concentration semiconductor diffusion region is the output side, a capacitor made of an insulating film is provided between the input side and the output side. The first connected to the output side of the capacitor
A high-pass filter can be constituted by the resistance of the conductive type high-concentration semiconductor buried region or the like. As a result, when the potential of the semiconductor support substrate fluctuates due to a surge voltage or the like, the high-pass filter can prevent the surge voltage from being transmitted to a region where the internal circuit is provided, and the internal circuit can operate normally.

Further, the invention according to claim 4 is characterized in that the second first conductivity type high concentration semiconductor diffusion region is in contact with the trench type insulating region.

Thus, the second high-concentration semiconductor diffusion region of the first conductivity type is maintained at a constant potential by being connected to the first constant voltage terminal, so that a surge voltage is applied through the trench-type insulating region. Can be prevented, and the potential fluctuation in each region can be suppressed.

According to a fifth aspect of the present invention, the shield region is formed in a region where an active element such as a MOSFET or a bipolar transistor is not formed among the plurality of regions, and the second first conductivity type is formed. A high-concentration semiconductor diffusion region is connected to the first constant-voltage terminal, and the first second-conductivity-type high-concentration semiconductor diffusion region is connected to one of the second constant-voltage terminal, the input terminal, and the output terminal. Configuration.

Thus, even in a region where no active element is formed, a high-pass filter is formed by the capacitor of the insulating film and the resistance of the first conductivity type high concentration semiconductor buried region connected to the output side of the capacitor. Can be configured. For this reason, it is possible to connect in parallel to high-pass filters provided in a plurality of regions, and it is possible to disperse and remove the surge voltage by using these high-pass filters. Can operate normally.

According to a sixth aspect of the present invention, there is provided a semiconductor device having an SOI substrate having a semiconductor layer dielectrically separated by an insulating film on a main surface of the first conductive type semiconductor support substrate. A second high-concentration semiconductor region of the second conductivity type formed on the main surface in contact with the insulating film; and a high-concentration semiconductor region of the second second conductivity type formed by removing the insulating film from the semiconductor layer. Electrode region connected to the third or third
A second conductive type high-concentration semiconductor region, a first conductive type semiconductor support substrate is connected to a first constant voltage terminal, and the electrode region or a third second conductive type is formed. A high-concentration semiconductor region is connected to a second constant-voltage terminal.

With this configuration, a diode and a capacitor can be formed between the first conductive type semiconductor supporting substrate and the second conductive type high-concentration semiconductor region.
For this reason, when the first conductive type semiconductor support substrate is used as the input side and the semiconductor layer is used as the output side, the first conductive type semiconductor support substrate and the second conductive type height are provided between the input side and the output side. A high-pass filter can be formed by a diode and a capacitor between the high-concentration semiconductor region and a resistor connected to the output side of the high-concentration semiconductor region and the like. As a result, when the potential of the semiconductor supporting substrate fluctuates due to a surge voltage or the like, the transmission of the surge voltage to the semiconductor layer can be prevented by the high-pass filter.

According to a seventh aspect of the present invention, the electrode region or the third second conductivity type high-concentration semiconductor region is formed by connecting the semiconductor layer constituting the semiconductor device or the end portion of the first conductivity type semiconductor support substrate. Is formed.

As a result, the electrode regions do not hinder the degree of freedom in layout, and the degree of integration of the semiconductor device is not impaired.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, as a semiconductor device according to an embodiment of the present invention, an LDMOS, a MOSF
An example in which the ET is provided will be described in detail with reference to FIGS. 1 to 12.

First, FIGS. 1 to 4 show a first embodiment of the present invention. In the drawings, reference numeral 1 denotes, for example, an n-type silicon substrate and a p-type silicon substrate bonded together via a silicon oxide film. In the formed SOI substrate, the SOI
The I-substrate 1 has an n-type silicon layer 2 on its front side and back side.
It has a p-type support substrate 3 and an n-type silicon layer 2
An insulating film 4 made of a silicon oxide film
The dielectric material is insulated from the dielectric material.

The n-type silicon layer 2 is formed by adding an impurity such as arsenic to a substrate made of, for example, a single crystal silicon material at a low concentration (for example, about 10 ¹⁴ to 10 ¹⁵ cm ⁻³ ). On the other hand, the p-type support substrate 3 is formed by adding an impurity such as boron to the substrate made of, for example, a single crystal silicon material at a low concentration (for example, about 10 ¹⁴ to 10 ¹⁵ cm ⁻³ ), and for example, a ground terminal. And is kept at the ground potential. On the bottom side of the n-type silicon layer 2, a p-type region 12, which will be described later, is formed.

Reference numeral 5 denotes a trench-type insulating region provided in the n-type silicon layer 2 surrounding the regions 7 and 9 described later. The trench-type insulating region 5 has, for example, a substantially quadrangular frame shape, and is formed by etching or the like. After the n-type silicon layer 2 is removed in a groove shape, a silicon oxide film 6 is formed in the groove. In the case where a depression occurs after the formation of the silicon oxide film 6, the depression may be filled with polycrystalline silicon.

Reference numeral 7 denotes a region for an internal circuit surrounded by the trench type insulating region 5. The region 7 is provided at a position adjacent to a region 9 described later with the trench type insulating region 5 interposed therebetween. It is formed in a substantially quadrangular island shape by the n-type silicon of the concentration. The region 7 is provided with terminal connection portions 7 by diffusing impurities such as arsenic from the surface side.
A, and a bias voltage Vcc of, for example, about several volts is applied to the terminal connection portion 7A. As a result, the region 7 is maintained at the bias voltage Vcc.

Reference numeral 8 denotes a p-channel type MOSFET provided as an internal circuit provided in the region 7.
For example, analog signal processing or the like is performed using a small voltage of about several volts. The MOSFET 8 includes a drain 8A made of a p-type diffusion layer, a source 8B made of a p-type diffusion layer provided near the drain 8A, and a metal thin film provided on the surface side of the drain 8A and the source 8B. And a gate electrode 8C. Also,
For example, a silicon oxide film 8D is provided between the gate electrode 8C and the surface of the region 7.

The source 8B is connected to a bias terminal to which a bias voltage Vcc of, for example, about several volts is applied as a source voltage Vs, and the gate electrode 8C is connected to an input terminal to which a gate voltage Vg is applied. . Thus, the MOSFET 8 controls the drain voltage Vd of the drain 8A by the gate voltage Vg and performs signal processing and the like.

Reference numeral 9 denotes a region for, for example, an output circuit surrounded by the trench type insulating region 5, and the region 9 is formed in a substantially square island shape with low-concentration n-type silicon. The region 9 is provided with a p-type well 9A by diffusing impurities such as boron from the surface side, and the p-type well 9A is maintained at, for example, the ground potential (0 V) together with a source 10B described later.

Reference numeral 10 denotes an LDMOS as an output circuit provided in the region 9.
It controls a large voltage of about to several hundred volts.
The LDMOS 10 has a drain 10A made of an n-type diffusion layer provided outside the p-type well 9A.
And a source 10B formed of an n-type diffusion layer provided in the p-type well 9A, and a gate electrode 10C formed of a metal thin film provided between the drain 10A and the source 10B. Further, for example, a silicon oxide film 10D is provided between the gate electrode 10C and the surface of the p-type well 9A.

Here, the drain 10A is provided, for example, on the center side of the region 9 as a position different from the p-type region 13 to be described later, extends in the thickness direction of the n-type silicon layer 2, and has a tip which will be described later. In contact with the p-type region 12.
The drain 10A is formed by diffusing impurities such as arsenic into the surface (main surface) of the region 9 at a high concentration (for example, about 10 ²⁰ cm ^-3 ).

The drain 10A is connected to an output terminal for outputting a drain voltage VD of several tens of volts to several hundred volts, and the source 10B is connected to a ground terminal having a source voltage VS such as a ground potential. I have. The gate electrode 10C is connected to an input terminal to which a gate voltage VG is applied, and the LDMOS 10 is connected to the gate voltage VG.
This controls the drain voltage VD to increase or decrease, for example, a load drive current.

Reference numeral 11 denotes a shield region provided in the region 9. The shield region 11 includes the region 9 and the p-type support substrate 3.
LDM is used to electrically shield the area 7 and the like.
The drain 10A of the OS 10, p-type regions 12, 13 described later
It is constituted by.

Are p-type regions buried on the bottom side of the n-type silicon layer 2, and the p-type region 12 is located between the n-type silicon layer 2 and the insulating film 4 to be insulated. It is provided in contact with the film 4 and covers the entire bottom surface of each of the regions 7 and 9. And the p-type region 12 is the n-type silicon layer 2.
Before bonding the n-type silicon layer 2 to the p-type support substrate 3, the bottom surface of the n-type silicon layer 2 is highly doped with impurities such as boron (for example, 10 ²⁰ c).
m ^-3 ).

Reference numeral 13 denotes a p-type region provided on the surface of the region 9. The p-type region 13 is formed in a substantially rectangular frame shape surrounding the region 9, and comes into contact with the trench groove type insulating region 5 to form the trench. The groove-shaped insulating region 5 is covered. Also, the p-type region 1
Reference numeral 3 extends in the thickness direction of the n-type silicon layer 2, and its tip is in contact with the p-type region 12. The p-type region 13 is formed by diffusing impurities such as boron into the surface of the region 9 made of n-type silicon at a high concentration (for example, about 10 ²⁰ cm ⁻³ ), and becomes a constant potential, for example, a ground potential. Connected to the ground terminal V0. Thereby, the p-type region 13 holds the p-type region 12 at the ground potential.

The semiconductor device according to the present embodiment has the structure as described above, and the MOSFE formed in region 7
T8 controls the drain voltage Vd of the drain 8A by the gate voltage Vg to perform signal processing and the like. On the other hand, area 9
The LDMOS 10 controls the drain voltage VD of the drain 10A by the gate voltage VG to increase or decrease, for example, a load driving current.

However, the drain 10A of the LDMOS 10
, A surge voltage of, for example, several tens of volts to several hundred volts may be applied from an external load or the like. Also, LDMO
A surge voltage may be output from the drain 10A with the driving of S10. Such a surge voltage acts on the p-type support substrate 3 from the region 9 through the insulating film 4 and tends to cause a potential change in other regions 7 and the like via the p-type support substrate 3.

In the present embodiment, however, LD
A shield region 11 comprising a drain 10A of the MOS 10 and p-type regions 12 and 13 is provided.
Since the p-type region 12 is connected to the ground terminal V0 through the p-type region 13 and the output terminal is connected to the drain 10A, a high-pass filter can be formed between the output terminal and the p-type support substrate 3.

That is, the output terminal of the drain 10A and the MOS
An equivalent circuit between the region 7 where the FET 8 is formed is as shown in FIGS. 3 and 4, and a high-pass filter is formed. The reason for such an equivalent circuit will be described below.

First, since the drain 10A is formed of an n-type diffusion layer, as shown in FIG.
A diode 14 is formed between A and the p-type region 12. Since a depletion layer is formed between the drain 10A and the p-type region 12, the capacitor 1
5 is connected in parallel with the diode 14. One end of the diode 14 and the capacitor 15 is connected to an output terminal by a drain 10A made of an n-type diffusion layer. Therefore, a resistor 16 in the drain 10A is provided between the diode 14 and the output terminal. It will be in the connected state.

On the other hand, the other end of the diode 14 or the like is in contact with the p-type region 12, and is therefore connected to the ground terminal V0 through the resistor 17 in the p-type regions 12, 13. An insulating film 4 is provided between the p-type region 12 and the p-type support substrate 3.
Is provided, the other end of the diode 14 or the like is
P-type support substrate 3 via capacitor 18 made of insulating film 4
Connected. Further, since the insulating film 4 is also provided between the p-type support substrate 3 and the region 7, the p-type support substrate 3 is connected to the region 7 via the capacitor 19.

As a result, when the p-type support substrate 3 and the region 7 are viewed from the output terminal side to which the drain voltage VD is applied, a high-pass filter including the capacitor 15 and the resistor 17 is formed therebetween. For this reason, the surge voltage applied from the output terminal can be removed by this high-pass filter, and the potential fluctuation of the p-type support substrate 3 and the region 7 can be suppressed.

At this time, the output terminal of the drain 10A and p
The connection with the shaped support substrate 3 is made by an external parasitic capacitor 20 as shown by a two-dot chain line in FIG. However, in the present embodiment, the impedance of the high-pass filter including the capacitor 15 and the resistor 17 is smaller than that of the parasitic capacitor 20 for the following reason.

That is, the width of the depletion layer formed between the drain 10A and the p-type region 12 decreases as the concentration of the impurity added to the drain 10A and the p-type region 12 increases.
The capacity of the capacitor 15 due to the depletion layer increases as the width of the depletion layer decreases, and the drain 10A and the p-type region 12 are heavily doped with impurities, so that the capacitance of the capacitor 15 increases. Also, the capacitor 15
Increases as the contact area between the drain 10A and the p-type region 12 increases. For this reason, the capacity of the capacitor 15 is set to a large value as needed.

On the other hand, the resistance 16 of the drain 10A and the resistance 17 of the p-type regions 12 and 13 are different from each other because the drain 10A and the p-type regions 12 and 13 are heavily doped with impurities.
The resistance value is small.

As a result, the current due to the surge voltage does not pass through the parasitic capacitor 20 but passes through the high-pass filter including the capacitor 15 and the resistor 17. This allows
Since the high-pass filter can remove a signal having a cut-off frequency f or less, a sharp surge voltage can be reliably removed by setting the cut-off frequency f high, and the potential fluctuation of the p-type support substrate 3 is suppressed. can do.

[0051]

(Equation 1) Where C: capacitance of capacitor 15 R: resistance value of resistor 17

When the capacitance C of the capacitor 15 is increased, the cutoff frequency f of the high-pass filter decreases. However, in this embodiment, the resistance value R of the resistor 17 is set to a sufficiently small value. , Condenser 15
The effect of the decrease in the cutoff frequency f due to the increase in the capacitance C of the first embodiment is substantially eliminated.

As described above, when a positive surge voltage with a steep time change is applied to the output terminal, the surge voltage is bypassed as a charging current for the capacitor 15. When the surge voltage becomes higher, the diode 14 is broken down and bypassed.

On the other hand, when a negative surge voltage with a steep time change is applied to the output terminal, the surge voltage is bypassed as a forward bias current of the diode 14 and as a charging current of the capacitor 15.

Therefore, even when a positive or negative surge voltage is applied to the output terminal, a high-pass filter including the capacitor 15 and the resistor 17 or the diode 14
As a result, a surge voltage can be removed, and a fluctuation in the potential of the p-type region 12 can be suppressed.
Can be prevented, and the MOSFET 8 formed in the region 7 can operate normally.

Thus, in this embodiment, the drain 9A of the LDMOS 10 and the p-type regions 12 and 13
Since the shield region 11 made of
A high-pass filter having a high cutoff frequency f can be formed between A and the p-type support substrate 3. For this reason,
Even when a time-varying surge voltage is applied to the drain 10A, the surge voltage can be removed by this high-pass filter, and the potential fluctuation of the p-type support substrate 3 can be suppressed. As a result, the potential change of the region 7 can be prevented, so that the MOSFET 8 can be operated normally and the reliability can be improved.

Since the drain 10A and the p-type region 12 are both formed by adding impurities at a high concentration, the capacitance C of the capacitor 15 formed between the drain 10A and the p-type region 12 is increased. The resistance values of the resistors 16 and 17 can be reduced. Therefore, the parasitic capacitor 20
Since the impedance of the high-pass filter including the capacitor 15 and the like can be made smaller as compared with the above, the current caused by the surge voltage can flow through the high-pass filter. As a result, the fluctuation of the potential of the p-type support substrate 3 due to the parasitic capacitor 20 can be suppressed.

Further, since the impedance of the high-pass filter can be reduced, the surge voltage itself can be reduced, and the fluctuation in the potential of the p-type support substrate 3 and the region 7 can be further reduced.

Further, since both the p-type regions 12 and 13 are formed by adding impurities at a high concentration, the resistance value R of the resistor 17 can be reduced by these, and the cutoff frequency f of the high-pass filter can be increased. it can. This makes it possible to reliably remove even a surge voltage having a sharp change with time, prevent a potential change in the region 7, and allow the MOSFET 8 to operate normally.

Further, since the drain 10A is configured to make surface contact (planar junction) with the p-type region 12, when the diode 14 between the drain 10A and the p-type region 12 breaks down due to an excessive positive surge voltage. Even in this case, the excessive current due to the breakdown does not concentrate on a part of the pn junction of the diode 14 but flows over the entire surface contact portion. Therefore, the diode 14
Can be prevented, and reliability and durability can be improved.

Further, in this embodiment, no parasitic bipolar transistor is formed in region 9. Therefore, the snapback phenomenon due to the surge voltage does not occur, and the LDMOS 10 and the like are not damaged, so that the reliability of the semiconductor device can be improved.

Since the p-type region 13 is configured to be in contact with the trench type insulating region 5, a p-type region connected to the ground terminal V0 and held at the ground potential is provided between the LDMOS 10 and the trench type insulating region 5. An area 13 can be provided. For this reason, it is possible to prevent a surge voltage applied to the drain 10A of the LDMOS 10 from acting on the region 7 through the trench-type insulating region 5, so that the region 7 where the MOSFET 8 as the internal circuit is formed is
The semiconductor device can be provided adjacent to the region 9 where the OS 10 is provided, so that the size of the semiconductor device can be reduced.

In the first embodiment, the region 9
Is provided with an LDMOS 10 as an output circuit. However, as in the modification of the first embodiment shown in FIG.
An emitter 21 composed of an n-type diffusion layer instead of the DMOS 10
A bipolar transistor 21 may be provided, which includes A, a base 21B made of a p-type well, and a collector 21C made of an n-type diffusion layer provided outside the p-type well.

In this case, the emitter 21A is connected to a ground terminal having an emitter voltage VE such as a ground potential, and the collector 21C is connected to an output terminal from which a collector voltage VC of several tens of volts to several hundred volts is output. In addition, an input terminal to which a base voltage VB is applied is connected to the base 21B.

The collector 21 to which the output terminal is connected
C is formed by diffusing impurities at a high concentration, and extends in the thickness direction of n-type silicon layer 2 to form p-type region 12.
Is in contact with Thereby, the p-type region 1 is included in the region 9.
2, 13 and shield region 11 'composed of collector 21C
Can be formed, and the collector 2 can be formed by the shield region 11 '.
The surge voltage applied to 1C is applied to the p-type support substrate 3, the region 7
Can be prevented.

FIGS. 6 and 7 show a second embodiment of the present invention. The feature of this embodiment is that a high concentration p-type silicon layer and a p-type diffusion layer are formed in a region where an internal circuit is provided. Layer, n
In that a shield region made of a shaped diffusion layer is formed.
In the present embodiment, the same components as those in the above-described first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

Reference numeral 31 denotes a region for an internal circuit provided on the surface side of the insulating film 4. The region 31 is formed by surrounding a part of the n-type silicon layer 2 by using the trench type insulating region 5. And made of low-concentration n-type silicon. The region 31 is provided with an n-type diffusion layer 36 to which a later-described bias voltage Vcc of about several volts is applied, and the region 31 is held at a bias voltage Vcc of about several volts through the n-type diffusion layer 36, for example. I have.

Reference numeral 32 denotes a p-channel type MOSFET as an internal circuit provided in the region 31.
Numeral 2 performs analog signal processing and the like using a small voltage of, for example, several volts. And MOSFET 32
Is a drain 32A made of a p-type diffusion layer and a source 3 made of a p-type diffusion layer provided near the drain 32A.
2B, and a gate electrode 32C made of a metal thin film provided on the surface side of the drain 32A and the source 32B. Further, for example, a silicon oxide film 32D is provided between the gate electrode 32C and the surface of the region 31.

The source voltage Vs is applied to the source 32B.
For example, a bias terminal to which a bias voltage Vcc of about several volts is applied is connected, and an input terminal to which a gate voltage Vg is applied is connected to the gate electrode 32C. Thus, the MOSFET 32 controls the drain voltage Vd of the drain 32A by the gate voltage Vg, and performs signal processing and the like.

Reference numeral 33 denotes a shield region provided in the region 31. The shield region 33 is formed of the region 31 and the p-type support substrate 3.
Are electrically shielded from each other. The shield region 33 includes p-type regions 34 and 35 and an n-type region 3 described later.
6.

Reference numeral 34 denotes p embedded on the bottom side of the region 31.
The p-type region 34 is located between the region 31 and the insulating film 4 and is provided in contact with the insulating film 4.
Is covered over the entire surface. And the p-type region 3
4 is formed by diffusing impurities such as boron into the bottom surface of the n-type silicon layer 2 at a high concentration (for example, about 10 ²⁰ cm ⁻³ ), similarly to the p-type region 12.

Reference numeral 35 denotes a p-type region provided on the surface of the region 31. The p-type region 35 is formed in a substantially rectangular frame shape surrounding the region 31, and comes into contact with the trench groove type insulating region 5 to form the trench. The groove-shaped insulating region 5 is covered. The p-type region 35 extends in the thickness direction of the n-type silicon layer 2, and the tip thereof contacts the p-type region 34. And
The p-type region 35 has a high concentration of an impurity such as boron (for example, about 10 ²⁰ cm ⁻³ ) on the surface of the region 31 made of n-type silicon.
And is connected to a ground terminal V0 at a constant potential, for example, a ground potential.

Reference numeral 36 denotes an n-type region provided at a position different from the p-type region 35, for example, on the center side of the region 31.
The n-type region 36 extends in the thickness direction of the n-type silicon layer 2, and its tip is in contact with the p-type region 34.
The n-type region 36 is formed by diffusing an impurity such as arsenic into the surface of the region 31 at a high concentration (for example, about 10 ²⁰ cm ⁻³ ).

The n-type region 36 is connected to a bias terminal to which a bias voltage Vcc of about several volts is applied. Thereby, the n-type region 36 holds the region 31 at the bias voltage Vcc.

The semiconductor device according to the present embodiment has the structure as described above, and the MOSF formed in region 31
There is no particular difference from the MOSFET 8 according to the first embodiment in that the ET 32 controls the drain voltage Vd of the drain 32A by the gate voltage Vg and performs signal processing and the like.

In the present embodiment, however, the shield region 33 including the p-type regions 34 and 35 and the n-type region 36 is formed in the region 31 where the MOSFET 32 as an internal circuit is provided. , The surge voltage can be prevented from acting on the region 31.

That is, as shown in FIGS. 6 and 7, between the p-type support substrate 3 and the bias terminal of the n-type region 36,
An equivalent circuit composed of a capacitor 37 by the insulating film 4, a resistor 38 by the p-type regions 34 and 35, a diode 39 between the p-type region 34 and the n-type region 36, a capacitor 40, and a resistor 41 by the n-type region 36. It will be in the connected state.

As a result, the region 31 in the n-type silicon layer 2
When a surge voltage is applied to an output transistor or the like formed in a region other than the above, and the potential of the p-type support substrate 3 fluctuates due to the surge voltage, when the n-type region 36 side is viewed from the p-type support substrate 3 side Similarly to the first embodiment, a high-pass filter including a capacitor 37, a resistor 38, and the like is formed therebetween, and the impedance of the high-pass filter is between the p-type support substrate 3 and the bias terminal. It can be made sufficiently smaller than the formed parasitic capacitor 42. Therefore, the p-type support substrate 3
The surge voltage that acts on the region 31 through the high-pass filter can be removed by the high-pass filter, and the potential fluctuation in the region 31 can be suppressed.

In addition, a parallel circuit of a diode 39 and a capacitor 40 and a series circuit of a resistor 41 form a p-type region 34.
And the bias terminal, these diodes 3
9, the impedance of the capacitor 40 and the resistance 41 is the first
Is sufficiently small as in the embodiment of FIG.
Can be suppressed.

Thus, in the present embodiment, the p-type regions 34 and 35 and the n-type region 3
6 is provided, the p-type region 35 is connected to the ground terminal V0, and the n-type region 36 is connected to the bias terminal. Therefore, a high-pass filter is provided between the p-type support substrate 3 and the n-type region 36. , And can be connected with a sufficiently small impedance in an AC manner. Therefore, even when a surge voltage having a sharp time change is applied to a region different from the region 31 and the potential of the p-type support substrate 3 fluctuates, the surge voltage is removed by the high-pass filter, and the region 31 is removed. Can be suppressed, the MOSFET 32 can operate normally, and the reliability can be improved.

Since the p-type region 35 is configured to cover the trench-type insulating region 5, the p-type region 35 connected between the MOSFET 32 and the trench-type insulating region 5 is connected to the ground terminal V0 and held at the ground potential. An area 35 can be provided. Therefore, it is possible to prevent a surge voltage from acting on the region 31 through the trench-type insulating region 5, prevent a potential change in the region 31, and allow the MOSFET 32 to operate normally.

In the second embodiment, the region 9
Is provided with a MOSFET 32 as an internal circuit, but as in a first modification shown in FIG.
Instead of 32, a bipolar transistor 51 including an emitter 51A formed of an n-type diffusion layer, a base 51B formed of a p-type well, and a collector 51C formed of an n-type diffusion layer provided outside the p-type well may be provided. .

In this case, the emitter 51A is connected to a ground terminal having an emitter voltage VE such as a ground potential, and the collector 51C is connected to a bias terminal to which a bias voltage Vcc is applied as a collector voltage VC of about several volts. At the same time, an input terminal to which a base voltage VB is applied is connected to the base 51B.

In the second embodiment, the p-type region 35 is provided so as to be in contact with the trench-type insulating region 5. However, as in the second modification shown in FIGS. A p-type region 35 ′ may be provided at a position separated from the trench-type insulating region 5, and the p-type region 35 ′ need not necessarily surround the MOSFET 32. Even in this case, the shield region 33 'is formed by the p-type regions 34 and 35' and the n-type region 36, and the surge voltage acting through the p-type support substrate 3 can be removed by the shield region 33 '. . Further, since the area of the p-type region 35 'can be reduced, the size of the semiconductor device can be reduced.

FIG. 11 shows a third embodiment of the present invention. This embodiment is characterized in that a shield region comprising a p-type region and an n-type region is formed in a region where an internal circuit is provided. In addition, another shield region including a p-type region and an n-type region is formed in a vacant region where no internal circuit or the like is provided. In the present embodiment, the same components as those in the first embodiment are given the same reference numerals,
The description is omitted.

Reference numeral 61 denotes a region for an internal circuit provided on the surface side of the insulating film 4. The region 61 is formed by surrounding a part of the n-type silicon layer 2 by using the trench type insulating region 5. And made of low-concentration n-type silicon.

Reference numeral 62 denotes a p-channel type MOSFET provided as an internal circuit provided in the region 61.
Numeral 2 performs analog signal processing and the like using a small voltage of, for example, several volts. And the MOSFET 62
Are a drain 62A, a source 62B, and a gate electrode 62C.
For example, a silicon oxide film 62D is provided between the gate electrode 62C and the surface of the region 61.

Reference numeral 63 denotes a first shield region provided in the region 61. The shield region 63 is a p-type region 6 described later.
4, 65, and an n-type region 66.

Are p-type regions buried on the bottom side of the n-type silicon layer 2, and the p-type region 64 is located between the n-type silicon layer 2 and the insulating film 4 to be insulated. It is provided in contact with the film 4 and covers the entire bottom surface of the region 61 and the like. The p-type region 64 is formed by diffusing impurities such as boron at a high concentration on the bottom surface of the n-type silicon layer 2 as in the p-type region 12.

Reference numeral 65 denotes a p-type region provided on the surface of the region 61. The p-type region 65 is formed in a substantially rectangular frame shape surrounding the region 61, and comes into contact with the trench groove type insulating region 5 to form the trench. The groove-shaped insulating region 5 is covered. The p-type region 65 extends in the thickness direction of the n-type silicon layer 2, and the tip thereof contacts the p-type region 64. And
The p-type region 65 has a high concentration of impurities such as boron (for example, about 10 ²⁰ cm ⁻³ ) on the surface of the region 61 made of n-type silicon.
And is connected to the ground terminal V0.

Reference numeral 66 denotes an n-type provided at the center of the region 61
In the region, the n-type region 66 is defined by the thickness of the n-type silicon layer 2.
And its tip contacts the p-type region 64. Ma
The n-type region 66 has an impurity such as arsenic on the surface of the region 61.
At a high concentration (for example, 10²⁰cm ^-3Spread)
Therefore, it is formed. The n-type region 66 has a voltage of several volts.
The bias terminal to which the bias voltage Vcc of about
Has been continued.

Reference numeral 67 denotes a region provided adjacent to the region 61. The region 67 is surrounded by the trench type insulating region 5 like the region 61, and is formed in an island shape. Then, the region 67 is formed as an empty region, and the MOSFE
No active elements such as T and bipolar transistors are formed. The region 67 does not necessarily need to be provided adjacent to the region 61, and may be provided at any position on the p-type support substrate 3.

Reference numeral 68 denotes a second shield region provided in the region 67. The shield region 68 is formed of the p-type regions 64, 6
9. It is constituted by an n-type region 70.

Reference numeral 69 denotes a p-type region provided on the surface of the region 67. The p-type region 69 has a high impurity concentration set similarly to the p-type region 65. The silicon layer 2 extends in the thickness direction, and the tip thereof is in contact with the p-type region 64. The p-type region 69 is connected to the ground terminal V0.

Reference numeral 70 denotes an n-type region provided on the center side of the region 67. The n-type region 70 is set to have a high impurity concentration similarly to the n-type region 66, and extends in the thickness direction of the n-type silicon layer 2. And its tip is in contact with the p-type region 64. Also,
The n-type region 70 is connected to a bias terminal to which a bias voltage Vcc of about several volts is applied.

Thus, in the present embodiment, the same operation and effect as in the second embodiment can be obtained. However, in the present embodiment, the regions 61 and 67 each include the p-type regions 64 and 64, the p-type regions 65 and 69, and the n-type regions 66 and 7.
Since the shield regions 63 and 68 made of 0 are formed, the p-type regions 64 and 65,
A high-pass filter can be formed by the n-type region 66, and a high-pass filter by the p-type regions 64 and 69 and the n-type region 70 can be formed in the region 67. Therefore, the high-pass filters in the regions 61 and 67 can be connected in parallel, so that the surge voltage acting through the p-type support substrate 3 can be dispersed and removed by the high-pass filters in the regions 61 and 67. 61 can be further reduced and suppressed. Therefore, MO
Since the SFET 62 can operate more stably, stability and reliability can be improved.

When the n-type region 70 is connected not to the bias terminal but to the input terminal or the output terminal, the shield region 68 is connected in parallel with the shield region 11 in the first embodiment. The surge voltage applied to the input terminal or the output terminal can be further removed.

Next, FIG. 12 shows a fourth embodiment of the present invention. The feature of this embodiment is that an n-type region is formed on a p-type support substrate and the n-type region is held at a bias voltage. It is in. In the present embodiment, the same components as those in the above-described first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

Reference numeral 71 denotes a region for an internal circuit provided on the surface side of the insulating film 4. The region 71 is formed by surrounding a part of the n-type silicon layer 2 by using a trench type insulating region 5. And made of low-concentration n-type silicon. The region 71 is provided with a terminal connection portion 71A.
, A bias voltage is applied.

Reference numeral 72 denotes a p-channel MOSFET as an internal circuit provided in the region 71.
2 is a drain 72A, a source 72B, a gate electrode 72
For example, a silicon oxide film 72D is provided between the gate electrode 72C and the surface of the region 71.

Reference numeral 73 denotes a shield region provided on the front surface side of the p-type support substrate 3. The shield region 73 includes an n-type region 74 and an electrode region 75 described later.

Reference numeral 74 denotes an n-type region provided between the p-type support substrate 3 and the insulating film 4 so as to be in contact with the insulating film 4. Is covered over the entire surface. And the n-type region 74 is the p-type support substrate 3
High concentration of impurities such as arsenic (for example, 10 ²⁰ cm ⁻³⁾
To the extent).

A ground terminal, for example, is connected to the p-type support substrate 3, and the p-type support substrate 3 is held at a ground potential as a constant potential (low voltage) different from the bias voltage Vcc.

Reference numeral 75 denotes an electrode region made of, for example, a conductive metal material provided at a position different from that of the region 71. The electrode region 75 is provided penetrating the n-type silicon layer 2 and the insulating film 4, and its tip is provided. It is in contact with the n-type region 74. And
The electrode region 75 is connected to, for example, a bias terminal having a bias voltage Vcc, and the n-type region 74 is connected to the bias voltage Vcc.
Holding. Note that the electrode region 75 may be formed of high-concentration n-type silicon.

Thus, the present embodiment can provide the same functions and effects as those of the second embodiment. That is, in the present embodiment, since the shield region 73 including the n-type region 74 and the electrode region 75 is provided on the p-type support substrate 3, a diode is provided in the p-type support substrate 3 near the interface with the n-type region 74. Capacitors can be formed. Therefore, a surge voltage transmitted from the p-type support substrate 3 to the region 71 can be removed by the diode and the like and the resistance in the n-type region 74, and the potential change in the region 71 can be prevented.

In the fourth embodiment, since the shield region 73 is provided in the p-type support substrate 3, it is not necessary to form a shield region in the region 71 as compared with the second embodiment. Therefore, the area corresponding to the shield region can be reduced, and the integration degree of the semiconductor device can be increased.

In the first to third embodiments, the p-type support substrate 3 of the SOI substrate 1 is connected to the ground terminal V0. However, the present invention is not limited to this. May not be connected to any terminal such as a ground terminal and a bias terminal, and may not be kept at a constant potential.

In each of the above embodiments, the n-type silicon layer 2 is provided on the surface side of the SOI substrate 1, and the regions 7, 9, 31, 61, 67, 71 are formed in the n-type silicon layer 2. However, a p-type silicon layer may be provided on the surface side of the SOI substrate 1, and a region may be formed in the p-type silicon layer. Further, although the LDMOS 10 and the bipolar transistor 21 are used as the output circuit, an IGBT or the like may be used. The regions 7, 9, 31, 61, 67, and 71 may be provided with an input circuit connected to an input terminal. In this case, a similar effect can be obtained for a surge voltage applied from the input terminal.

Further, a p-channel type MO is used as an internal circuit.
Although SFETs 8, 32, 62 and 72 are used,
It may be an n-channel type MOSFET, CMOS, bipolar transistor or the like.

Furthermore, in each of the above embodiments, the case where the p-type is used as the first conductivity type and the n-type is used as the second conductivity type has been described as an example, but the present invention is not limited to this, and the present invention is not limited to this. 1
The n-type may be used as the conductivity type and the p-type may be used as the second conductivity type. In this case, the n-type region is connected to a bias terminal (high voltage terminal) as a first constant voltage terminal, and the p-type region in contact with the n-type region is a ground terminal (low voltage terminal) as a second constant voltage terminal. Is to be connected to.

[0111]

As described above in detail, according to the first aspect of the present invention, one region of the semiconductor layer has a first high-concentration semiconductor buried region of the first first conductivity type, and a second high concentration of the first conductivity type. Since the shield region including the high-concentration semiconductor diffusion region and the first second-conductivity-type high-concentration semiconductor diffusion region is formed, the first-conductivity-type high-concentration semiconductor buried region is formed through the first-conductivity-type high-concentration semiconductor diffusion region. A diode and a capacitor can be formed between the first conductivity type high-concentration semiconductor buried region and the second conductivity type high-concentration semiconductor diffusion region by connecting to the constant voltage terminal. For this reason, a high-pass filter can be formed between the region and the semiconductor supporting substrate, so that even when a surge voltage with a sharp time change is applied, the surge voltage is removed by the high-pass filter. be able to. As a result, it is possible to prevent a surge voltage from being transmitted between the region and the semiconductor supporting substrate, so that internal circuits and the like provided in each region can operate normally, and reliability can be improved.

According to the second aspect of the present invention, the MOSFET or the bipolar transistor provided in the semiconductor layer is connected to the input terminal or the output terminal, and the first second conductivity type high concentration semiconductor diffusion region is provided. Is the MOS
Since the drain of the FET or the collector of the bipolar transistor is configured or connected to the drain of the MOSFET or the collector of the bipolar transistor, the first conductivity type high concentration semiconductor buried region and the second conductivity type high concentration semiconductor A diode and a capacitor between the diffusion region and a first diode connected to the output side of the diode and the like;
A high-pass filter can be constituted by the resistance of the conductive type high-concentration semiconductor buried region or the like. For this reason, when a surge voltage is applied to an input terminal or the like, the surge voltage can be prevented from being transmitted to the semiconductor support substrate by the high-pass filter.

On the other hand, according to the third aspect of the present invention, the MOSFET or the bipolar transistor formed in the semiconductor layer inside the region forms an internal circuit, and the first second conductivity type high concentration semiconductor diffusion region is formed. Since it is configured to be connected to the second constant voltage terminal, a capacitor made of an insulating film is provided between the semiconductor supporting substrate and the second conductive type high-concentration semiconductor diffusion region, and a second capacitor connected to the output side of the capacitor. A high-pass filter can be formed by the resistance of the one-conductivity-type high-concentration semiconductor buried region or the like. As a result, when the potential of the semiconductor support substrate fluctuates due to a surge voltage or the like,
This high-pass filter can prevent a surge voltage from being transmitted to a region where the internal circuit is provided, and can normally operate the internal circuit.

According to the fourth aspect of the present invention, since the second first conductivity type high-concentration semiconductor diffusion region is in contact with the trench type insulating region, the second first conductivity type high-concentration semiconductor diffusion region is formed. By connecting the semiconductor diffusion region to the first constant voltage terminal, the semiconductor diffusion region can be maintained at a constant potential, a surge voltage can be prevented from acting through the trench type insulating region, and the potential fluctuation in the region can be suppressed. it can.

Further, according to the fifth aspect of the present invention, the shield region is formed in a region where an active element such as a MOSFET or a bipolar transistor is not formed among a plurality of regions, and the second first region is formed. A conductive type high-concentration semiconductor diffusion region connected to the first constant voltage terminal;
Is connected to any one of the second constant voltage terminal, the input terminal, and the output terminal. Therefore, even in a region where no active element is formed, the capacitor made of an insulating film can be used. In addition, a high-pass filter can be constituted by the first conductive type high-concentration semiconductor buried region and the like connected to the output side of the capacitor. For this reason,
High-pass filters provided in a plurality of regions can be connected in parallel to each other, and surge voltages can be dispersed and removed using these high-pass filters. Can work.

On the other hand, according to the invention of claim 6, the second conductive type high-concentration semiconductor region formed on the main surface of the first conductive type semiconductor support substrate in contact with the insulating film, and the semiconductor layer. An electrode region formed by removing the insulating film and connected to the second second conductivity type high concentration semiconductor region or a third second region;
Forming a shield region comprising a conductive type high-concentration semiconductor region, connecting the first conductive-type semiconductor support substrate to a first constant voltage terminal, and forming the electrode region or a third second conductive type high-concentration semiconductor region; Since the region is connected to the second constant voltage terminal, the first conductive type semiconductor supporting substrate and the second
A diode and a capacitor can be formed between the conductive type high-concentration semiconductor region. Therefore, between the semiconductor substrate of the first conductivity type and the semiconductor layer, a diode and a capacitor between the semiconductor substrate of the first conductivity type and the high-concentration semiconductor region of the second conductivity type, and an output side of the diode and the like. A high-pass filter can be formed by the resistance of the second conductivity type high-concentration semiconductor region or the like connected to the high-pass filter. As a result, when the potential of the semiconductor supporting substrate fluctuates due to a surge voltage or the like, the surge voltage can be prevented from being transmitted to the semiconductor layer by the high-pass filter.

According to the seventh aspect of the present invention, the electrode region or the third high conductivity type semiconductor region of the second conductivity type is used as the semiconductor layer or the first conductivity type semiconductor support substrate of the semiconductor device. Since the structure is formed at the end, the electrode region does not hinder the degree of freedom in layout, and does not impair the degree of integration of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing the semiconductor device in FIG. 1 without a gate electrode.

FIG. 3 is an enlarged sectional view showing an LDMOS and the like in FIG. 1 in an enlarged manner.

FIG. 4 is an electric circuit diagram showing an equivalent circuit between an output terminal and a region according to the first embodiment.

FIG. 5 is a longitudinal sectional view showing a semiconductor device according to a modification of the first embodiment.

FIG. 6 is an enlarged sectional view showing a MOSFET and the like according to a second embodiment in an enlarged manner.

FIG. 7 is an electric circuit diagram showing an equivalent circuit between a bias terminal and a p-type silicon layer according to the second embodiment.

FIG. 8 is a longitudinal sectional view showing a semiconductor device according to a first modification of the second embodiment.

FIG. 9 is a longitudinal sectional view showing a semiconductor device according to a second modification of the second embodiment.

10 is a plan view showing the semiconductor device in FIG. 9 without a gate electrode.

FIG. 11 is a longitudinal sectional view showing a semiconductor device according to a third embodiment.

FIG. 12 is a longitudinal sectional view showing a semiconductor device according to a fourth embodiment.

[Explanation of symbols]

Reference Signs List 1 SOI substrate 2 n-type silicon layer (semiconductor layer) 3 p-type support substrate (semiconductor support substrate) 4 insulating film 5 trench-grooved insulating region 7, 9, 31, 61, 67, 71 region 8, 32, 62, 72 MOSFET 10 LDMOS 10A Drain 11, 11 ', 33, 33', 63, 68, 73 Shield region 12, 34, 64 P-type region (first first conductivity type high concentration semiconductor buried region) 13, 35, 35 ', 65, 69 p-type region (second first conductivity type semiconductor diffusion region) 21, 51 bipolar transistor 21C collector 36, 66, 70 n-type region (first second conductivity type high concentration semiconductor diffusion region) 74 n-type region (second second conductivity type high concentration semiconductor region) 75 electrode region V0 ground terminal (constant voltage terminal)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/08 331 H01L 29/72 21/331 29/78 613A 29/73 621 29/786 623Z (72) Inventor Toshiro Shinohara 1370 Onna, Atsugi-shi, Kanagawa Prefecture Inside Unisex Gex Co., Ltd. (72) Inventor Teruyoshi Mihara 2 Takaracho, Kanagawa-ku, Yokohama-shi, Kanagawa Nissan Motor Co., Ltd. (72) Inventor Masakatsu Hoshi, Yokohama-shi, Kanagawa Nissan Motor Co., Ltd., 2nd, Takaracho, Kanagawa-ku (72) Inventor Yoshio Shimoda 2nd Takaracho, Kanagawa-ku, Yokohama-shi, Kanagawa Prefecture Nissan Motor Co., Ltd. F term (reference) 5F003 AP00 AP06 AZ03 BA25 BA27 BA93 BB90 BC02 BC90 BG03 BJ12 BJ15 BJ18 BJ20 5F032 AA06 AA34 AA44 AA45 AA63 AC04 BA01 BA05 BB01 CA17 CA18 CA20 CA24 DA71 5F038 BH02 BH03 BH05 B H10 BH13 CD04 EZ20 5F048 AA03 AA04 AA05 AA07 AB06 AB07 AC04 AC05 AC06 AC07 BA12 BA16 BF17 BG07 BH04 CC01 CC05 CC06 5F110 AA21 BB04 BB12 CC02 DD05 DD13 DD22 EE02 FF02 GG02 GG12 GG32 GG60 H01 NN

Claims (7)

[Claims] An SOI substrate having a semiconductor layer dielectrically separated by an insulating film on a main surface of a semiconductor support substrate, and a trench-type insulating region provided in the semiconductor layer and dielectrically separating the semiconductor layer into a plurality of regions. A first first-conductivity-type high-concentration semiconductor buried region provided in contact with the insulating film on a bottom surface of the semiconductor layer inside at least one of the plurality of regions; A second first conductivity type high concentration semiconductor diffusion region provided on the semiconductor layer main surface and in contact with the first first conductivity type high concentration semiconductor buried region, respectively; Forming a shield region comprising a first region and a second first-conductivity-type high-concentration semiconductor diffusion region; connecting the second first-conductivity-type high-concentration semiconductor diffusion region to a first constant-voltage terminal; Second constant voltage terminal, input terminal, output terminal The semiconductor device is characterized in that the configuration of connecting to or deviation. 2. A MOSFET provided in the semiconductor layer
Alternatively, a bipolar transistor is connected to an input terminal or an output terminal, and the first second-conductivity-type high-concentration semiconductor diffusion region is connected to the MO terminal.
2. The semiconductor device according to claim 1, wherein the semiconductor device comprises a drain of an SFET or a collector of the bipolar transistor, or is connected to a drain of the MOSFET or a collector of the bipolar transistor. 3. A MOSFET or a bipolar transistor formed in the semiconductor layer inside the region forms an internal circuit, and the first second conductivity type high concentration semiconductor diffusion region is connected to the second constant voltage terminal. The semiconductor device according to claim 1, wherein the semiconductor device is configured to be connected. 4. The semiconductor device according to claim 1, wherein said second first conductivity type high concentration semiconductor diffusion region is configured to be in contact with said trench type insulating region. 5. The shield region is also formed inside a region where an active element such as a MOSFET or a bipolar transistor is not formed among the plurality of regions, and the second first conductivity type high concentration semiconductor diffusion region is formed. The first
And the first second conductivity type high concentration semiconductor diffusion region is connected to the second constant voltage terminal, the input terminal,
5. The semiconductor device according to claim 1, wherein said semiconductor device is configured to be connected to one of output terminals. 6. A semiconductor device having an SOI substrate having a semiconductor layer dielectrically separated by an insulating film on a main surface of a first conductive type semiconductor support substrate, wherein the insulating film is formed on a main surface of the first conductive type semiconductor support substrate. A second second conductivity type high-concentration semiconductor region formed in contact with an electrode region formed by removing the insulating film from the semiconductor layer and connected to the second second conductivity type high-concentration semiconductor region; Forming a shield region comprising a third second conductivity type high-concentration semiconductor region; connecting the first conductivity type semiconductor support substrate to a first constant voltage terminal; A semiconductor device having a structure in which a conductive high-concentration semiconductor region is connected to a second constant voltage terminal. 7. The semiconductor device according to claim 1, wherein the electrode region or the third second conductivity type high-concentration semiconductor region is formed at an end of the semiconductor layer or the first conductivity type semiconductor support substrate in which the semiconductor device is formed. The semiconductor device according to claim 6.