JP2001028423A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide bypass capacitors near a noise generation source in an IC chip and to suppress fluctuation in a power voltage and a ground voltage is a semiconductor integrated circuit device. SOLUTION: A bypass capacitor C1 is formed by a P-N junction between an N-type well region 2e and a P-type substrate 2, on the side of an analog circuit block 20. A power line (VDD1) 22 and a ground line (VSS1) 23 are partially made to approach each other, and parasitic resistors R1 and R2, which are connected in series with the capacitor C1, are reduced. A bypass capacitor C2 is formed by a P-N junction between an N-type well region 2f and the substrate 2 on the side of a digital circuit block 21. A power line (VDD2) 26 and a ground line (VSS2) are made to approach each other in part, and parasitic resistors R3 And R4, which are connected in series with the capacitor C2, are lessened. Hereby, full noise removing capability is given to the capacitors C1 and C2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device.

In a semiconductor integrated circuit device in which a block composed of an analog circuit (hereinafter, referred to as an analog circuit block) and a block composed of a digital circuit (hereinafter, referred to as a digital circuit block) are mounted on the same semiconductor chip, a digital Electrical noise occurs during the switching operation of the circuit block. Due to the influence of the noise, the voltages of the power supply line and the ground line may become unstable, which causes a problem such as malfunction of the analog circuit. Therefore, it is necessary to suppress voltage fluctuations of the power supply line and the ground line.

[0003]

2. Description of the Related Art FIG. 16 is a sectional perspective view showing a main part of a semiconductor integrated circuit device in which an analog circuit block and a digital circuit block are mounted on the same semiconductor chip. In this semiconductor integrated circuit device, for example, an analog circuit block 1 is provided on a P-type semiconductor substrate (hereinafter, referred to as a P substrate) 1.
0 and the digital circuit block 11 are manufactured. N-type buried regions (hereinafter, referred to as N-well regions) 1a and 1d are formed in the P substrate 1. High-concentration N-type impurity diffusion regions (hereinafter, referred to as N + regions) 1c and 1b are formed in the N well regions 1a and 1d, respectively. In the P substrate 1, high-concentration P-type impurity diffusion regions (hereinafter, referred to as P + regions) 1e and 1f are formed.

The power supply line (VDD1) 12 and the ground line (VSS1) 1 of the analog circuit block 10
3 is electrically connected to N + region 1c and P + region 1e via contact group 14 and contact group 15, respectively. Power supply line (VDD2) 16 and ground line (VSS2) of digital circuit block 11
Reference numeral 17 is electrically connected to N + region 1b and P + region 1f via contact group 18 and contact group 19, respectively.

Here, a PN junction is formed between N well region 1a and P substrate 1. A capacitor is formed by the PN junction and becomes a parasitic capacitance. Also, the N + region 1c
And an N well region 1a, a resistance is formed, which becomes a parasitic resistance. These parasitic capacitance and parasitic resistance are connected in series. Similarly, at the PN junction between N well region 1d and P substrate 1, a capacitor serving as a parasitic capacitance is formed. Further, a parasitic resistance is formed between the N + region 1b and the N well region 1d. These parasitic capacitance and parasitic resistance are connected in series. Further, a parasitic resistance is formed between the two ground lines 13 and 17.

In such a digital / analog mixed circuit, at the time of the switching operation of the digital circuit, electric noise is generated by the switching current, and due to the influence, the power supply lines 12, 16 and the ground lines 13, 16 are affected.
17 may cause a voltage swing. This voltage fluctuation increases as the operation speed of the digital circuit increases, which may cause a problem such as malfunction of the analog circuit.
It is necessary to suppress 3, 17 voltage fluctuations.

Therefore, conventionally, regarding the power supply line,
By separating the power supply line 12 for the analog circuit block 10 and the power supply line 16 for the digital circuit block 11, the influence of the power supply voltage fluctuation caused by the high-speed switching operation of the digital circuit block 11 can be reduced. Power supply voltage.

As for the ground line, since the analog circuit block 10 and the digital circuit block 11 use the same substrate, the effect of the fluctuation of the ground voltage in the digital circuit block 11 from affecting the ground voltage of the analog circuit is limited. Have difficulty. Therefore, conventionally, in order to suppress the influence of the analog circuit on the ground voltage, a capacitor is mounted outside the IC chip and functions as a bypass capacitor.

[0009]

However, since the capacitor is mounted outside the IC chip, the capacitor and the noise source are separated from each other, and there is a problem that the voltage fluctuation cannot be suppressed effectively. . In order to effectively suppress voltage fluctuation caused by noise, it is necessary to arrange a capacitor near a noise source.
In addition, in order for a capacitor provided near a noise source to have sufficient noise removing capability as a bypass capacitor, it is necessary to reduce the value of a parasitic resistance connected in series with the capacitor. Also, it is difficult to provide a bypass capacitor in an IC chip because the chip area increases and the cost increases. Such a problem is the same when an N-type semiconductor substrate is used.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and a capacitor is formed in an IC chip near a noise source and is used as a bypass capacitor to reduce a power supply voltage and a ground voltage. It is an object of the present invention to provide a semiconductor integrated circuit device that suppresses fluctuation.

[0011]

In order to achieve the above object, the present invention relates to a semiconductor integrated circuit device, comprising: a ground line for supplying a ground voltage to a circuit block; and a power line for supplying a power supply voltage to the circuit block. However, at least a part thereof faces each other with a width smaller than the width of the circuit block. Therefore, the parasitic resistance connected in series to the parasitic capacitance formed due to the PN junction in the semiconductor integrated circuit device is reduced, and the parasitic capacitance can have sufficient noise removing capability as a bypass capacitor.

Further, according to the present invention, a plurality of semiconductor regions of the second conductivity type electrically connected to a power supply line for supplying a power supply voltage to a circuit block are provided in the semiconductor region of the first conductivity type. Are provided in a divided manner. Therefore, the area of the PN junction forming the parasitic capacitance increases, and as a result, the capacitance value increases, so that the parasitic capacitance can have sufficient noise removing capability as a bypass capacitor.

Further, according to the present invention, in a semiconductor region of a first conductivity type, a semiconductor region of a second conductivity type electrically connected to a power supply line for supplying a power supply voltage to a circuit block is provided. It is characterized in that it is provided in a tooth-like planar shape. Therefore, the area of the PN junction forming the parasitic capacitance increases, and as a result, the capacitance value increases, so that the parasitic capacitance can have a sufficient noise removing capability as a bypass capacitor.

Further, the present invention provides a semiconductor region of a first conductivity type, a semiconductor region of a second conductivity type formed in the semiconductor region of the first conductivity type, and a semiconductor region of the second conductivity type. A first conductivity type high-concentration impurity diffusion region formed in a semiconductor region and electrically connected to a ground line for supplying a ground voltage to a circuit block; A second conductive type high-concentration impurity diffusion region formed in the impurity diffusion region and electrically connected to a power supply line for supplying a power supply voltage to the circuit block. Therefore, the impurity (ion) concentration at the PN junction portion that forms the parasitic capacitance increases, and as a result, the capacitance value increases, so that the parasitic capacitance can have sufficient noise removing capability as a bypass capacitor.

Further, according to the present invention, there is provided an insulating film laminated on a first ground line to which a ground voltage is applied, and a first insulating film laminated on the insulating film and supplied with a power supply voltage.
A second ground line electrically connected to the first ground line and supplying a ground voltage to a circuit block; and a second ground line electrically connected to the first power line, and A second power supply line for supplying a power supply voltage to the circuit block. Therefore, a bypass capacitor is formed by the first ground line, the insulating film, and the first power supply line.

In the present invention, the first ground line may be a semiconductor substrate, the insulating film may be a gate oxide film, and the first power supply line may be a gate electrode. Then, the structure of this bypass capacitor is MO
Since it is the same as the S transistor, a bypass capacitor can be manufactured in the same process as the other MOS transistors.

In the present invention, the insulating film may be made of a material having a high dielectric constant. Then, a bypass capacitor having a larger capacitance value can be obtained.

[0018]

Embodiments of a semiconductor integrated circuit device according to the present invention will be described below in detail with reference to the drawings. In each of the following embodiments, since each semiconductor integrated circuit device can be manufactured by a well-known manufacturing process, the description of the manufacturing process is omitted.

(First Embodiment) FIG. 1 is a sectional perspective view showing a main part of a semiconductor integrated circuit device according to a first embodiment of the present invention. This semiconductor integrated circuit device is manufactured using, for example, a P substrate 2, and has an analog circuit block 2
0 and a digital circuit block 21.

The power supply line (VDD1) 22 and the ground line (VSS1) 2 of the analog circuit block 20
Numerals 3 are electrically connected to corresponding N + regions 2a and P + regions 2b formed on P substrate 2 via contact groups 24 and contact groups 25 penetrating through interlayer insulating film 2i, respectively. The power supply line (VDD2) 26 and the ground line (VSS) of the digital circuit block 21
2) 27 are the corresponding N + region 2c and P + region 2 formed on P substrate 2 via contact group 28 and contact group 29 penetrating through interlayer insulating film 2i, respectively.
d is electrically connected. The N + regions 2a and 2c are respectively formed on N well regions 2e and 2f formed on the P substrate 2.
Is formed within.

The power supply line (VDD1) 22 and the ground line (VSS1) 23 of the analog circuit block 20 are wired so as to approach each other in a region where the analog circuit block 20 does not exist. That is, the power supply line (VDD)
1) 22 is wired outside the analog circuit block 20 so as to extend along one side thereof. The ground line (VSS1) 23 is wired outside the analog circuit block 20 so as to extend along the opposite side of the power supply line (VDD1) 22.

The power supply line (VDD1) 22 and the ground line (VSS1) 23 bend and extend outside the end of the analog circuit block 20. Accordingly, the distance between the power supply line (VDD1) 22 and the ground line (VSS1) 23 is smaller than the portion where the analog circuit block 20 is interposed.

Similarly, the power supply line (VDD2) 26 of the digital circuit block 21 and the ground line (VSS2)
27 is wired so as to approach in a region where the digital circuit block 21 is not present. That is, the power supply line (V
DD2) 26 is outside the digital circuit block 21,
It is wired so as to extend along one side. Also,
The ground line (VSS2) 27 is wired outside the digital circuit block 21 so as to extend along the opposite side of the power supply line (VDD2) 26.

The power supply line (VDD 2) 26 and the ground line (VSS 2) 27 are bent and extended outside the terminal of the digital circuit block 21. Thereby, the distance between the power supply line (VDD2) 26 and the ground line (VSS2) 27 is smaller than the portion where the digital circuit block 21 is interposed.

FIG. 2 is a circuit diagram schematically showing a circuit configuration of the semiconductor integrated circuit device shown in FIG. On the analog circuit block 20 side, a parasitic capacitance is formed by a PN junction formed between the N well region 2 e and the P substrate 2. Its parasitic capacitance functions as a bypass capacitor,
In FIG. 2, it is represented by C1. Parasitic resistance exists between N + region 2a and N well region 2e and between P + region 2b and P substrate 2, respectively. In FIG.
These parasitic resistances are represented by R1 and R2.

The bypass capacitor C1 and the two parasitic resistors R1 and R2 are connected in series between a power supply line (VDD1) 22 and a ground line (VSS1) 23. Since the power supply line (VDD1) 22 and the ground line (VSS1) 23 are close to each other in a region where there is no analog circuit block 20, the distance between the power supply and the ground is short, and the two parasitic resistances R1 and R2 are small. Therefore, the bypass capacitor C1 has a sufficient noise removing ability. In other words, to the extent that the bypass capacitor C1 has a sufficient noise removal capability, the power supply line (V
DD1) 22 and the ground line (VSS1) 23 are brought closer to each other.

Similarly, on the digital circuit block 21 side, a parasitic capacitance is formed by a PN junction formed between the N well region 2f and the P substrate 2. The parasitic capacitance functions as a bypass capacitor, and is represented by C2 in FIG. The N + region 2c and the N well region 2f
, And between the P + region 2 d and the P substrate 2, respectively. In FIG. 2, those parasitic resistances are represented by R3 and R4.

The bypass capacitor C2 and the two parasitic resistors R3 and R4 are connected in series between a power supply line (VDD2) 26 and a ground line (VSS2) 27. Since the power supply line (VDD2) 26 and the ground line (VSS2) 27 are close to each other in a region where there is no digital circuit block 21, the distance between the power supply and the ground is short, and the two parasitic resistances R3 and R4 are small. Therefore, the bypass capacitor C2 has a sufficient noise removing ability. In other words, to the extent that the bypass capacitor C2 has sufficient noise removal capability, the power supply line (V
DD2) 26 and the ground line (VSS2) 27 are brought close to each other.

Further, the ground line (VSS1) 23 of the analog circuit block 20 and the digital circuit block 2
There is a parasitic resistance between the first ground line (VSS2) 27 and the first ground line (VSS2) 27. In FIG. 2, the parasitic resistance is represented by R5.

FIG. 3 is an enlarged plan view showing the vicinity of the end of N well region 2e forming bypass capacitor C1 in FIG. FIG. 4 is a longitudinal sectional view taken along line AA of FIG. Generally, the ion concentration of N well region 2e is higher at the surface layer portion 2g (the region indicated by broken lines in FIGS. 3 and 4), that is, at the boundary between N well region 2e and P substrate 2 in the horizontal direction.

The higher the ion concentration is, the larger the capacitance per unit area of the capacitor formed by the N well region 2e and the P substrate 2 is.
The capacitance value of the capacitor formed on the surface portion 2g of e becomes large. Therefore, the capacitance value of the bypass capacitor C1 is
This is substantially the capacitance value of the capacitor formed in the surface portion 2g of the N-well region 2e.

The capacitance value of the capacitor formed on the surface layer 2g is determined by the area of the surface layer 2g. Here, assuming that the length of the N well region 2e in the depth direction is constant, the surface layer portion 2
The area of g is determined by the horizontal length of the surface layer 2g.
Therefore, assuming that the length of this surface layer portion 2g in a certain direction (X direction) and the direction orthogonal to it (Y direction) are Lx and Ly, respectively, there are two portions extending in the X direction in the surface layer portion 2g. In addition, since there is one portion extending in the Y direction, the size L of the capacitor formed on the surface portion 2g is represented by the following equation (1). L = 2Lx + Ly (1)

That is, the capacitance value of the bypass capacitor C1 is a value proportional to L expressed by the above equation (1).
Although the description is omitted, the same applies to the bypass capacitor C2.

Next, the operation of the first embodiment will be described. When noise occurs in the digital circuit block 21, the noise flows to the digital circuit block 21 before flowing into the ground line 23 (VSS 1) of the analog circuit block 20 through the ground line 27 (VSS 2) of the digital circuit block 21. It is removed by the formed bypass capacitor C2. The noise generated in the analog circuit block 20 passes through a ground line 23 (VSS1) of the digital circuit block 21 through a ground line 23 (VSS1) of the analog circuit block 20.
Before flowing into 2), it is removed by a bypass capacitor C1 formed on the analog circuit block 20 side.

According to the first embodiment, on the analog circuit block 20 side, the N well region 2e and the P substrate 2
A bypass capacitor C1 is formed by the PN junction between the two. On the digital circuit block 21 side,
A PN junction between N well region 2f and P substrate 2 forms bypass capacitor C2. The bypass capacitor C1 has a portion between the N + region 2a and the N well region 2e,
And the parasitic resistances R1 and R2 existing between the P + region 2b and the P substrate 2 are connected in series, but the power supply line (VDD1) 22 and the ground line (VSS1)
23 are arranged close to each other in a region where the analog circuit block 20 is not provided.
2 becomes smaller.

The bypass capacitor C2 has N +
Between region 2c and N well region 2f, and between P + region 2
parasitic resistances R3,
R4 is connected in series, but the power supply line (VDD
2) Since the wiring 26 and the ground line (VSS2) 27 are arranged close to each other in a region where the digital circuit block 21 is not provided, the parasitic resistances R3 and R4 are reduced.

Therefore, the bypass capacitors C1, C
2 have sufficient noise removal capability, and can be used in the analog circuit block 20 or the digital circuit block 21.
, And voltage fluctuations of the power supply and the ground, which are caused by the above, can be individually removed. This eliminates the need for an external bypass capacitor. In addition, since it is not necessary to newly form a bypass capacitor dedicated to noise removal in the IC chip, it is possible to prevent an increase in the area and cost of the IC chip.

(Embodiment 2) FIG. 5 is an enlarged plan view showing the vicinity of the terminal portion of N well region 2e forming bypass capacitor C1. FIG. 6 is a vertical sectional view taken along line BB in FIG. In the second embodiment, the N well region 2e and the N + region 2a are divided into a plurality of regions in the first embodiment. In addition, about the structure which has a function similar to Embodiment 1, the same code | symbol as Embodiment 1 is attached | subjected and description is abbreviate | omitted.

Also in the second embodiment, in the same manner as in the first embodiment, in each of the divided N well regions 2e, the ion concentration in the region surface layer portion 2h is increased. Therefore, the capacitance value of the capacitor formed on the surface portion 2h increases, and the capacitance value of the bypass capacitor C1 is substantially determined by the total length of the surface portion 2h in the horizontal direction. In FIGS. 5 and 6, the surface portion 2h is indicated by a broken line, but in order to avoid complicating the drawing,
Only one of the plurality of N well regions 2e is shown, and the illustration of the remaining N well regions 2e is omitted.

In each of the divided N well regions 2e,
The length of the surface layer 2h in the X and Y directions is 1x, respectively.
And ly, there are a total of eight portions extending in the X direction, and a total of seven portions extending in the Y direction. Therefore, the capacitance value of the bypass capacitor C1 is given by the following (2).
It is a value proportional to 1 represented by the equation. l = 8lx + 7ly (2)

Incidentally, lx in the second embodiment is:
It is approximately equal to one quarter of Lx in the first embodiment. Ly in the second embodiment is the same as that in the first embodiment.
Is equal to Ly. Therefore, the above equation (2) becomes
The following equation (3) is obtained. 1 = 2Lx + 7Ly (3)

When this equation (3) is compared with the above equation (1),
It can be seen that the capacitance value of the bypass capacitor C1 of the second embodiment is larger than that of the first embodiment. Therefore, according to the second embodiment, the bypass capacitor C1 has a higher noise removal capability than the first embodiment. Although the description is omitted, the same applies to the bypass capacitor C2.

Third Embodiment FIG. 7 is a plan view showing, on an enlarged scale, a part of a power supply line and a ground line in a semiconductor integrated circuit device according to a third embodiment. FIG. 8 is a longitudinal sectional view taken along the line CC of FIG. The third embodiment is different from the first embodiment in that the power supply line (VDD)
1) 22 and the ground line (VSS1) 23 are formed in a comb shape, and they are configured to mesh with each other. N well region 2e and N + region 2a are formed in a comb shape along power supply line (VDD1) 22. The P + region 2b is connected to the ground line (VSS
1) It is formed along 23. Embodiment 1
The components having the same functions as those described in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and the description is omitted.

Also in the third embodiment, as in the first embodiment, in the comb-shaped N-well region 2e, the ion concentration of the surface layer portion 2j of the region becomes high. Therefore, the capacitance of the capacitor formed on the surface portion 2j increases, and the capacitance of the bypass capacitor C1 is
It is substantially determined by the total length of the surface layer 2j in the horizontal direction.

In this comb-shaped N-well region 2e,
The length of the surface layer 2j in the X and Y directions is mx
And my, the portion extending in the X direction is 10
Since there is one portion and one portion extends in the Y direction, the capacitance value of the bypass capacitor C1 is given by the following (4)
It is a value proportional to m represented by the equation. m = 10mx + my (4)

This is compared with the first embodiment. FIG. 10, which is an enlarged plan view showing a part of the power supply line and the ground line in the semiconductor integrated circuit device according to the first embodiment, is a vertical cross-sectional view taken along line DD in FIG. 9. In the first embodiment, since the total length of the surface portion 2j of the N-well region 2e is My, the capacitance value of the bypass capacitor C1 is a value proportional to M expressed by the following equation (5). M = My (5)

By the way, in the third embodiment, my is
It is equal to My in the first embodiment. Therefore, the above equation (4) becomes the following equation (6). m = 10mx + My (6)

From equation (6), it can be seen that according to the third embodiment, a bypass capacitor C1 having a larger capacitance value than that of the first embodiment can be obtained. Therefore,
The bypass capacitor C1 has a higher noise removal capability than in the first embodiment. Although the description is omitted, the same applies to the bypass capacitor C2.

(Fourth Embodiment) FIG. 11 is a sectional perspective view showing a main part of a semiconductor integrated circuit device according to a fourth embodiment of the present invention. In this semiconductor integrated circuit device, an N well region 3a corresponding to a collector of a bipolar transistor is formed on a P substrate 3. Inside the N well region 3a, a P offset region 3b corresponding to the base of a bipolar transistor and heavily doped with P type impurities is provided.
Is formed.

The P offset region 3b is electrically connected to a ground line 33 via a contact group 35 penetrating through the interlayer insulating film 3i. Also, P offset area 3
An N + region 3c corresponding to the emitter of the bipolar transistor is formed inside b. This N + region 3c is
It is electrically connected to the power supply line 32 via a contact group 34 penetrating through the interlayer insulating film 3i.

In the semiconductor integrated circuit device having such a configuration, the PN is located between the P offset region 3b and the N + region 3c.
A bond is formed. The capacitor formed by the PN junction is formed in the surface layers 3d and 3e (regions shown by broken lines in FIG. 11) having a high ion concentration in the P offset region 3b, and is used as a bypass capacitor for removing noise. In this case, the magnitude relationship between the ion concentrations in each region is P offset region 3b> P substrate 3, and N + region 3c> N well region 3a.

Therefore, according to the fourth embodiment, the bypass capacitor having a larger capacitance than the PN junction capacitor formed between N well region 2e and P substrate 2 in the first to third embodiments. Is obtained.
Therefore, a bypass capacitor having a larger noise removal capability can be obtained.

(Fifth Embodiment) FIG. 12 is a sectional perspective view showing a main part of a semiconductor integrated circuit device according to a fifth embodiment of the present invention. The fifth embodiment is different from the semiconductor integrated circuit device of the fourth embodiment in that an N + region 3f is further formed in N well region 3a, and a contact group 36 penetrating through interlayer insulating film 3i is formed in N + region 3f. , And another power supply line 37 is electrically connected. In addition, about the structure which has a function similar to Embodiment 4, the same code | symbol as Embodiment 4 is attached | subjected and description is abbreviate | omitted.

The power supply line 37 is electrically connected to another power supply line 32 by a conductor 41 formed on the substrate surface. Further, a P + region 3g is further formed on the P substrate 3, and another ground line 39 is formed in the P + region 3g via a contact group 38 penetrating the interlayer insulating film 3i.
Are electrically connected. This ground line 39 is electrically connected to another ground line 33 by a conductor 42 formed on the surface of the substrate.

In the semiconductor integrated circuit device having such a configuration, the PN between the P offset region 3b and the N + region 3c is
A surface layer portion 3d having a high ion concentration in the junction (the region is indicated by a broken line in FIG. 12), and a surface layer portion 3h having a high ion concentration in the PN junction between the P offset region 3b and the N well region 3a (the region is shown in FIG. A capacitor is formed in each of the surface layer portion 3j having a high ion concentration at the PN junction between the P substrate 3 and the N well region 3a (the region is indicated by a broken line in FIG. 12). These capacitors are used as bypass capacitors.

Therefore, according to the fifth embodiment, a bypass capacitor having a larger capacitance value than that of the fourth embodiment can be obtained, so that a larger noise removing capability can be obtained.

(Embodiment 6) FIG. 13 is a sectional perspective view showing a main part of a semiconductor integrated circuit device according to Embodiment 6 of the present invention. In this semiconductor integrated circuit device, the P substrate 5 is used as a ground line (VSS1) 51. Then, a thin insulating film 52 made of, for example, SiO ₂ is formed on the P substrate 5.
Are stacked, and the conductive layer 53 is further stacked thereon.
The conductive layer 53 is used as a power supply line (VDD1) 54. The power line (VDD1) 54 and the ground line (VSS1) 51 are electrically separated by an insulating film 52. Thereby, a capacitor is formed between the power supply and the ground. This capacitor is used as a bypass capacitor for removing noise.

A circuit block 55 is formed on the P substrate 5. The power line (VDD2) 56 of the circuit block 55 is connected to another power line (VDD2).
1) It is electrically connected to 54. The ground line (VSS2) 57 of the circuit block 55 is electrically connected to a P + region 5a formed on the P substrate 5 via a contact group 58 penetrating through the interlayer insulating film 5i.

According to the sixth embodiment, the circuit block 55
Power supply line (VDD1) 54 between the power supply and the ground,
Thin insulating film 52 and ground line (VSS1) 51
Is formed, and this capacitor functions as a bypass capacitor for removing noise.
Therefore, a bypass capacitor can be provided near the circuit block 55.

(Seventh Embodiment) FIG. 14 is a sectional perspective view showing a main part of a semiconductor integrated circuit device according to a seventh embodiment of the present invention. This semiconductor integrated circuit device has a configuration in which a MOS transistor is formed on a P substrate 6.
On the P substrate 6, as a gate oxide film, for example, SiO 2
_A thin oxide film 61 of 2 is laminated. A power supply line (VDD) 62 is used as a gate electrode.
The ground line (VSS) 63 is electrically connected to a P + region 6a formed on the P substrate 6 via a contact group 64 penetrating through the interlayer insulating film 6i. In FIG. 14, although the interlayer insulating film 6i is continuous with the gate oxide film, the interlayer insulating film is actually thicker than the gate oxide film. In FIG. 14, 6b is a P + region.

According to the seventh embodiment, the power supply line (VD
D) A capacitor constituted by 62 (gate electrode), gate oxide film 61 and ground line (VSS) 63 (P substrate 6) is formed, and this capacitor functions as a bypass capacitor for removing noise.

According to the seventh embodiment, another MOS
Since the bypass capacitor can be manufactured together with the transistor, the conventional manufacturing process and the like need not be changed.

(Eighth Embodiment) FIG. 15 is a sectional perspective view showing a main part of a semiconductor integrated circuit device according to an eighth embodiment of the present invention. In this semiconductor integrated circuit device, a conductive layer is laminated on a P substrate 7 and is connected to a ground line (VSS).
1) It becomes 71. Then, an insulating film 72 made of a high dielectric constant material is laminated on the conductive layer. Further, a conductive layer is laminated on the insulating film, and the power supply line (VDD1)
73. The power supply line (VDD1) 73 and the ground line (VSS1) 71 are electrically separated by an insulating film 72 made of a high dielectric constant material. Thereby, a capacitor is formed between the power supply and the ground. This capacitor is used as a bypass capacitor for removing noise.

A circuit block 74 is formed on the P substrate 7. The power line (VDD2) 75 of the circuit block 74 is connected to another power line (VDD).
1) It is electrically connected to 73. The ground line (VSS2) 76 of the circuit block 74 is electrically connected to another ground line (VSS1) 71.

According to the eighth embodiment, the circuit block 74
Power supply line (VDD1) 73 between the power supply and ground,
A capacitor composed of an insulating film 72 made of a high dielectric constant material and a ground line (VSS1) 71 is formed, and this capacitor functions as a bypass capacitor for removing noise. Therefore, a bypass capacitor can be provided near the circuit block 74. Also,
Since the insulating film 72 is made of a high dielectric constant material, a bypass capacitor having a larger capacitance value can be obtained.

In the above, the present invention is not limited to a semiconductor integrated circuit device in which digital circuits and analog circuits are mixed,
The present invention can be applied to various semiconductor integrated circuit devices requiring a bypass capacitor.

Further, the present invention is not limited to the P substrate, and is similarly applicable to the case where an N-type semiconductor substrate is used. In the case of an N-type semiconductor substrate, "P" representing the conductivity type in the above description may be replaced with "N" and "N" may be replaced with "P". Further, the power line may be replaced with a ground line, and the ground line may be replaced with a power line.

[0068]

As described above, according to the semiconductor integrated circuit device of the present invention, in the IC chip,
By forming a capacitor near the noise source and using it as a bypass capacitor, fluctuations in the power supply voltage and the ground voltage can be effectively suppressed.

[Brief description of the drawings]

FIG. 1 is a sectional perspective view showing a main part of a semiconductor integrated circuit device according to a first embodiment;

FIG. 2 is a circuit diagram schematically showing a circuit configuration of the semiconductor integrated circuit device shown in FIG.

FIG. 3 shows N forming a bypass capacitor in FIG. 1;
It is a top view which expands and shows the vicinity of the terminal part of a well area.

FIG. 4 is a longitudinal sectional view taken along line AA of FIG. 3;

FIG. 5 is a sectional perspective view showing a main part of the semiconductor integrated circuit device according to the second embodiment;

6 is a vertical sectional view taken along line BB of FIG. 5;

FIG. 7 is an enlarged plan view showing a part of a power supply line and a ground line in the semiconductor integrated circuit device according to the third embodiment;

8 is a longitudinal sectional view taken along the line CC of FIG. 7;

FIG. 9 is an enlarged plan view showing a part of a power supply line and a ground line in the semiconductor integrated circuit device according to the first exemplary embodiment;

FIG. 10 is a vertical sectional view taken along line DD in FIG. 9;

FIG. 11 is a sectional perspective view showing a main part of a semiconductor integrated circuit device according to a fourth embodiment of the present invention;

FIG. 12 is a sectional perspective view showing a main part of a semiconductor integrated circuit device according to a fifth embodiment of the present invention;

FIG. 13 is a sectional perspective view showing a main part of a semiconductor integrated circuit device according to a sixth embodiment of the present invention;

FIG. 14 is a sectional perspective view showing a main part of a semiconductor integrated circuit device according to a seventh embodiment of the present invention;

FIG. 15 is a sectional perspective view showing a main part of a semiconductor integrated circuit device according to an eighth embodiment of the present invention.

FIG. 16 is a sectional perspective view showing a main part of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

10, 11, 20, 21, 55, 74 Circuit Blocks 12, 16, 22, 26, 32, 37, 54, 56, 6
2, 73, 75 power supply lines 13, 17, 23, 27, 33, 39, 57, 63, 7
1,76 ground line 1,2,3,5,6,7 P type semiconductor substrate 2a, 2c, 3c, 3f N + region 1e, 1f, 2b, 2d, 3g, 5a, 6a, 6b P
+ Region 1a, 1b, 2e, 2f, 3a N well region 3b P offset region (high-concentration impurity diffusion region of first conductivity type) 52, 72 Insulating film

Claims (7)

[Claims] 1. A ground line for supplying a ground voltage to a circuit block and a power supply line for supplying a power supply voltage to the circuit block are opposed to each other in at least a part thereof with a width smaller than the width of the circuit block. And a semiconductor integrated circuit device. 2. A semiconductor region of a second conductivity type, which is electrically connected to a power supply line for supplying a power supply voltage to a circuit block, is divided into a plurality of regions in the semiconductor region of the first conductivity type. A semiconductor integrated circuit device characterized by being provided. 3. A comb-shaped semiconductor region electrically connected to a power supply line for supplying a power supply voltage to a circuit block in the first conductivity type semiconductor region. A semiconductor integrated circuit device provided in a shape. 4. A semiconductor region of a first conductivity type, a semiconductor region of a second conductivity type formed in the semiconductor region of the first conductivity type, and a semiconductor region of the second conductivity type. A first conductivity type high-concentration impurity diffusion region formed and electrically connected to a ground line for supplying a ground voltage to the circuit block; And a high-concentration impurity diffusion region of a second conductivity type electrically connected to a power supply line for supplying a power supply voltage to the circuit block. 5. An insulating film laminated on a first ground line to which a ground voltage is applied; a first power supply line laminated on the insulating film and to which a power supply voltage is applied; Electrically connected to one ground line, and
A second ground line for supplying a ground voltage to the circuit block; and a second power supply line electrically connected to the first power supply line and supplying a power supply voltage to the circuit block. A semiconductor integrated circuit device characterized by the above-mentioned. 6. The semiconductor device according to claim 5, wherein said first ground line is a semiconductor substrate, said insulating film is a gate oxide film, and said first power supply line is a gate electrode. Integrated circuit device. 7. The semiconductor integrated circuit device according to claim 6, wherein said insulating film is made of a high dielectric constant material.