KR0183046B1 - Gate electrode and method thereof - Google Patents
Gate electrode and method thereof Download PDFInfo
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- KR0183046B1 KR0183046B1 KR1019920012266A KR920012266A KR0183046B1 KR 0183046 B1 KR0183046 B1 KR 0183046B1 KR 1019920012266 A KR1019920012266 A KR 1019920012266A KR 920012266 A KR920012266 A KR 920012266A KR 0183046 B1 KR0183046 B1 KR 0183046B1
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- gate electrode
- polysilicon layer
- doped
- gate
- semiconductor device
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- 238000000034 method Methods 0.000 title abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 229920005591 polysilicon Polymers 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims 1
- 230000008878 coupling Effects 0.000 description 7
- 238000010168 coupling process Methods 0.000 description 7
- 238000005859 coupling reaction Methods 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 6
- 230000010354 integration Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 고집적 반도체 소자의 MOS 트랜지스터의 게이트전극 및 그 제조방법에 관한 것으로, 고집적화에 따른 게이트전극간에 캐패시터 결합노이즈로 인해 게이트전극에 누설전류가 발생되는 것을 해결하기 위하여 게이트전극에 P-N 다이오드의 미약한 특성을 갖도록 하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate electrode of a MOS transistor of a highly integrated semiconductor device, and a method of manufacturing the same. It is a technique to have one characteristic.
Description
제1도는 공지의 기술로 게이트전극을 형성한 상태의 단면도.1 is a cross-sectional view of a state in which a gate electrode is formed by a known technique.
제2도는 제1도의 우측게이트전극을 기준으로 하여 도시한 등가회로.FIG. 2 is an equivalent circuit shown on the basis of the right gate electrode of FIG.
제3도는 공지의 기술로 실리콘 기판 상부에 게이트 산화막과 N-타입 불순물이 도프된 게이트전극용 폴리실리콘층을 적층한 상태의 단면도.3 is a cross-sectional view of a state in which a gate oxide film and a polysilicon layer for a gate electrode doped with N-type impurities are stacked on a silicon substrate by a known technique.
제4도는 본 발명에 의해 게이트전극용 폴리실리콘층 상부면에 P-타입 불순물을 도프한 상태의 단면도.4 is a cross-sectional view of a polysilicon layer for gate electrode doped with a P-type impurity according to the present invention.
제5도는 공지의 기술로 게이트전극 패턴을 형성한 상태의 단면도.5 is a cross-sectional view of a state in which a gate electrode pattern is formed by a known technique.
* 도면의 주요부분에 대한 부호설명* Explanation of symbols on the main parts of the drawings
1 : 실리콘 기판 2 : 게이트 산화막1 silicon substrate 2 gate oxide film
3, 5 : 폴리실리콘층 4 : 절연막3, 5: polysilicon layer 4: insulating film
3A, 3B, 5A, 5B : 게이트전극3A, 3B, 5A, 5B: gate electrode
본 발명은 고집적 반도체 소자의 MOS 트랜지스터 게이트전극 및 그 제조방법에 관한 것으로, 특히 고집적화에 의해 게이트전극에서 누설전류가 발생되는 것을 방지하기 위하여 게이트전극 하부면과 상부면에 불순물 타입을 다르게 형성하는 게이트전극 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor gate electrode of a highly integrated semiconductor device and a method of fabricating the same. In particular, in order to prevent leakage current from occurring in the gate electrode due to high integration, a gate having different impurity types in the gate electrode lower surface and the upper surface An electrode and a method of manufacturing the same.
반도체 소자의 집적도가 증가함에 따라 초미세 패턴으로 제조하는데 이는 인터콘넥션 라인간에 간격을 더욱 좁게 만들게 된다.As the integration of semiconductor devices increases, they are manufactured in ultra-fine patterns, which further narrow the gap between interconnection lines.
따라서, 반도체 소자 제작시 전도체 간의 간격이 좁아질수록 전도체의 독립적인 동작은 여러가지 노이즈에 의해 좋지않은 영향을 받게 된다.Therefore, as the gap between conductors becomes narrower during semiconductor device fabrication, independent operation of conductors is adversely affected by various noises.
종래기술에 의한 반도체 소자 제작시 MOS 트랜지스터의 게이트전극 재료는 도프된 폴리실리콘을 사용하며 패턴이 형성된 후에는 게이트전극 사이를 절연막으로 절연시켜주고 있다.When fabricating a semiconductor device according to the prior art, the gate electrode material of the MOS transistor uses doped polysilicon, and after the pattern is formed, the gate electrode is insulated with an insulating film.
그러나 집적도가 증가되면 게이트전극간에 간격이 좁아져서 두개의 게이트전극사이에 노이즈 성분인 캐패시터 결합노이즈(Capacitive Coupling Noise)가 점점 악화되면서 게이트전극의 누설전류가 발생하게 된다.However, when the degree of integration increases, the gap between the gate electrodes is narrowed, and the capacitive coupling noise, which is a noise component, between the two gate electrodes is gradually worsened, resulting in leakage current of the gate electrode.
두개의 게이트전극 간에 캐패시터 결합노이즈를 첨부된 도면을 참조하여 설명하면 다음과 같다.Capacitor coupling noise between two gate electrodes will be described with reference to the accompanying drawings.
제1도는 실리콘 기판(1) 상부에 게이트 산화막(2)이 하부에 구비되고, N-타입 불순물이 도프된 두개의 게이트전극(3A 및 3B)이 형성되고 전체구조 상부에 절연막(4)이 형성되어 게이트전극(3A 및 3B) 상호간에 절연된 상태의 단면도이다.1 shows a gate oxide film 2 disposed below the silicon substrate 1, two gate electrodes 3A and 3B doped with N-type impurities are formed, and an insulating film 4 is formed over the entire structure. And sectional views insulated from the gate electrodes 3A and 3B.
제2도는 제1도의 좌측에 있는 게이트전극(3A)을 a-라인으로, 우측에 있는 게이트전극(3B)을 b-라인으로 설정하고, b-라인을 기준으로 설정한 상태에서 결합비(coupling factor)를 등가회로로 도시하였다. 여기서 Cc는 결합캐패시터, Cb는 벌크캐패시터, Rb는 벌크저항을 도시하며, a-라인에 Va를 공급하면 b-라인에는 Va에 영향을 받게 되는데 Va 시그날()이 Zero로 변화할때 Vb 시그날은 네가티브 볼테이지 다운(Negative Voltage Down)()이 나타나게 된다. 이때 N-채널일 경우, 소수캐리어인 홀(hole)에 의한 누설전류가 발생되는 요인이 된다.FIG. 2 shows a coupling ratio in which the gate electrode 3A on the left side of FIG. factor is shown in an equivalent circuit. Where Cc is the coupling capacitor, Cb is the bulk capacitor, and Rb is the bulk resistance. When Va is supplied to a-line, Va is affected by Va signal. Vb signal becomes negative voltage down when ) Will appear. At this time, in the case of the N-channel, a leakage current caused by a hole which is a minority carrier is generated.
따라서, 본 발명은 고집적화에 따른 게이트전극 간에 캐패시터 결합노이즈는 피할 수 없으므로 게이트전극의 형성과정에서 게이트전극 표면에 포텐셜 베리어(potential Barrier)를 형성시켜서 네가티브 볼테이지 다운에 해당하는 노이즈 시그날로 인한 게이트전극 하부의 누설전류가 흐르지 못하게 하는 게이트전극 및 그 제조방법을 제공하는데 그 목적이 있다.Therefore, in the present invention, capacitor coupling noise between gate electrodes due to high integration cannot be avoided, so that a potential barrier is formed on the surface of the gate electrode during the formation of the gate electrode, thereby forming a gate electrode due to a noise signal corresponding to negative voltage down. It is an object of the present invention to provide a gate electrode and a method of manufacturing the same, which prevent leakage of a lower leakage current.
이하, 첨부된 도면을 참고하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제3도는 실리콘 기판(1) 상부에 게이트 산화막(2)이 형성되고, 그 상부에 게이트전극용 폴리실리콘층(3)이 형성되고, N-타입 불순물이 폴리실리콘층(3)에 도프된 상태의 단면도로서, 종래의 게이트전극 형성방법과 동일한 것이다.3 shows a gate oxide film 2 formed on the silicon substrate 1, a polysilicon layer 3 for the gate electrode formed on the silicon substrate 1, and an N-type impurity doped on the polysilicon layer 3. A cross-sectional view of Fig. 2 is similar to that of the conventional gate electrode forming method.
제4도는 본 발명에 의해 N-타입 불순물이 도프된 상기 폴리실리콘층(3)의 상부면에 P-타입 불순물을 도프한 폴리실리콘층(5)을 형성한 상태의 단면도이다.4 is a cross-sectional view of a state in which a polysilicon layer 5 doped with P-type impurities is formed on an upper surface of the polysilicon layer 3 doped with N-type impurities according to the present invention.
제5도는 공지의 기술로 상기 폴리실리콘층(5)의 일정부분을 제거하여 게이트전극(5A 및 5B)을 형성한 상태의 단면도이다.5 is a cross-sectional view of a state in which gate electrodes 5A and 5B are formed by removing a portion of the polysilicon layer 5 by a known technique.
본 발명에 의해 게이트전극 상부면에 서로 상이한 타입(N타입, P타입)의 불순물을 도프하므로서 게이트전극의 상부면과 하부면에는 P-N 다이오드 특성을 미약하게 지니게 된다. 그로 인하여 게이트전극의 표면에 다이오드 특성에 의한 포텐셜 베리어가 캐패시터 결합노이즈 시그날이 네가티브 볼테이지 특성을 갖을때 역-바이어스(reverse bias)로 작동되어서 네가티브 볼테이지 다운에 해당하는 노이즈 시그날이 게이트전극을 작동시키질 못하게 된다.According to the present invention, impurities of different types (N type and P type) are doped on the upper surface of the gate electrode, so that the upper and lower surfaces of the gate electrode have weak P-N diode characteristics. Therefore, when the potential barrier due to the diode characteristic on the surface of the gate electrode is operated as a reverse bias when the capacitor coupling noise signal has a negative voltage characteristic, the noise signal corresponding to the negative voltage down operates the gate electrode. You won't be able to.
이는 N-채널 MOS 트랜지스터의 게이트전극의 소수캐리어(minority carrier)가 패스채널(path channel)이 없게됨을 뜻하며, 결국 소수캐리어에 의한 누설전류가 억제됨을 의미한다.This means that the minority carrier of the gate electrode of the N-channel MOS transistor does not have a path channel, so that leakage current by the minority carrier is suppressed.
본 발명의 또다른 실시예는 종래의 기술에 의해 N-타입 불순물이 도프된 게이트전극을 형성한 다음, 이온주입법을 이용하여 게이트전극 상부면에 P-타입 불순물을 도프시킬 수도 있다.Another embodiment of the present invention may form a gate electrode doped with N-type impurities by a conventional technique, and then dopant the P-type impurities on the top surface of the gate electrode by using an ion implantation method.
상기한 본 발명에 의하면, 게이트전극의 상부면과 하부면 사이에 P-N 다이오드 특성을 갖도록 구성시킴으로써, 캐패시터 결합노이즈에 의한 게이트전극의 누설전류를 억제할 수 있다.According to the present invention described above, by configuring the P-N diode characteristic between the upper surface and the lower surface of the gate electrode, the leakage current of the gate electrode due to the capacitor coupling noise can be suppressed.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920012266A KR0183046B1 (en) | 1992-07-10 | 1992-07-10 | Gate electrode and method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920012266A KR0183046B1 (en) | 1992-07-10 | 1992-07-10 | Gate electrode and method thereof |
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| Publication Number | Publication Date |
|---|---|
| KR940002946A KR940002946A (en) | 1994-02-19 |
| KR0183046B1 true KR0183046B1 (en) | 1999-04-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019920012266A KR0183046B1 (en) | 1992-07-10 | 1992-07-10 | Gate electrode and method thereof |
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| KR (1) | KR0183046B1 (en) |
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1992
- 1992-07-10 KR KR1019920012266A patent/KR0183046B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR940002946A (en) | 1994-02-19 |
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