KR940002946A - Gate electrode and manufacturing method - Google Patents

Gate electrode and manufacturing method Download PDF

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Publication number
KR940002946A
KR940002946A KR1019920012266A KR920012266A KR940002946A KR 940002946 A KR940002946 A KR 940002946A KR 1019920012266 A KR1019920012266 A KR 1019920012266A KR 920012266 A KR920012266 A KR 920012266A KR 940002946 A KR940002946 A KR 940002946A
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KR
South Korea
Prior art keywords
gate electrode
polysilicon layer
manufacturing
doped
type impurity
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KR1019920012266A
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Korean (ko)
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KR0183046B1 (en
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박해성
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김주용
현대전자산업주식회사
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Priority to KR1019920012266A priority Critical patent/KR0183046B1/en
Publication of KR940002946A publication Critical patent/KR940002946A/en
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Publication of KR0183046B1 publication Critical patent/KR0183046B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 고집적 반도체 소자의 MOS 트랜지스터의 게이트전극 및 그 제조방법에 관한 것으로, 고집적화에 따른 게이트전극간에 캐패시터 결합노이즈로 인해 게이트전극에 누설전류가 발생되는 것을 해결하기 위하여 게이트전극에 P-N 다이오드의 미약한 특성을 갖도록 하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate electrode of a MOS transistor of a highly integrated semiconductor device, and a method of manufacturing the same. It is a technique to have one characteristic.

Description

게이트전극 및 그 제조방법Gate electrode and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 공지의 기술로 게이트전극을 형성한 상태의 단면도.1 is a cross-sectional view of a state in which a gate electrode is formed by a known technique.

제2도는 제1도의 우측게이트전극을 기준으로 하여 도시한 등가회로.FIG. 2 is an equivalent circuit shown on the basis of the right gate electrode of FIG.

제3도는 공지의 기술로 실리콘 기판 상부에 게이트 산화막과 N-타입 불순물이 도프된 게이트전극용 폴리실리콘층을 적층한 상태의 단면도.3 is a cross-sectional view of a state in which a gate oxide film and a polysilicon layer for a gate electrode doped with N-type impurities are stacked on a silicon substrate by a known technique.

제4도는 본 발명에 의해 게이트전극용 폴리실리콘층 상부면에 P-타입 불순물을 도프한 상태의 단면도.4 is a cross-sectional view of a polysilicon layer for gate electrode doped with a P-type impurity according to the present invention.

제5도는 공지의 기술로 게이트전극 패턴을 형성한 상태의 단면도.5 is a cross-sectional view of a state in which a gate electrode pattern is formed by a known technique.

* 도면의 주요부분에 대한 부호설명* Explanation of symbols on the main parts of the drawings

1 : 실리콘 기판 2 : 게이트 산화막1 silicon substrate 2 gate oxide film

3, 5 : 폴리실리콘층 4 : 절연막3, 5: polysilicon layer 4: insulating film

3A, 3B, 5A, 5B : 게이트전극3A, 3B, 5A, 5B: gate electrode

Claims (3)

반도체 소자의 MOS 트랜지스터 게이트전극에 있어서, 전체적으로 N-타입 불순물이 도프된 게이트전극에 P-타입 불순물이 게이트전극 상부면에만 도프되어 게이트전극 상부-하부간에 P-N 다이오드의 미약한 특성을 갖는 것을 특징으로 하는 게이트전극.In the MOS transistor gate electrode of a semiconductor device, the gate electrode doped with N-type impurities as a whole is doped with P-type impurities only on the upper surface of the gate electrode, so that the PN diode has weak characteristics between the upper and lower gate electrodes. Gate electrode. 반도체 소자의 MOS 트랜지스터 게이트전극 제조방법에 있어서, 실리콘 기판 상부에 게이트 산화막과 N-타입 불순물이 도프되는 폴리실리콘층을 적층하는 단계와, 상기 폴리실리콘층 상부면에 P-타입 불순물을 도프시켜 폴리실리콘층 상부-하부면에 P-N 다이오드의 미약한 특성을 갖도록 하는 단계와, 상기 폴리실리콘층을 일정부분 제거하여 게이트전극 패턴을 형성하는 단계로 이루어지는 것을 특징으로 하는 게이트전극 제조방법.A method of manufacturing a MOS transistor gate electrode of a semiconductor device, comprising: stacking a polysilicon layer doped with a gate oxide film and an N-type impurity on a silicon substrate, and doping a P-type impurity on an upper surface of the polysilicon layer Forming a gate electrode pattern by removing a portion of the polysilicon layer and forming a gate electrode pattern on the upper and lower surfaces of the silicon layer. 반도체 소자의 MOS 트랜지스터 게이트전극 제조방법에 있어서, 실리콘 기판 상부에 게이트산화막과 N-타입 불순물이 도프되는 폴리실리콘층을 적층하는 단계와, 상기 폴리실리콘층의 일정부분을 제거하여 게이트전극 패턴을 형성하는 단계와, 상기 게이트전극으로 패턴된 폴리실리콘층의 상부면에 P-타입 불순물을 도프시켜 폴리실리콘층 패턴 상부-하부면에 P-N 다이오드의 미약한 특성을 갖도록 하는 단계로 이루어지는 게이트전극 형성방법.A method of manufacturing a MOS transistor gate electrode of a semiconductor device, comprising: depositing a polysilicon layer doped with a gate oxide film and an N-type impurity on a silicon substrate, and removing a portion of the polysilicon layer to form a gate electrode pattern And doping a P-type impurity on the upper surface of the polysilicon layer patterned with the gate electrode so as to have a weak characteristic of the PN diode on the upper and lower surfaces of the polysilicon layer pattern. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920012266A 1992-07-10 1992-07-10 Gate electrode and method thereof KR0183046B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920012266A KR0183046B1 (en) 1992-07-10 1992-07-10 Gate electrode and method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920012266A KR0183046B1 (en) 1992-07-10 1992-07-10 Gate electrode and method thereof

Publications (2)

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KR940002946A true KR940002946A (en) 1994-02-19
KR0183046B1 KR0183046B1 (en) 1999-04-15

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