KR930006963A - Manufacturing method of high breakdown voltage bipolar transistor - Google Patents

Manufacturing method of high breakdown voltage bipolar transistor Download PDF

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Publication number
KR930006963A
KR930006963A KR1019910016966A KR910016966A KR930006963A KR 930006963 A KR930006963 A KR 930006963A KR 1019910016966 A KR1019910016966 A KR 1019910016966A KR 910016966 A KR910016966 A KR 910016966A KR 930006963 A KR930006963 A KR 930006963A
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KR
South Korea
Prior art keywords
breakdown voltage
manufacturing
substrate
type
bipolar transistor
Prior art date
Application number
KR1019910016966A
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Korean (ko)
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KR940007449B1 (en
Inventor
전창기
최용철
김현수
김명성
Original Assignee
강진구
삼성전자 주식회사
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Priority to KR1019910016966A priority Critical patent/KR940007449B1/en
Publication of KR930006963A publication Critical patent/KR930006963A/en
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Publication of KR940007449B1 publication Critical patent/KR940007449B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

본 발명은 고내압 바이폴라 트랜지스터의 제조방법에 관한 것으로, 별도의 마스트없이 매몰층이 형성된 기판 전면에 n형의 불순물 전면 주입함으로써, 내압특성과 관계있는 에치층의 두께를 늘리지 않고 소자의 전기적 특성이나 고내압을 확보할 수 있는 것을 특징으로 한다.The present invention relates to a method for manufacturing a high breakdown voltage bipolar transistor, and by injecting an n-type impurity on the entire surface of the substrate where the buried layer is formed without a separate mast, the electrical characteristics of the device without increasing the thickness of the etch layer related to the breakdown voltage characteristics. It is characterized in that the high internal pressure can be secured.

Description

고내압 바이폴라 트랜지스터의 제조방법Manufacturing method of high breakdown voltage bipolar transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명으로 제작된 NPN 트랜지스터 및 SPNP 트랜지스터의 수직단면도, 제3도 (A)-(E)은 본 발명에 따른 제조공정을 나타내는 단면도.2 is a vertical cross-sectional view of the NPN transistor and the SPNP transistor fabricated according to the present invention, and FIGS.

Claims (3)

반도체기판(15)상부에 고농도의 n형 매몰층(18)을 형성하는 공정과, 그 기판(15)전면에 내압특성을 좋게하는 불순물을 주입하는 공정과, p형 기판 상부에 반정층(20)이 형성되며 그 상부에 저농도의 N형 에피층(21)을 형성하는 공정으로 이루어진 것을 특징으로 하는 반도체장치의 제조방법.Forming a high concentration n-type buried layer 18 on the semiconductor substrate 15, injecting impurities to improve the breakdown voltage characteristics on the entire surface of the substrate 15, and semi-crystal layer 20 on the p-type substrate. And forming a low concentration N-type epitaxial layer 21 thereon. 제1항에 있어서, 상기 고농도의 n형 매몰층(18) 상부의 기판(15)전면에 별도의 마스크없이 비소나 인과 같은 N형 불순물을 전면 주입하여 실효 에피층을 확보하여 내압특성을 향상시키는 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein an N-type impurity such as arsenic or phosphorus is injected into the entire surface of the substrate 15 on the high concentration n-type buried layer 18 without a separate mask to secure an effective epitaxial layer to improve breakdown voltage characteristics. A method of manufacturing a semiconductor device, characterized by the above-mentioned. 제1항에 있어서, 상기 N형 불순물을 실리콘기판의 SPNP 영역에만 주입하는 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the N-type impurity is implanted only into the SPNP region of the silicon substrate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910016966A 1991-09-28 1991-09-28 Manufacturing method of high voltage bipolar transistor KR940007449B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910016966A KR940007449B1 (en) 1991-09-28 1991-09-28 Manufacturing method of high voltage bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910016966A KR940007449B1 (en) 1991-09-28 1991-09-28 Manufacturing method of high voltage bipolar transistor

Publications (2)

Publication Number Publication Date
KR930006963A true KR930006963A (en) 1993-04-22
KR940007449B1 KR940007449B1 (en) 1994-08-18

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910016966A KR940007449B1 (en) 1991-09-28 1991-09-28 Manufacturing method of high voltage bipolar transistor

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Publication number Publication date
KR940007449B1 (en) 1994-08-18

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