CN102832211B - High voltage resistor with PIN diode isolation - Google Patents

High voltage resistor with PIN diode isolation Download PDF

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Publication number
CN102832211B
CN102832211B CN201110406344.9A CN201110406344A CN102832211B CN 102832211 B CN102832211 B CN 102832211B CN 201110406344 A CN201110406344 A CN 201110406344A CN 102832211 B CN102832211 B CN 102832211B
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Prior art keywords
dopant well
doped region
resistor
region
resistance device
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CN201110406344.9A
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CN102832211A (en
Inventor
苏如意
杨富智
蔡俊琳
郑志昌
柳瑞兴
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0676—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type comprising combinations of diodes, or capacitors or resistors
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0802—Resistors only
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    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes

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Abstract

The invention discloses a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.

Description

There is the high voltage resistor of PIN diode isolation
Technical field
The present invention relates to field of semiconductor devices, and especially, relate to a kind of high voltage resistor with PIN diode isolation.
Background technology
Semiconductor integrated circuit (IC) industry experienced by and develops fast.The technological progress of IC material and design creates many for IC, and wherein, every generation all has less and more complicated circuit than last generation.But these progress add process and manufacture the complexity of IC and for the progress that will realize, need the similar exploitation of IC process and manufacture.In the process of IC development, functional density (that is, the quantity of every chip area interconnect devices) generally increases, and physical dimension (that is, the minimal parts that manufacturing process can be used to create) reduces simultaneously.
Various types of passive circuit components can be manufactured on the semiconductor wafer.Such as, resistor can be formed as the passive circuit components on wafer.Some application require these resistors high pressure resistant (such as, up to the voltage of a few hectovolt).But traditional high voltage resistor can experience device breakdown problem before the sufficiently high voltage of arrival.Such as, traditional high voltage resistor can depend on and use P/N knot to resist puncture voltage.Limit junction breakdown by doping content, this is also not optimised in traditional high voltage resistor.
Therefore, although existing high-tension resistive device is enough to be used in the object needed for them usually, they can't meet each aspect completely.
Summary of the invention
Consider the problems referred to above, according to an aspect of the present invention, provide a kind of semiconductor device, comprising: substrate; First doped region, is arranged in the substrate; Second doped region, arrange in the substrate, the second doped region carries out contrary doping with the first doped region; 3rd doped region, is arranged in the substrate and between the first doped region and the second doped region, and the 3rd doped region has than the first doped region and the low doping content grade of the second doped region; Insulating device, on the part being arranged on the first doped region; And resistor, be arranged on insulating device.
Wherein, the first doped region, the second doped region and the 3rd doped region totally form PIN diode.
Wherein: substrate is P type substrate; First doped region comprises N-type dopant well; Second doped region comprises P type dopant well; And the 3rd doped region comprise one in lightly doped n-type intrinsic region and doped with P type intrinsic region.
Wherein, the 3rd doped region is the part of epitaxial loayer.
Wherein, the 3rd doped region has the width of scope between about 40 microns to about 70 microns.
Wherein: resistor packages is containing polycrystalline silicon material; And insulating device comprises dielectric substance.
Wherein, resistor is elongated structure, and have zigzag manner, square shape and spiral-shaped in one.
This semiconductor device also comprises the interconnection structure be arranged on resistor, and interconnection structure comprises: the first contact site, is electrically connected to the first doped region; Second contact site, is electrically connected in resistor the part be arranged between the first end of resistor and the second end; And wire, the first contact site and the second contact site are electrically connected.
Wherein, the part of resistor is approximately positioned at the midpoint of resistor.
According to a further aspect in the invention, provide a kind of high-voltage semi-conductor device, comprising: substrate; PIN diode structure, formed in the substrate, PIN diode comprises the intrinsic region between the first dopant well and the second dopant well, wherein, first dopant well and the second dopant well have contrary doping polarity, and each has the doping content grade larger than intrinsic region; Insulation system, on the part being formed in the first dopant well; Extend resistance device, be formed on insulation system, resistance device has Part I and the Part II at the opposite end place being separately positioned on resistance device; And interconnection structure, be formed on resistance device, interconnection structure comprises: the first contact site, is electrically connected to the first dopant well; Second contact site, is electrically connected to the Part III in resistor between Part I and Part II; And wire, the first contact site and the second contact site are electrically connected.
Wherein, intrinsic region has the lateral dimension of scope between about 40 microns to about 70 microns.
Wherein, resistance device comprises polycrystalline silicon material.
Wherein, resistance device have zigzag manner, square shape and spiral-shaped in one.
Wherein, the Part III of resistance device is approximately positioned at the midpoint of resistance device.
In accordance with a further aspect of the present invention, additionally provide a kind of method manufacturing high-voltage semi-conductor device, comprising: form intrinsic region in the substrate; Form the first dopant well in the substrate; First dopant well is formed adjacent with intrinsic region and has the doping content grade being greater than intrinsic region; Form the second dopant well in the substrate, the second dopant well carries out contrary doping with the first dopant well and has the doping content grade being greater than intrinsic region, and wherein, intrinsic region is arranged between the first dopant well and the second dopant well; Isolation structure is formed on the first dopant well; And resistor is formed on isolation structure.
Wherein, form intrinsic region to comprise: perform epitaxy technique to form epitaxial loayer in substrate; And epitaxial loayer pattern is turned to multiple part, one of them part is intrinsic region.
Wherein, ion implantation technology is used to perform formation intrinsic region.
Wherein: there is the mode of the lateral dimension of scope between about 40 microns to about 70 microns to perform formation intrinsic region to make intrinsic region; And intrinsic region and the first dopant well and the second dopant well totally form PIN diode structure.
The method also comprises: on resistor, form interconnection structure, wherein, forms interconnection structure and comprises: form the first contact site being electrically connected to the first dopant well; Form the second contact site being electrically connected to the part of resistor; And form the wire being electrically connected to the first contact site and the second contact site.
Wherein, the part of resistor is positioned near the mid point of resistor.
Accompanying drawing explanation
When read in conjunction with the accompanying drawings, various aspects of the present disclosure are understood better from the following detailed description.It is emphasized that according to the standard practices of industry, various parts are not drawn in proportion.In fact, clear in order to what discuss, the size of various parts can increase arbitrarily or reduce.
Fig. 1 is the flow chart of the method for the manufacture of high-voltage semi-conductor device illustrated according to various aspects of the present disclosure;
Fig. 2 is be according to various aspects of the present disclosure the schematic partial cross sectional end view of a part of wafer manufacturing each stage to Fig. 8;
Fig. 9 is the schematic partial cross sectional end view being in a part of wafer of fabrication stage according to embodiment of the present disclosure;
Figure 10 to Figure 13 is the simplification top view of the different embodiments of high voltage resistor according to various aspects of the present disclosure respectively;
Figure 14 illustrates according to the puncture voltage of the high pressure N trap of various aspects of the present disclosure the diagram of the relation of electrical bias;
Figure 15 illustrates according to the puncture voltage of various aspects of the present disclosure the diagram of the relation between light dope intrinsic region.
Embodiment
Should be appreciated that, the following disclosure provides many different embodiment or example for implementing different characteristic of the present invention.The following describe the instantiation of parts and configuration to simplify the disclosure.Certainly, these are only example and are not used in the object of restriction.In addition, in below describing first component on second component or on formed and can comprise the embodiment that the first and second parts are formed directly contact, and the embodiment that can form sandwiched first and second parts of optional feature and the first and second parts are not directly contacted can be comprised.For simplification and object clearly, various parts can be drawn arbitrarily with different ratios.
Fig. 1 shows the flow chart of the method 10 according to disclosure various aspects.Method 10 starts from frame 12, wherein, forms intrinsic region in the substrate.Method 10 proceeds to frame 14, wherein, forms the first dopant well in the substrate, and the first doped region is formed adjacent with intrinsic region and has the doping content grade higher than intrinsic region.Method 10 proceeds to frame 16, wherein, forms the second dopant well in the substrate, and the second trap carries out contrary doping with the first dopant well and has the doping content grade higher than intrinsic region, and wherein, intrinsic region is arranged between the first and second dopant wells.Method 10 proceeds to frame 18, wherein, is formed in by isolation structure on the first dopant well.Method 10 proceeds to frame 20, and wherein, resistor is formed on isolation structure.
Fig. 2 to Fig. 8 is the schematic section side view being in the various piece of the semiconductor wafer of each fabrication stage according to disclosure embodiment.Should be appreciated that, simplifying Fig. 2 to Fig. 8 to understand inventive concept of the present disclosure better.
With reference to Fig. 2, show a part for substrate 30.Substrate 30 is doped with the P type alloy of such as boron.In another embodiment, substrate 30 can doped with the N-type dopant of such as phosphorus or arsenic.Substrate 30 can also comprise another kind of suitable basic semi-conducting material, such as diamond or germanium; Suitable compound semiconductor, such as carborundum, indium arsenide or indium phosphide; Or suitable alloy semiconductor, SiGe of such as talking, gallium phosphide arsenic or InGaP.
Formed in a part for substrate 30 by ion implantation technology known in the art and imbed trap 35.Imbed N trap to be formed by injection technology, wherein, injection technology has scope from about 1 × 10 12atom/cm 2to about 2 × 10 12atom/cm 2dosage.Should be appreciated that, before execution injection technology, the photoresist layer of one patterned can be formed on the upper surface of substrate.The photoresist layer of one patterned is used as the mask during injection technology.Imbed trap 35 and be formed that there is the doping polarity contrary with substrate 30.In the embodiment shown, trap 35 is imbedded for N-type doping, this is because substrate 30 is P type substrate.In another embodiment, substrate 30 is N-type substrate, imbeds trap 35 for the doping of P type.
Perform epitaxial growth technology 40 to form epitaxial loayer 45 with imbedding above trap 35 above substrate 30.Epitaxial loayer 45 can adulterate for N-type in one embodiment, and can adulterate for P type in another embodiment.Epitaxial loayer 45 has light or low doping concentration grade.In one embodiment, epitaxial loayer 45 has scope about 5 × 10 13atom/cm 3to about 5 × 10 15atom/cm 3doping content grade.In one embodiment, epitaxial growth technology 40 is N-type epitaxy technique, and the epitaxial loayer 45 obtained has the resistivity of about 45 ohm-cms.
Now, with reference to Fig. 3, in substrate 30, high pressure dopant well 50 is formed.High pressure dopant well 50 is formed by ion implantation technology known in the art.Such as, high pressure dopant well 50 is formed by injection technology, and wherein, injection technology has scope from about 3 × 10 12atom/cm 2to about 4 × 10 12atom/cm 2dosage.Can imbed form one patterned above trap 35 photoresist layer (not shown) as the mask during injection technology.To adulterate high pressure dopant well 50 with the doping polarity (contrary with the polarity of substrate 30) identical with imbedding trap 35.In addition, to form high pressure dopant well 50 around the method imbedding trap 35.Should be appreciated that, in certain embodiments, can think and imbed the part that trap 35 is high pressure dopant wells 50, or think that they form N-type doped region jointly.
Now, with reference to Fig. 4, form dopant well 60 in the substrate.With the doping polarity identical with substrate 30, dopant well 60 is adulterated.Therefore, in the embodiment shown, dopant well 60 is formed P trap.After formation dopant well 60, epitaxial loayer 45 is divided into part 45A now, and it can also be called as epi region.Each epi region 45 is arranged between high pressure dopant well 50 (being N-type in the embodiment shown) and dopant well 60 (being P type in the embodiment shown).
PIN diode is formed by high pressure dopant well 50, epi region 45 and dopant well 60.PIN diode is the diode with the light dope intrinsic region be arranged between territory, p type island region and N-type region territory.P type and N-type region territory normally heavily doped because they can be used for ohmic contact.Light dope intrinsic region makes PIN diode be more suitable for high-voltage applications, and this will be described in detail after a while.In the embodiment shown, epi region 45 has than high pressure dopant well 50 and the low doping content grade of dopant well 60.Therefore, high pressure dopant well 50 is used as heavily doped N-type region, and dopant well 60 is used as heavily doped P-type region, and epi region 45 is used as the light dope intrinsic region of PIN diode.
Now, with reference to Fig. 5, isolation structure 80,81 is formed on epi region 45, and isolation structure 82 is formed on high pressure dopant well 50.Isolation structure 80 to 82 can comprise dielectric substance.Isolation structure 82 has thickness 90.In one embodiment, thickness 90 is in about 0.2 micron (um) scope to about 1um.In the embodiment shown in fig. 5, isolation structure 80 to 82 is local oxidation of silicon (LOCOS) device (being also referred to as field oxide).Nitride mask can be used and form LOCOS device by mask open thermal growth oxide material.Alternatively, isolation structure 80 to 82 can comprise shallow trench isolation from (STI) device or deep trench isolation (DTI) device.
After this, limit the active region of transistor, and form transistor device (not shown).Such as, these transistor devices can be field-effect transistor (FET) device, and can comprise regions and source/drain and grid structure.Regions and source/drain can for being formed in the doped region in substrate 30 or dopant well, and grid structure can comprise polysilicon gate construction or metal gate structure.These grid structures can be called as low pressure (LV) grid structure, because they are designed to process the voltage up to a few volt.
Now, with reference to Fig. 6, on isolation structure 82, resistance device 100 is formed.Resistance device 100 has elongation and curved shape.In one embodiment, word (or S) shape that has of resistance device 100.In another embodiment, resistance device 100 has spiral-shaped.In another embodiment, resistance device 100 has square shape.Clearly see these shapes hereinafter with reference to Figure 10 to Figure 13, those figures show the top view of each embodiment of resistance device 100.In the sectional view shown in Fig. 6, resistance device 100 occurs with multiple resistor block 100A to 100G.But should be appreciated that, these resistor blocks 100A to 100G is actually the part of extending resistance device.
In one embodiment, resistance device 100 comprises polycrystalline silicon material, and therefore can be called as polyresistor.Polyresistor 100 is designed to handle high voltages, such as, be greater than the voltage of about 100 volts, and can up to hundreds of volt.Therefore, polyresistor 100 can also be called as high tension apparatus.In this case, polyresistor 100 can be formed while other high pressure polysilicon gates of formation.In other words, the technique identical with forming other high pressure polysilicon gates can be used to form polyresistor 100.
After this, heavily doped region 110,111 is formed on the upper surface place of high pressure dopant well 50 and adjacent with isolation structure 80.In the embodiment shown, heavily doped region 110,111 is respectively formed between isolation structure 80-82 and 81-82.Heavily doped region 110,111 is formed by one or more ion implantation technology.Heavily doped region 110,111 has the doping polarity (be in this case N-type) identical with high pressure dopant well 50, but has higher doping content.Heavily doped region 110,111 has scope about 1 × 10 19atom/cm 3to about 1 × 10 20atom/cm 3doping content grade.
Now, with reference to Fig. 7, above isolation structure 80-82, heavily doped region 110-111 and resistance device 100, interconnection structure 150 is formed.Interconnection structure 150 comprises multiple one patterned dielectric layer and conductive layer, and it provides interconnection (such as, distribution) between circuit, I/O and various doping parts (such as, high pressure dopant well 50).More specifically, interconnection structure 150 can comprise multiple interconnection layer (being also referred to as metal level).Each interconnection layer comprises multiple interconnecting member (being also referred to as metal wire).Metal wire can be aluminum interconnecting or copper interconnecting line, and can comprise the electric conducting material of such as aluminium, copper, aluminium alloy, copper alloy, aluminium/silicon/copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide or their combination.By comprising physical vapour deposition (PVD) (PVD), chemical vapour deposition (CVD) (CVD), sputtering, plating or their technique of combination to form metal wire.
Interconnection structure 150 is included in the interlayer dielectric (ILD) providing isolation between interconnection layer.ILD can comprise the dielectric substance of such as low-k materials or oxide material.Interconnection structure 150 is also included in the multiple contact sites (contact) providing electrical connection between the parts (such as high pressure dopant well 50 or resistance device 100) on different interconnection layers and/or substrate.
As a part for interconnection structure, contact site 160 is formed on heavily doped region 110.So, contact site 160 is electrically connected to heavily doped region 110, and is therefore electrically connected to high pressure dopant well 50.Electrical bias is applied to high pressure dopant well 50 by contact site 160.Meanwhile, another contact site 161 is formed on part (segment) 100D of resistance device.Part 100D is positioned between two opposing end portions (such as, 100A and 100G) of resistance device 100, and be positioned at resistance device 100 midpoint or near.
The mid point of resistance device is point equidistant with two opposing end portions on resistance device.As an example, if resistance device 100 has the total length L measured along all coils of resistance device or circle, then the mid point of resistance device 100 is the points away from two end 0.5 × L.The impedance of device is the function of device length, width, height and material.Therefore, have at resistance device 100 in the embodiment of relatively uniform width, height and material composition, the partial ohmic of mid point both sides resistance device is 0.5 × (total impedance of resistance device).According to Kirchhoff's theorem, voltage=electric current × impedance.Therefore, because electric current keeps fixing, so voltage and impedance linearly change.This means that the voltage of resistance device midpoint is about 0.5 × (V high-V low), wherein, V highbe defined as the high pressure of an end, and V lowbe defined as the low pressure (it typically is electrical ground) of an end.
In the present embodiment, part 100D (being connected to contact site 161) in 0.1 × L of the mid point of resistance device 100, wherein, the total length of L=resistance device.In other words, this part can be positioned at distance midpoint or be not more than 0.1 × L apart from mid point.The another kind of this relation represent be distance between part 100D and end 100A or end 100G at about 0.4 × L in the scope being greater than 0.6 × L.
Interconnection structure 150 comprises the metal wire (or interconnection line) 170 being electrically connected to contact site 160 and contact site 161.By this way, high pressure dopant well 50 electrical bias is to the voltage identical with the part 100D of resistance device.In other words, the voltage (it is the percentage of the voltage of the end being applied to resistance device 100) at part 100D place is by the voltage for high pressure dopant well 50 place.Such biasing scheme provides the various advantages will discussed in detail after a while.
Now, with reference to Fig. 8, the end 100A of resistance device is connected to terminal 200, and the end 100G of resistance device is connected to terminal 201.Terminal 200 and 201 comprises the electric conducting material of such as Al or Cu or their combination.Terminal 200 and 201 can be electrically connected to end 100A and 100G by the contact site of one or more correspondence and/or metal wire (in order to the object simplified, there is no need to be shown specifically) here.Terminal 200,201 can also be formed directly into the top of resistance device 100 or not be formed directly into the top of resistance device 100.
Terminal 200 and 201 is used as the electric input/output point (or access point) of resistance device 100.Such as, high pressure (grade of hundreds of volt) can be applied to terminal 200, and terminal 201 can ground connection.Vice versa, and high pressure can be applied to terminal 201, and terminal 200 can ground connection.
As discussed above, part 100D only shows as the fraction of the high pressure that terminal 200 or terminal 201 place apply.As an example, terminal 201 is applied to and in terminal 200 ground connection and the embodiment of part 100D generally within the midpoint of resistance device 100, the voltage at part 100D place is about 250 volts at the voltages of about 500 volts.Along with the position of part 100D is moved towards end 100A or 100G away from mid point, the voltage that part 100D place is measured will depart from 250 volts.
At V highbe applied in terminal 200,201 and another terminal ground connection, and in the embodiment of the position of part 100D in the scope away from resistance device mid point 0.1 × L, the voltage at part 100D place will at about 0.4 × V highto about 0.6 × V highscope in, such as about 0.5 × V high.Because heavily doped region 110 and part 100D are linked together (therefore high pressure dopant well 50 and part 100D are linked together), this means the voltage of high pressure dopant well 50 electrical bias to part 100D place.In other words, high pressure dopant well 50 electrical bias is close to the half of the voltage difference between two terminals 200,201, and this does not realize in traditional high tension apparatus.Therefore, for traditional high tension apparatus, high-voltage is present between HVNW and an end of resistance device.This device can stand the breakdown problem caused by this high-voltage.Device breakdown limited by the thickness 90 of isolation structure 82 usually.Usually, V is worked as highwhen exceeding about 470 volts, traditional high tension apparatus can experience device breakdown problem.
Compare, the present embodiment here makes high pressure dopant well 50 electrical bias with the voltage of the voltage difference half between having close to two terminals 200,201.So, this device can stand higher voltage difference before puncturing, this is because the voltage at high pressure dopant well 50 place is not different from V very much highor V low.As an example, device herein can tolerate the voltage difference of about 730 volts in one embodiment, because high pressure dopant well 50 is biased to the half (being approximately 365 volts) of about 730 volts.In other words, this device only needs about 365 volts of tolerance to be applied to an one terminal (another terminal ground connection) can make the high pressure of about 730 volts.Meanwhile, the thickness 90 of isolation structure can be left identical with traditional devices, this is because the increase that do not need to rely on isolation structure 82 thickness of embodiment is herein to improve its tolerance to high pressure.In addition, the high pressure dopant well 50 of bias voltage can also expand the depletion region in substrate, and this can improve the electrical property of device further.
Here the PIN diode formed by high pressure dopant well 50, epi region 45 and dopant well 60 also contributes to the puncture voltage increasing resistance device 100.Do not have in the high voltage structures of light dope intrinsic region (such as, epi region 45) traditional, near the P/N knot that P trap and high pressure N trap place are formed, concentrate high electric field.This concentrated electric field can have triangle, and can cause device breakdown at the voltage place being less than about 100 volts.Compare, by mixing epi region 45, the alteration of form of electric field can be more trapezoidal shape by high tension apparatus of the present disclosure.Puncture voltage is at the integration (integral) of electric field region.At least in part due to its larger area, trapezoidal electric field herein will produce the integration larger than traditional triangular shape electric field.So, puncture voltage is added.
Epi region 45 has width 170 (lateral dimension, in the embodiment shown horizontal survey) and height 175 (or the degree of depth, in the embodiment shown vertical surveies).In one embodiment, width 170 is in the scope of about 5um to about 100um, and height 175 is in the scope of about 2um to about 6um.The grade of puncture voltage is the function of the width 170 of epi region 45.
Although epi region 45 is used as the light dope intrinsic region of PIN diode by the embodiment discussed, other devices or method also may be used for forming intrinsic region.For example, referring to Fig. 9, show the schematic partial cross sectional figure of embodiment.According to embodiment, after trap 35 is imbedded in formation, perform ion implantation technology 180 and form lightly doped region 45A in substrate 30.The photoresist layer (not shown) of one patterned can be formed as injecting mask.In one embodiment, lightly doped region 45 is formed with to imbed trap 35 adjacent.Lightly doped region 45 can have N-type doping polarity or P type doping polarity.In one embodiment, the doping content grade of lightly doped region is from about 5 × 10 13atom/cm 3to about 5 × 10 15atom/cm 3scope in.Injection technology 180 can be adulterated for N-type in one embodiment, and can adulterate for P type in another embodiment.Implanted layer 180 has light or low doping concentration grade.In one embodiment, implanted layer 180 has about 5 × 10 13atom/cm 3to about 5 × 10 15atom/cm 3scope in doping content grade.
After this, same process discussed above can be used to complete the manufacture of high tension apparatus.Such as, this additional process can comprise the formation of high pressure N trap, the formation of P trap, isolation structure formation, resistor formation etc.In order to the object simplified, do not repeat the discussion of these techniques.Be also to be understood that and can perform additional manufacturing process to complete the part of semiconductor device shown in Fig. 2 to Fig. 9.Such as, semiconductor device can stand passivation, wafer Acceptance Test and wafer dicing processes.In order to the object simplified, here do not illustrate and these additional process are discussed.
Now, with reference to Figure 10, the simplification top view of the embodiment of resistance device 250A is shown.Resistance device 250A is formed according to various aspects of the present disclosure discussed above.In this embodiment, resistance device 250A has zigzag manner or the S shape of elongation.Resistance device 250A has two opposing end portions 260 and 270.End 260 and 270 is electrically connected to terminal 280 and 290 respectively.High pressure can be applied to terminal 280, and terminal 290 is grounded, and vice versa.Therefore, by terminal 280 and 290, high pressure spot position is present in the two ends of resistance device 250A.Resistance device 250A has and two ends 260 and 270 are equidistant mid point 300 (according to along the absolute distance between the distance of resistor 250A instead of 2).According to various aspects of the present disclosure, the high pressure N trap below resistance device 250A can be electrically connected to mid point 300 or with it close to (such as, in 10% of the total length of resistance device 250A).As discussed above, this structure makes resistance device 250A have better breakdown performance, and it can stand higher voltage before puncturing.
Figure 11 shows another simplification top view of the embodiment of resistance device 250B.Resistance device 250B is formed according to various aspects of the present disclosure discussed above.In this embodiment, resistance device 250B has the square shape of elongation.Resistance device 250B has two opposing end portions 330 and 340.End 330 and 340 is electrically connected to terminal 350 and 360 respectively.High pressure can be applied to terminal 350, and terminal 360 is grounded, and vice versa.Therefore, by terminal 350 and 360, high pressure spot position is present in the two ends of resistance device 250B.Resistance device 250B has and two ends 350 and 360 are equidistant mid point 370 (according to along the absolute distance between the distance of resistor 250B instead of 2).According to various aspects of the present disclosure, the high pressure N trap below resistance device 250B can be electrically connected to mid point 370 or with it close to (such as, in 10% of the total length of resistance device 250B).Due to the similar reason discussed above with reference to Fig. 6, this structure makes resistance device 250B have better breakdown performance.
Figure 12 shows another simplification top view of the embodiment of resistance device 250C.Resistance device 250C is formed according to various aspects of the present disclosure discussed above.In this embodiment, resistance device 250C has the spiral-shaped of elongation.Resistance device 250C has two opposing end portions 410 and 420.End 410 and 420 is electrically connected to terminal 430 and 440 respectively.High pressure can be applied to terminal 430, and terminal 440 is grounded, and vice versa.Therefore, by terminal 430 and 440, high pressure spot position is present in the two ends of resistance device 250C.Resistance device 250C has and two ends 410 and 420 are equidistant mid point 450 (according to along the absolute distance between the distance of resistor 250C instead of 2).According to various aspects of the present disclosure, the high pressure N trap below resistance device 250C can be electrically connected to mid point 450 or with it close to (such as, in 10% of the total length of resistance device 250C).Due to the similar reason discussed above with reference to Fig. 6, this structure makes resistance device 250C have better breakdown performance.
Figure 13 shows another simplification top view of the embodiment of resistance device 250D.Resistance device 250D is formed according to various aspects of the present disclosure discussed above.In this embodiment, resistance device 250D has zigzag manner or the S shape of elongation.Resistance device 250D has two opposing end portions 460 and 465.End 460 and 465 is electrically connected to terminal 470 and 475 respectively.High pressure can be applied to terminal 470, and terminal 475 is grounded, and vice versa.Therefore, by terminal 470 and 475, high pressure spot position is present in the two ends of resistance device 250D.Resistance device 250D has and two ends 460 and 465 are equidistant mid point 480 (according to along the absolute distance between the distance of resistor 250D instead of 2).According to various aspects of the present disclosure, the high pressure N trap below resistance device 250D can be electrically connected to mid point 480 or with it close to (such as, in 10% of the total length of resistance device 250D).As discussed above, this structure makes resistance device 250D have better breakdown performance, and it can stand higher voltage before puncturing.
Resistance device 250D has high pressure ring junction 485.In top view, high pressure ring junction 485 is around the resistance device extended.High pressure ring junction 485 comprises doped region.In one embodiment, as discussed above, doped region is epi region 45 or lightly doped region 45A.Therefore, high pressure ring junction 485 has Ring Width 170 (also shown in Figure 8), and it is the width of epi region 45.
Figure 14 be puncture voltage and high pressure N trap be shown bias voltage between the diagram 500 of relation.The X-axis of diagram 500 represents the bias amount at the high pressure N trap place below resistance device.This bias voltage with which part of resistance device is associated according to high pressure N trap and changes.The Y-axis of diagram 500 represents puncture voltage (BV).Such as, at point 510 place, high pressure N trap is associated with the point of distance high-voltage end 0.1 × L on resistance device, wherein, and the total length of L=resistance device.Therefore, the bias voltage putting 510 place N traps is 0.9 × VH, wherein, and the voltage difference at VH=resistance device two ends.Owing to putting 510 relative to relatively keeping off the mid point of resistance device close to end, so the puncture voltage at point 510 places is not best, be slightly smaller than about 400 volts in this case.
Similarly, at point 520 place, high pressure N trap is associated with the point of distance high-voltage end 0.3 × L on resistance device, and the bias voltage putting 520 place N traps is 0.7 × VH.Owing to putting 520 closer to the mid point of resistance device compared with 510, so the puncture voltage at point 520 places is better, be a bit larger tham about 520 volts in this case, although it is not still best.
At point 530 place, high pressure N trap is similar to and is associated with the mid point of resistance device, and the bias voltage putting 530 place N traps is 0.5 × VH.The puncture voltage at point 530 places is best substantially and reaches about 730 volts.
At point 540 and 550 place, high pressure N trap is associated (or distance high-voltage end 0.3 × L and 0.1 × L) with the point of distance high-voltage end 0.7 × L and 0.9 × L on resistance device respectively.Therefore, the bias voltage at point 540 and 550 place is respectively 0.3 × VH and 0.1 × VH, and the breakdown performance of point 540 and 550 place's resistance device is deteriorated again.Therefore, as can be seen from diagram 500, when high pressure N trap is associated with the mid point close to resistance device, resistance device is tending towards reaching best breakdown performance.
Figure 15 is the diagram 600 of the relation illustrated between puncture voltage and the width of the light dope intrinsic region of PIN diode above.The X-axis of diagram 600 represents source-drain voltages (Vds), and it is also the voltage at high-tension resistive device two ends discussed herein.The Y-axis of diagram 600 represents source-drain current (Ids), and it is also the electric current in high-tension resistive device discussed herein.If resistance device suitably works, then Vds and Ids should have linear relationship, Vds=Ids × R, and wherein, R is the impedance of resistance device.But puncture if resistance device subjected to, then the relation between Vds and Ids is no longer linear.
Such as, diagram 600 comprises multiple curve plotting 610-615, and each represents the analog result of the Vds-Ids curve corresponding with the concrete width of the light dope intrinsic region of PIN diode.For curve plotting 610, the width of light dope intrinsic region is approximately 0um, means that light dope intrinsic region does not exist substantially.As shown in the figure, the resistance device be associated with curve plotting 610 stands to puncture, itself or, when Vds is about 75 volts, Ids starts upwards " outstanding (shoot) ".This puncture voltage does not meet many high-voltage applications.For curve plotting 611, the width of light dope intrinsic region is about 10um, and when Vds is about 270 volts, the resistance device be associated with curve plotting 611 stands device breakdown.For curve plotting 612, the width of light dope intrinsic region is about 20um, and when Vds is about 460 volts, the resistance device be associated with curve plotting 612 stands device breakdown.For curve plotting 613, the width of light dope intrinsic region is about 30um, and when Vds is about 560 volts, the resistance device be associated with curve plotting 613 stands device breakdown.For curve plotting 614, the width of light dope intrinsic region is about 40um, and when Vds is about 590 volts, the resistance device be associated with curve plotting 614 stands device breakdown.For curve plotting 615, the width of light dope intrinsic region is about 70um, and when Vds is about 600 volts, the resistance device be associated with curve plotting 615 stands device breakdown.
Can find out, the width increasing light dope intrinsic region (such as, the epi region 45 of Fig. 8) will increase the puncture voltage of resistance device.But at some some places, can reach capacity grade, wherein, the width increasing light dope intrinsic region can not make puncture voltage improve a lot.In the embodiment shown in fig. 15, when the width of light dope intrinsic region is in the scope of about 40um to about 70um, there is saturation grade.Can consider according to Design and manufacture and select optimum width.Such as, in one embodiment, this width can have provides sufficient puncture voltage enough greatly but the simultaneously enough little value not consuming too many chip space.
Embodiment discussed above provides the advantage more excellent than conventional high-tension device, should be appreciated that, different embodiments can provide different advantages, and does not go concrete advantage for all embodiments.An advantage is, by the suitable bias voltage of high pressure N trap, greatly can improve the breakdown performance of resistance device.Another advantage is, the bias voltage of high pressure N trap does not require extra manufacturing process and compatible with existing technological process.Therefore, herein embodiment is discussed enforcement can not increase cost.
Another advantage is, by P trap and N trap in conjunction with light dope intrinsic region, form PIN diode.Puncture voltage is increased at least up to 600 volts by PIN diode.In addition, N trap discussed above can also make puncture voltage double (if the mid point of resistor is electrically connected to N trap) effectively.So, puncture voltage can be increased to 1200 volts.
A broad form of the present disclosure relates to a kind of semiconductor device, comprising: substrate; First doped region, is arranged in the substrate; Second doped region, arrange in the substrate, the second doped region carries out contrary doping with the first doped region; 3rd doped region, is arranged in the substrate and between the first doped region and the second doped region, and the 3rd doped region has than the first doped region and the low doping content grade of the second doped region; Insulating device, on the part being arranged on the first doped region; And resistor, be arranged on insulating device.
In one embodiment, first, second, and third doped region totally forms PIN diode.
In one embodiment, substrate is P type substrate; Described doped region comprises N-type dopant well; Second doped region comprises P type dopant well; And the 3rd doped region comprise one in lightly doped n-type intrinsic region and doped with P type intrinsic region.
In one embodiment, the 3rd doped region is the part of epitaxial loayer.
In one embodiment, the 3rd doped region has the width of scope between about 40 microns to about 70 microns.
In one embodiment, resistor packages is containing polycrystalline silicon material; And insulating device comprises dielectric substance.
In one embodiment, resistor is elongated structure, and have zigzag manner, square shape and spiral-shaped in one.
In one embodiment, semiconductor device also comprises the interconnection structure be arranged on resistor, and interconnection structure comprises: the first contact, is electrically connected to the first doped region; Second contact, is electrically connected in resistor the part be arranged between the first end of resistor and the second end; And wire, the first contact is contacted with second and is electrically connected.
In one embodiment, the part of resistor is approximately positioned at the midpoint of resistor.
Another broad form of the present disclosure relates to a kind of semiconductor device, comprising: substrate; PIN diode structure, formed in the substrate, PIN diode comprises the intrinsic region between the first dopant well and the second dopant well, wherein, first dopant well and the second dopant well have contrary doping polarity, and each has the doping content grade larger than intrinsic region; Insulation system, on the part being formed in the first dopant well; Extend resistance device, be formed on insulation system, resistance device has Part I and the Part II at the opposite end place being separately positioned on resistance device; And interconnection structure, be formed on resistance device, interconnection structure comprises: the first contact, is electrically connected to the first dopant well; Second contact, is electrically connected to the Part III in resistor between Part I and Part II; And wire, the first contact is contacted with second and is electrically connected.
In one embodiment, intrinsic region has the lateral dimension of scope between about 40 microns to about 70 microns.
In one embodiment, resistance device comprises polycrystalline silicon material.
In one embodiment, resistance device have zigzag manner, square shape and spiral-shaped in one.
In one embodiment, the Part III of resistance device is approximately positioned at the midpoint of resistance device.
Another broad form of the present disclosure relates to the method manufacturing semiconductor device.The method comprises: form intrinsic region in the substrate; Form the first dopant well in the substrate, the first dopant well is formed adjacent with intrinsic region and has the doping content grade being greater than intrinsic region; Form the second dopant well in the substrate, the second dopant well carries out contrary doping with the first dopant well and has the doping content grade being greater than intrinsic region, and wherein, intrinsic region is arranged between the first dopant well and the second dopant well; Isolation structure is formed on the first dopant well; And resistor is formed on isolation structure.
In one embodiment, form intrinsic region to comprise: perform epitaxy technique to form epitaxial loayer in substrate; And by prolong a layer pattern and turn to multiple part, one of them part is intrinsic region.
In one embodiment, ion implantation technology is used to perform formation intrinsic region.
In one embodiment, to make intrinsic region have the mode of the lateral dimension of scope between about 40 microns to about 70 microns to perform formation intrinsic region; And intrinsic region and the first dopant well and the second dopant well totally form PIN diode structure.
In one embodiment, the method also comprises: on resistor, form interconnection structure, wherein, forms interconnection structure and comprises: form the first contact being electrically connected to the first dopant well; Form the second contact being electrically connected to the part of resistor; And form the wire being electrically connected to the first and second contacts.
In one embodiment, the part of resistor is positioned near the mid point of resistor.
Outline the parts of multiple embodiment above, make those skilled in the art can understand detailed description better.It should be appreciated by those skilled in the art, they can easily the disclosure be used as design and amendment be used for performing with herein introduce the identical object of embodiment and/or realize other techniques of same advantage and the basis of structure.Those skilled in the art also applies and recognizes, this equivalence formation does not deviate from spirit and scope of the present disclosure, and they carry out various change, replacement and change when not deviating from spirit and scope of the present disclosure.

Claims (20)

1. a semiconductor device, comprising:
Substrate;
First doped region, is arranged in described substrate;
Second doped region, is arranged in described substrate, and described second doped region carries out contrary doping with described first doped region;
3rd doped region, to be arranged in described substrate and between described first doped region and described second doped region, and described 3rd doped region has than described first doped region and the low doping content grade of described second doped region;
Insulating device, on the part being arranged on described first doped region, but is not arranged on above described 3rd doped region; And
Resistor, is arranged on described insulating device.
2. semiconductor device according to claim 1, wherein, described first doped region, described second doped region and described 3rd doped region totally form PIN diode.
3. semiconductor device according to claim 1, wherein:
Described substrate is P type substrate;
Described first doped region comprises N-type dopant well;
Described second doped region comprises P type dopant well; And
Described 3rd doped region comprises the one in lightly doped n-type intrinsic region and doped with P type intrinsic region.
4. semiconductor device according to claim 1, wherein, described 3rd doped region is the part of epitaxial loayer.
5. semiconductor device according to claim 1, wherein, described 3rd doped region has the width of scope between 40 microns to 70 microns.
6. semiconductor device according to claim 1, wherein:
Described resistor packages is containing polycrystalline silicon material; And
Described insulating device comprises dielectric substance.
7. semiconductor device according to claim 1, wherein, described resistor is elongated structure, and have zigzag manner, square shape and spiral-shaped in one.
8. semiconductor device according to claim 1, also comprises the interconnection structure be arranged on described resistor, and described interconnection structure comprises:
First contact site, is electrically connected to described first doped region;
Second contact site, is electrically connected in described resistor the part be arranged between the first end of described resistor and the second end; And
Wire, is electrically connected described first contact site and described second contact site.
9. semiconductor device according to claim 8, wherein, the part of described resistor is positioned at the midpoint of described resistor.
10. a high-voltage semi-conductor device, comprising:
Substrate;
PIN diode structure, be formed in described substrate, described PIN diode comprises the intrinsic region between the first dopant well and the second dopant well, wherein, described first dopant well and described second dopant well have contrary doping polarity, and each has the doping content grade larger than described intrinsic region;
Insulation system, on the part being formed in described first dopant well, and is not formed in above described intrinsic region;
Extend resistance device, be formed on described insulation system, described resistance device has Part I and the Part II at the opposite end place being separately positioned on described resistance device; And
Interconnection structure, be formed on described resistance device, described interconnection structure comprises:
First contact site, is electrically connected to described first dopant well;
Second contact site, is electrically connected to the Part III between described Part I and described Part II in described resistor; With
Wire, is electrically connected described first contact site and described second contact site.
11. high-voltage semi-conductor devices according to claim 10, wherein, described intrinsic region has the lateral dimension of scope between 40 microns to 70 microns.
12. high-voltage semi-conductor devices according to claim 10, wherein, described resistance device comprises polycrystalline silicon material.
13. high-voltage semi-conductor devices according to claim 10, wherein, described resistance device have zigzag manner, square shape and spiral-shaped in one.
14. high-voltage semi-conductor devices according to claim 10, wherein, the described Part III of described resistance device is positioned at the midpoint of described resistance device.
15. 1 kinds of methods manufacturing high-voltage semi-conductor device, comprising:
Form intrinsic region in the substrate;
The first dopant well is formed in described substrate; Described first dopant well is formed adjacent with described intrinsic region and has the doping content grade being greater than described intrinsic region;
The second dopant well is formed in described substrate, described second dopant well carries out contrary doping with described first dopant well and has the doping content grade being greater than described intrinsic region, wherein, described intrinsic region is arranged between described first dopant well and described second dopant well;
On described first dopant well, form isolation structure, but described isolation structure is not formed in above described intrinsic region; And
Resistor is formed on described isolation structure.
The method of 16. manufacture high-voltage semi-conductor devices according to claim 15, wherein, forms described intrinsic region and comprises:
Perform epitaxy technique to form epitaxial loayer in described substrate; And
Described epitaxial loayer pattern is turned to multiple part, and one of them part is described intrinsic region.
The method of 17. manufacture high-voltage semi-conductor devices according to claim 15, wherein, uses ion implantation technology to perform and forms described intrinsic region.
The method of 18. manufacture high-voltage semi-conductor devices according to claim 15, wherein:
Perform in the mode making described intrinsic region have the lateral dimension of scope between 40 microns to 70 microns and form described intrinsic region; And
Described intrinsic region and described first dopant well and described second dopant well totally form PIN diode structure.
The method of 19. manufacture high-voltage semi-conductor devices according to claim 15, also comprises: on described resistor, form interconnection structure, wherein, forms described interconnection structure and comprises:
Form the first contact site being electrically connected to described first dopant well;
Form the second contact site being electrically connected to the part of described resistor; And
Form the wire being electrically connected to described first contact site and described second contact site.
The method of 20. manufacture high-voltage semi-conductor devices according to claim 19, wherein, the part of described resistor is positioned near the mid point of described resistor.
CN201110406344.9A 2011-06-14 2011-12-08 High voltage resistor with PIN diode isolation Expired - Fee Related CN102832211B (en)

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