JPS61222249A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make it possible to manufacture an integrated circuit device having excellent performance readily, by simultaneously forming a semiconductor layer for an SOI structure and a semiconductor layer used for a bipolar transistor element on a semiconductor substrate. CONSTITUTION:A semiconductor layer 4 used for an FET element on an insulating film 2 and a semiconductor layer 4 used for a bipolar transistor element on a semiconductor substrate 1 at an opening part 3 in the insulating film 2 are simultaneously deposited. Both layers are made to be a single crystal. Before the deposition of the semiconductor layer 4, impurities are introduced through the opening part 3 of the insulating film. Thus an embedded and diffused layer 11 of the bipolar transistor element is formed. Therefore, the deep embedded and diffused layer 11 of the bipolar element can be readily formed. At the same time the semiconductor layer 4 on the layer 11 is dissolved and recrystallized, impurities are diffused in the semiconductor layer 4, and a collector region can be formed. By using this substrate, the impurity diffused regions of FETs 20, 30 and 40, a bipolar element 10 and the like can be performed in parallel. The integrated circuit device, in which characteristics of both elements are fully utilized can be readily manufactured.

Description

Detailed Description of the Invention [Summary] The present invention provides a method for manufacturing a semiconductor integrated circuit device that includes a bipolar transistor element and a field effect transistor element with an SOI structure. By forming a semiconductor layer used in an element on a semiconductor substrate, it is possible to easily manufacture an integrated circuit device with excellent performance.

[Industrial application field]

The present invention relates to a manufacturing method for easily realizing a semiconductor integrated circuit device, particularly an integrated circuit device including a bipolar transistor element and a field effect transistor element having an SOI structure, with excellent performance.

5OI (Silicon On In5ulat), which forms semiconductor devices using a silicon (Si) layer on an insulator
or) The technology is being developed. This SOI technology is a complementary MO3 field effect transistor (C-MOS FE).
T) For circuits, etc., normal F formed on a semiconductor substrate
The original objective was to improve operating speed and integration compared to ET.

However, in many cases, it is desired to use FET elements and bipolar transistor elements in integrated circuit devices by taking advantage of their respective characteristics, and a manufacturing method in which SO■ structure FET elements and bipolar transistor elements are integrated on the same substrate. There is a further demand for the establishment of

[Conventional technology]

A MOS PET having a sor structure has a structure as shown in the schematic side sectional view of FIG. 3, and is manufactured as follows.

That is, a silicon dioxide (SiO□) film 52 is formed on a silicon (Si) substrate 51 to a thickness of, for example, about 1-
A polycrystalline Si layer 53 is deposited on this SiO□ film 52 to a thickness of, for example, about 0.3 to 0.5 J1a+, and is converted into a single crystal by scanning with a laser beam, for example. Before or after this single crystallization, the Si layer 53 is patterned to a size that forms a required FET element.

Impurities necessary for forming a channel of the FET are introduced into the Si layer 53. Before and after introducing this impurity, SiO is formed on the S4 layer 53.
□Membrane 54 is formed into a membrane shape 4, and a gate electrode 55 is provided thereon. Using this gate electrode 55 as a mask, impurities are introduced to form source and drain regions 56.

The bipolar transistor element is SO like the FET element.
If it is made into an I, a horizontal structure in which an emitter, base, and collector are arranged in one Si layer is easy to manufacture. However, in lateral bipolar transistor elements,
It is difficult to narrow the base width, which is determined by the impurity doping pattern width, to increase speed, and to expand the area of the emitter junction, etc., which is restricted by the vertical cross section of the Si layer, to increase current capacity. It is not suitable for achieving high driving force and high speed with high integration density, which is the main purpose of using this method.

On the other hand, vertical bipolar transistor elements and Sol
In order to integrate the FET elements in this structure, two possible structures are a structure in which a vertical bipolar transistor element is formed in the SO1 layer and a structure in which a Si substrate is used in the opening of the insulating film.

However, of the above two types of structures, the structure in which the vertical bipolar transistor element is formed in the 801st layer does not take advantage of the characteristics of the bipolar element.

On the other hand, a structure in which an opening is provided in the insulating film and a Si substrate is used is suitable for obtaining the effect of a bipolar element, and in particular, if a Si layer is provided on the Si substrate, it is possible to create a brainer structure. .

[[C- using zone melting recrystallization 5OIli
MOS/bipolar merging technology and microwave ME
SFETJ (“Merged CMOS/bipo
lar technology and micro
wave MESFETs utilizing zo
ne-melting-recrystallzed
SOI fi1ms'') B, Y, Tsaur et
al, ;Technical Digest of I
international ElectronDevi
ces Meeting 1984+ San Fra
ncisco+ pp, 812-815] [Problems to be Solved by the Invention] As an integrated circuit device in which an FET element of an SOI structure and a bipolar transistor element are integrated, a structure in which a vertical bipolar element is provided in an opening of an insulating film is proposed. However, for example, in the above-mentioned document, a bipolar device uses a Si layer selectively epitaxially grown on a Si substrate, and prior to this epitaxial growth, polycrystalline Si is deposited and recrystallized on SiO□iO□. Is going.

In promoting the practical use of integrated circuit devices, the above-mentioned manufacturing process is complicated, and a more rational manufacturing method is desired.

[Means for solving problems]

As shown in FIG. 1, which is a schematic side sectional view of the process order of the embodiment of the present invention, the above problem is solved by selectively forming an insulating film 2 on a semiconductor substrate 1, and opening 3 of the insulating film 2. An impurity for forming a buried diffusion Ji'll of a bipolar transistor element is introduced into the semiconductor substrate 1, and a semiconductor layer 4 is laminated on the semiconductor substrate 1 in the insulating film opening 3 and on the insulating film 3. Semiconductor integration in which the semiconductor layer 4 is made into a single crystal, a bipolar transistor element is formed in the semiconductor layer 4 in the insulating film opening 3 and the semiconductor substrate 1, and a field effect transistor element is formed in the semiconductor layer 4 on the insulating film 3. The problem is solved by a method for manufacturing a circuit device.

[For production]

According to the present invention, the semiconductor layer 4 used for the FET element on the insulating film 2 and the semiconductor layer 4 used for the bipolar transistor element on the semiconductor substrate 1 in the opening 3 of the insulating film 2 are deposited simultaneously, and the semiconductor layer 4 used for the bipolar transistor element is formed into a single crystal. do.

Further, prior to depositing the semiconductor layer 4, impurities are introduced through the insulating film opening 3 to form the buried diffusion layer 11 of the bipolar transistor element. As a result, not only the deep buried diffusion layer 11 of the bipolar element is easily formed, but also impurities are diffused into the semiconductor layer 4 at the same time as the semiconductor layer 4 thereon is melted and recrystallized to form a collector region. becomes possible.

By using this substrate, it is possible to form impurity diffusion regions for FET elements and bipolar elements in parallel, and it is possible to easily manufacture integrated circuit devices that fully utilize the characteristics of pixel elements. can.

〔Example〕

The present invention will be specifically explained below with reference to an embodiment shown in FIG. 1, which is a schematic side sectional view of the process order.

FIG. 1 (see al) A mask (not shown) covering a region where a bipolar transistor element is to be formed is provided on a p-type St semiconductor substrate 1 using, for example, silicon nitride (SiJa), and a wet oxidation method is performed at a temperature of about 1050° C. A SiO□ insulating film 2 is formed to a thickness of, for example, about 1 μm.

For example, arsenic (^S) is diffused into the Si substrate 1 through the opening 3 of the SiO□ film 2 to form a male-type buried diffusion N11 having a concentration of about IXIO cm-.

See FIG. 1(b) For example, silane (SiH) is
i) Alternatively, dichlorosilane (on the Si substrate 1) or the like is thermally decomposed to form a non-doped St semiconductor layer 4 with a thickness of, for example, 1-
Si substrate 1 on stozmZ and its opening 3
deposit on top. This Si layer 4 is generally in a polycrystalline state.

For example, the Si layer 4 is scanned at a speed of 10 mm/sec and an overlap of about 50% using a C-wave, about 10 - argon (Ar) laser beam, and is melted and recrystallized to form a single crystal.

This melted and recrystallized n-type buried diffusion layer 11 was formed first.
The region 12 of the Si layer 4 in contact with this is used as the collector region with an n-type concentration of, for example, about 1 conduct.

Refer to FIG. 1(C). An npn bipolar transistor element is placed in the opening 3 of the 5i02 film 2. An n-channel MOS FET element 20 and a p-channel MOS FET are placed in the Si layer 4 on the 5iOz film 2.
A device 30 and an n-channel MO3FET device 40 are respectively formed. This process can be performed by conventional techniques.

That is, each ? The n-type N regions 3 and 41 and the p-type region 21, which serve as the channel region of the lO5FET element, and the p-type head region 13, which has a concentration of, for example, about 2XIQ"cm-3, which serves as the base region of the bipolar transistor element/device, are made of the same conductivity. The mold region is usually formed at the same time.Then the gate Si
O□ films 22, 32, 42 are formed by a thermal oxidation method, and gate electrodes 23 of each MOS FET element are formed using polycrystalline Si.
．． 33 and 43 respectively.

Next, As ions are implanted into the source, drain regions 24.44 and gate electrodes 23.43 of the MOS FET element 20.40 to form type 1, and boron ( B
) Ion implantation is performed to make it p+ type, and at the same time, the emitter region 16 and collector contact region 14 of the bipolar transistor element are made to be type 1, and the base contact region 15 is made to be p+ type.

Isolation region 17 between collector contact region 14 and base contact region 15 of the bipolar transistor element
are provided, and each electrode and wiring are formed.

In this embodiment, since an emitter follower bipolar CMOS gate circuit whose equivalent circuit diagram is shown in FIG.
E1 emitter electrode 16E, source and drain electrodes 44E of MOS FET element 40, and MOS FET element 2
1 electrode 24E of 0 is formed independently, but the MOS
One electrode of the FET element 30 is the common electrode 18 with the collector electrode of the bipolar transistor element, and the other electrode is the MO
This electrode 25 is common to one electrode of the S FET element 20.

In this example manufactured as described above, the FET element is Sol.
Taking full advantage of its structural features, the bipolar transistor element also satisfactorily served its purpose, and an integrated circuit device with high speed, high driving force, and high degree of integration was realized.

〔Effect of the invention〕

As explained above, according to the present invention, the SOI structure FET
It has become possible to easily manufacture planar integrated circuit devices with high speed and high drive power by integrating elements and bipolar transistor elements at high density and taking advantage of the characteristics of each element, and this has led to advances in semiconductor integrated circuit devices. greatly contributes to

[Brief explanation of drawings]

FIG. 1 is a schematic side sectional view showing the process order of an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram thereof. FIG. 3 is a schematic side sectional view showing a MOS FIET having an SOI structure. In the figure, 1 is a p-type Si semiconductor substrate, 2 is a SiOg insulating film, 3 is an opening in the insulating film, 4 is a Si semiconductor layer, 10 is a bipolar transistor element, 11 is an n+ type buried diffusion layer, 12 is a collector region , 13
is a base region, 14 is a collector contact region, 15 is a base contact region, 16 is an emitter region, 17 is an isolation region, 20.30
and 40 are FET elements, 21.31 and 41 are channel regions, 22.32 and 42 are gate SiO□ films, 23.33 and 43 are gate electrodes, 24.34 and 44 are source and drain regions, 18.2
5 and the subscript E indicate electrodes. Grass once

Claims (1)

[Claims] An insulating film (2) is selectively formed on a semiconductor substrate (1),
The semiconductor substrate (1) from the opening (3) of the insulating film (2)
An impurity to form a buried diffusion layer (11) of a bipolar transistor element is introduced into the semiconductor layer (4) on the semiconductor substrate (1) in the insulating film opening (3) and on the insulating film (2). The semiconductor layer (
4) is made into a single crystal, a bipolar transistor element is formed on the semiconductor layer (4) in the insulating film opening (3) and the semiconductor substrate (1), and a bipolar transistor element is formed on the semiconductor layer (4) on the insulating film (2). A method of manufacturing a semiconductor integrated circuit device, comprising forming a field effect transistor element.