JP2001135850A - Optical mosfet and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lessen troubles in a photoresist process in the manufacture of an optical MOSFET where a power MOSFET element and a photovoltaic device 4 which drives the element are formed on the same substrate, by a method wherein a level difference made by a polycrystalline Si layer is relaxed when the photovoltaic device 4 is formed of a polycrystalline Si layer. SOLUTION: A power MOSFET element 5 is of vertical type where a channel is formed on the side wall of a groove 110, and a photovoltaic device 4 is formed on a polycrystalline Si layer 106c formed through a vapor growth method on a recess that is formed at the same time when the groove 110 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an optical MOSFET used for an optical MOS relay.

[0002]

2. Description of the Related Art An optical MOS relay is a kind of solid-state relay device in which an input portion and an output portion are electrically insulated from each other and optically coupled. When a current is applied to the input side, a light emitting element (for example, a light emitting diode element) emits light, and this light is received by a photoelectric conversion element (for example, a photovoltaic device = a plurality of small solar cells connected in series) to generate a voltage. . This voltage is applied to the gate, and the power MOSFET element
N-OFF control is performed, and the load circuit connected to this output side power MOSFET element is ON-OFF controlled.

[0003] A conventional optical MOS relay incorporates a light-emitting element, a photoelectric conversion element disposed opposite to the light-emitting element, and a power MOSFET element in the same package. And, in order to make the output side compatible with AC, two power MOSFET elements are used. Further, in order to secure the switching speed, a discharge circuit for discharging the electric charge of the gate circuit of the power MOSFET may be included as an independent chip, or may be formed on the same chip as the photoelectric conversion element. Therefore, in the same package,
It is necessary to assemble three or more chips, which complicates the structure of the device and increases the manufacturing cost.

In order to solve such a problem, a proposal for forming a power MOSFET element and a photovoltaic device on the same chip is disclosed in Japanese Patent Application Laid-Open No. 2-44779. One example is a device in which a power MOSFET device and a photovoltaic device are arranged at different positions (in a planar manner) on the same substrate. This is to make an electromotive device. The point is the following manufacturing method. (1) When forming an N-Si epitaxial layer functioning as a drain to form a double-diffusion vertical power MOSFET device, the thickness is reduced by a thickness necessary for manufacturing a photovoltaic device from a required thickness. Finish growing once in the state. (2) The entire surface is oxidized, leaving the portion where the photovoltaic device is arranged, and removing the oxide film at the portion where the power MOSFET is formed. (3) Next, the remaining thickness is epitaxially grown.
Then, the portion from which the oxide film has been removed grows epitaxially, but on the oxide film, N-polycrystalline Si grows to approximately the same thickness. (4) Next, a double-diffusion vertical power MOSFET device including a gate electrode, a P base region, and an N source region is formed in a single crystal portion by a conventional method. At this time, an impurity is introduced into a portion (polycrystalline Si portion) of a photovoltaic device formed by connecting a large number of small solar cells in series at the same time as the formation of the P base region. Then, when the N source region is formed, impurities are selectively introduced so as to leave the electrode lead portion of the P region previously formed in each small solar cell forming portion. (5) Next, the polycrystalline Si layer around each small solar cell is etched away so as to electrically separate each small solar cell from other small solar cells and power MOSFET elements. (6) Next, an interlayer insulating film is formed on the entire surface, and a power MOS
In the FET element portion, a contact hole exposing the surface of each of the P-type region and the N-type region of each small solar cell is formed in the source electrode contact portion, the gate electrode lead portion, and in the photovoltaic device portion. (7) Next, a metal layer such as Al is formed on the entire surface and is subjected to a predetermined patterning, and necessary electrodes and bonding pads,
The wiring between them is formed.

According to the optical MOSFET formed as described above, a photovoltaic device and a power MOSFET are mounted on the same chip.
Since the elements are built in, the number of chips to be assembled when making the optical MOS relay is reduced by one. In addition, compared to the case where the power MOSFET element is manufactured independently, the steps to be added are only the steps (2) and (5) described above, which facilitates the manufacturing.

[0006]

However, in the method of forming a photovoltaic device simultaneously with the power MOSFET device having the DMOS structure as described above, the polycrystalline Si layer is removed by etching in the step (5). Separation causes a large step. Therefore, in the subsequent steps (6) and (7), the photoresist processing tends to cause a problem that the corners are cut or a required coating thickness cannot be secured.

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a power MOSFET device having a UMOS structure and a polycrystalline Si for forming a photovoltaic device and an element constituting a discharge circuit provided as required. Power MOSF layer
When the groove for the ET element is formed by etching, the substrate is etched at the same time and provided in a portion where the concave portion is formed, thereby alleviating the step on the surface.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Power MOSFE of UMOS structure
Various procedures for manufacturing the T element are conceivable. As a procedure for manufacturing a power MOSFET device according to the present invention, without limitation, an impurity introducing step for forming a base region and a source region is performed after forming a trench. It is preferable that a layer is formed and an impurity introduction step for forming an element forming a photovoltaic device or a discharge circuit can be shared with a power MOSFET element.

[0009]

Embodiment 1 An embodiment of the present invention will be described with reference to the drawings. The optical MOSFET 1 according to this embodiment has the light M shown in FIG.
In the equivalent circuit diagram of the OS relay, the portion enclosed by the broken line is 1
This is a chip configuration. This optical MOSFET is a light M
When the OS relay is configured, it is combined with two chips of the light emitting diode element 2 and the power MOSFET element 3.

The photo MOSFET 1 is composed of a photovoltaic device 4 in which a plurality of small solar cells 4a are connected in series, and a power MOSF whose voltage is applied to a gate and which is ON-OFF controlled.
It includes an ET element 5, two diode elements 6, 6 and a thyristor element 7 constituting a discharge circuit for speeding up a response at the time of OFF. When configuring an optical MOS relay, the photovoltaic device 4 is arranged to face the light emitting diode element 2. It is preferable that the other elements are not irradiated with light as much as possible.

The power MO in the optical MOSFET 1
The SFET element 5 is configured as a vertical type having a drain on the back side of the substrate.

Next, a detailed structure will be described while explaining a method of manufacturing the optical MOSFET 1. The left side of FIG. 1 shows the power MOSFET element 5 and the right side shows the photovoltaic device 4. FIG. 2 shows a portion of the thyristor element 7. Since the diode 6 is the same as the small solar cell 4a constituting the photovoltaic device 4, it is not shown. And these are longitudinal sectional views showing each intermediate step. (1) First, a substrate 101 made of, for example, N-type Si that functions as a drain of the power MOSFET element 5 is prepared. As the substrate 101, a substrate obtained by epitaxially growing N-type Si to a predetermined thickness on a high-concentration N-type substrate (not shown) can be used. Next, a P well 102 is formed by selectively introducing a P-type impurity. The P-well 102 is a power MOS in which a number of fine cells are arranged in a lattice.
It is arranged so as to surround the FET element to ensure a withstand voltage at the time of OFF. Further, although not shown in the drawings, if there is a place where the cell is not arranged, such as a contact portion connecting the gate electrode and the upper metal wiring or a bonding pad, the P well 102 is arranged for the same reason. The P-well 102 shown in the drawing shows the gate bonding pad portion arranged on the outer peripheral portion of the power MOSFET element 5 and is drawn large, but the portion merely surrounding the cell is narrow. Next, a thin oxide film (not shown) is formed on the entire surface by thermal oxidation, a silicon nitride film 103 is formed on the entire surface by chemical vapor deposition (hereinafter referred to as CVD), and a predetermined portion is etched. It is removed and an opening is provided. The opening is provided in the portion where the power MOSFET element 5 is to be formed so as to partition each cell, and a thick oxide such as a groove forming position 104a where a channel is to be formed on the side wall and a gate bonding pad forming position 104b is formed. This is a portion where a film needs to be formed. In the portion where the photovoltaic device 4 is formed, it is the formation position 104c of each small solar cell 4a. In the portion where the discharge circuit is formed, the formation position of the diode 6 ( (Not shown) and the planned position 104 of the thyristor element 7
d. The cell-side end 102a of the P-well 102 is made to coincide with an opening position 104a for forming a groove. Thus, the shape shown in FIGS. 1A and 2A is obtained. (2) Next, using the silicon nitride film 103 as a mask, the oxide film (not shown) in the opening is removed by etching, and the substrate 101 is subsequently etched by, for example, 1.4 μm.
Then, a thick (eg, 0.7 μm) oxide film 105 is formed by thermal oxidation using the silicon nitride film 103 as a mask.
Then, the thick oxide film 105 is selectively formed in a portion where the substrate 101 is etched in a self-aligned manner. And
After the silicon nitride film 103 is removed by etching, FIG.
2 (b) and the shape of FIG. 2 (b). (3) Next, an oxide film on the top surface of the substrate 101: N-type polycrystalline Si is deposited on the entire surface to a thickness of, for example, 1.8 μm by CVD, leaving an oxide film (not shown) under the silicon nitride film 103. Formed and etched using photoresist as a mask,
The polycrystalline Si layer 106c for the solar cell and the polycrystalline Si layer for the diode are left at the planned formation position 104c of each small solar cell 4a, the planned formation position (not shown) of the diode 6, and the planned formation position 104d of the thyristor element 7, respectively. (Not shown), and a thyristor polycrystalline Si layer 106d. If it does so, it will become a shape of FIG.1 (c) and FIG.2 (c). (4) Next, after the oxide film (not shown) on the top surface of the substrate 101 is removed by etching, the substrate 101 is again thermally oxidized.
A thin oxide film (not shown) is formed on the top surface of the substrate and on the surfaces of the polycrystalline Si layers 106c and 106d, and the power MOSFET element forming portion is opened by a photoresist, and the polycrystalline Si layer 106c for the solar cell and the diode are formed. In the portion of the polycrystalline Si layer for use (not shown), an opening is provided except for the portion where the N region electrode is provided. A mask for selectively opening each is formed, and the photoresist mask (not shown) and the thick oxide film 10 are formed.
5 in the power MOSFET element portion by ion implantation using
The base region 107a is formed. Then, at the same time, a P-type region 107c is formed in the polycrystalline Si layer 106c for the solar cell, and a P-type region (not shown) is similarly formed in the polycrystalline Si layer for the diode (not shown). In the Si layer 106d, an anode region 107d and a P base region 107b are formed. Then, Figure 1
(D) and the shape of FIG. 2 (d). (4 ′) If the impurity concentration on the surface of the P-type region formed in the above step is sufficient to make ohmic contact with a metal electrode to be formed later, the process may proceed to the next step (5).
In the case of a design with a low surface concentration, a process similar to the above step (4) is performed to form a high concentration and shallow P layer (not shown).
However, the photoresist (not shown) in the portion of the polycrystalline Si layer 106c for the solar cell and the polycrystalline Si layer for the diode (not shown) and the portion of the polycrystalline Si layer 106d for the thyristor
Need only be provided for the electrodes provided in the respective P-type regions. Further, the P-type region 107c in the polycrystalline Si layer for solar cell 106c may be formed in this step instead of being formed in the step (4). In that case, the PN junction is shallower and the sensitivity to light is higher. (5) Next, the power MOSFE is formed by photoresist.
In the T element forming portion, the source region portion is opened, and in the portion of the solar cell polycrystalline Si layer 106c and the diode polycrystalline Si layer (not shown), the portion where the N region electrode is provided is opened, and the thyristor polycrystalline silicon layer is opened. In the portion of the crystalline Si layer 106d, masks are formed to selectively open portions where the N-type contact region of the lateral thyristor and the cathode region in the P-type region are to be formed, and the photoresist mask is used for ion implantation and subsequent indentation. By the processing, in the power MOSFET element portion, the N source region 108a
To form Then, at the same time, polycrystalline Si for solar cells
An N-type contact region 108c is formed in the layer 106c, an N-type contact region (not shown) is similarly formed in the diode polycrystalline Si layer (not shown), and an N base contact is formed in the thyristor polycrystalline Si layer 106d. A region 108d and a cathode region 108b are formed. If it does so, it will become the shape of FIG.1 (e) and FIG.2 (e). (6) Next, the photoresist is used to cover a portion where the thick oxide film 105 is required to be left, such as the position 104b where the gate bonding pad is to be formed, and the thick oxide film 105 in the groove 110 surrounding the cell 109 and the polycrystalline silicon for the solar cell. The thin oxide film (not shown) on the surfaces of the Si layer 106c, the diode polycrystalline Si layer (not shown), and the thyristor polycrystalline Si layer 106d is removed by etching. Then, the photoresist is removed, and a gate oxide film (not shown) is formed by thermal oxidation. Next, polycrystalline Si is formed on the entire surface by CVD.
A gate electrode 111 is formed by forming a film, increasing conductivity by introducing a conductive impurity such as phosphorus by a vapor phase diffusion method, and patterning the film into a predetermined shape. Gate electrode 111
Is formed integrally over the entire portion of the power MOSFET element covering the bottom and side walls of the groove 110, and an opening for a source electrode is provided on the top surface of each cell 109. And
1 to the gate bonding pad formation expected position 104b
Extend to the body. Then, the polycrystalline Si film is removed in a region where the photovoltaic device and the discharge circuit are arranged. If it does so, it will become a shape of FIG.1 (f) and FIG.2 (f). (7) Next, after an oxide film (not shown) is formed on the surface of the gate electrode 111 by thermal oxidation, an interlayer insulating film 112 made of, for example, BPSG is formed by CVD, and a contact hole for each electrode is formed. Then, each electrode and a predetermined wiring are formed with a metal such as Al. Then, Figure 1
2 (g) and the shape shown in FIG. 2 (g).

Here, the source electrode 113a is in contact with the source region 108a and the P base region 107a of each of the cells 109 provided in a large number in a grid pattern so as to be in contact with the interlayer insulating film 112.
Each cell 109 is connected above. The source electrode 113a is also in contact with the P-well 102 at a position that does not appear as a cross-sectional view in FIG. Then, as shown in FIG. 3, the source electrode 113a is connected to the cathode electrode of the thyristor element 7 and to the anode electrode of one of the diodes 6 at a position not appearing as a cross-sectional view in FIG. The source electrode 113a also serves as a pad for wire bonding connection with the source electrode of the separate power MOSFET element 3 when configuring the optical MOS relay.

The gate wiring 113b is in contact with the gate electrode 111 at the position 104b where the gate bonding pad is to be formed, and is connected to the gate electrode of the separate power MOSFET device 3 by wire bonding when forming an optical MOS relay. It has become a pad. The gate wiring 113b is connected to the anode electrode of the thyristor element 7 and to the cathode electrode of the other diode 6, as shown in FIG.

The wiring 113c between solar cells contacts the P-type region 107c of the small solar cell and contacts the N-type contact region 108c of the adjacent small solar cell to connect a plurality of small solar cells 4a in series to generate photovoltaic signals. Power device 4
And Then, the N-type contact region 108c of the small solar cell at one end (the P-type region 107 of the small solar cell at the other end)
c) is contacted with the electromotive element wiring 113d, and the cathode electrode of one diode 6 and the P of the thyristor element 7 are connected.
It is connected to the gate electrode (the anode electrode of the other diode 6 and the N gate electrode of the thyristor element 7).

The thyristor polycrystalline Si layer 106
In the part d, the anode electrode 113f contacting the anode region 107d of the horizontal thyristor, and the cathode region 1
Cathode electrode 113g contacting Pb 08b, and P gate electrode 113 contacting P base region 107b
h, N gate electrodes 113i that are in contact with the N base contact region 108d are formed and connected as described above.

Thus, as shown in FIGS. 1 (g) and 2 (g), an optical MOS including a discharge circuit including a power MOSFET element 5, a photovoltaic device 4, and a thyristor element 7 in one chip.
FET1 is completed.

According to the above embodiment, the power MOSFET
A groove 110 and a concave portion of a gate bonding pad portion are provided in the portion of the element 5, but when performing a photoresist process, the step is reduced by being buried with a thick oxide film 105 and a gate electrode 111, and a photoresist process is possible. It is in a state. For example, at the beginning of the groove 110, 1.4 μm
After being excavated, a thick oxidation is performed so as to have a thickness of 0.7 μm.
Although the groove is considerably deep, the width is about 1 μm and narrow, so that the polycrystalline Si layer serving as the gate electrode 111 has a thickness of 0.5 μm.
If it grows m, it will be buried. In a portion where a small solar cell or a thyristor element is formed, a recess is formed in the substrate 101 and a polycrystalline Si layer is provided so as to fill the recess, so that the step is reduced.

[0019]

Embodiment 2 Next, a second embodiment will be described. The optical MOSFET 10 of this embodiment has a one-chip configuration in a portion surrounded by a broken line in the equivalent circuit diagram of the optical MOS relay shown in FIG. This optical MOSFET is configured such that only the light emitting diode element 2 is combined when configuring the optical MOS relay.

This optical MOSFET 10 is a photovoltaic device 4 similar to that of the first embodiment, and a power MOSFET whose voltage is applied to the gate and which is ON-OFF controlled.
Two sets of elements 13 and 15 are provided. The two photovoltaic devices 4 and 4 are arranged close to each other, and one light emitting diode element 2
And are simultaneously responsive to the light. A discharge circuit including two diode elements 6, 6 and a thyristor element 7 is also provided for each.

The power M in the optical MOSFET 10
The OSFET elements 13 and 15 are configured as a vertical type having a drain on the substrate side. Then, as shown in FIG. 4, the drains are commonly connected, and the respective sources are used as output terminals. Therefore, it is of course preferable to perform a firm separation such as a dielectric separation between the two power MOSFET elements 13 and 15, but it is not always necessary. In order to prevent latch-up, it is sufficient to increase the distance between the two.

The optical MOSFET 1 shown in FIG.
0, two power MOSFET elements 1
Photovoltaic device 4 and discharge circuit arrangement area 17 are provided at a central position so as to partition 3 and 15.

The structure and manufacturing method of the optical MOSFET 10 in the vertical direction are similar to those of the first embodiment, so that the description is omitted. According to the optical MOSFET 10, when configuring the optical MOS relay, only the light emitting diode element 2 is required as a chip, and the structure is simple and easy to assemble.

[0024]

Embodiment 3 Next, a third embodiment will be described. The optical MOSFET 20 of this embodiment has a one-chip configuration in a portion surrounded by a broken line in the equivalent circuit diagram of the optical MOS relay shown in FIG. This optical MOSFET is configured such that only the light emitting diode element 2 is combined when configuring the optical MOS relay.

This photo MOSFET 20 is a photovoltaic device 4 similar to that of the first embodiment, and two power MOSFETs whose voltage is applied to the gate and which is ON-OFF controlled.
FET devices 23 and 25 are provided. Then, the photovoltaic device 4 is arranged close to the light emitting diode element 2 and is responsive to the light. A discharge circuit including two diode elements 6, 6 and a thyristor element 7 is also provided in the same manner as in the first embodiment.

The power M in the optical MOSFET 20
The OSFET elements 23 and 25 are insulated and separated from each other, and the drain electrode is also led out to the surface together with the gate and source electrodes. Then, as shown in FIG. 6, the sources are commonly connected, and each drain is used as an output terminal.

In this case, in order to insulate and separate the two power MOSFET elements 23 and 25 from each other, a bipolar I
The known PN junction separation technique used in C can be applied. The method of leading the collector electrode of the vertical power bipolar transistor to the surface in a bipolar IC can also be applied to leading the drain electrode of the vertical power MOSFET element to the surface. For example, when fabricating an N-channel power MOSFET device, an N-type epitaxial layer is grown on a P-type substrate, and a P-type impurity such as boron is deposited on the substrate to surround a portion where the N-channel power MOSFET device is to be formed. It can be separated by spreading to reach a straight. Then, in order to lead the drain electrode to the surface, an N-type impurity is buried and diffused at a high concentration in a portion where the N-channel power MOSFET element of the substrate is formed, and after the epitaxial growth, the buried diffusion layer is reached from the surface. N-type impurities may be diffused at a high concentration.

The method of manufacturing the power MOSFET element, the photovoltaic element, and the discharge circuit is the same as that of the first embodiment if the above-mentioned substrate is used. However, as a modification of this embodiment, the discharge circuit can be constituted by a single crystal portion which is isolated and not formed in the polycrystalline Si layer.

In each of the first, second, and third embodiments, a discharge circuit is provided. However, when a small solar cell is formed of polycrystalline Si as in the present invention, a single crystal S
Since the discharge when light is no longer generated is faster than that formed by i, the discharge circuit may be omitted if the speed at the time of turning off the optical MOS relay can be tolerated.

In each of the first, second, and third embodiments, as a method of manufacturing a power MOSFET device, first, a groove and a thick oxide film are formed thereon, and the oxide film is used as a mask. After forming a base region and a source region, and thereafter forming a gate oxide film and a gate electrode made of polycrystalline Si, the polycrystalline Si for forming an element constituting a small solar cell or a discharge circuit is formed. The process of forming a layer is provided independently, but first, a groove is formed, a gate electrode made of a gate oxide film and polycrystalline Si is formed, and a base region and a source region are formed using the gate electrode as a mask. Then, the polycrystalline Si layer serving as a gate electrode can be used as a polycrystalline Si layer for forming a small solar cell or an element constituting a discharge circuit. However, when the impurity is introduced into the polycrystalline Si layer at a high concentration to reduce the resistance in order to use it as a gate electrode, the impurity is not introduced into a portion where an element forming a small solar cell or a discharge circuit is formed. Must be masked.

[0031]

As described above, the optical MO of the present invention is
In SFET, a power MOSFET is formed by UMO to form a power MOSFET element and a small solar cell on the same substrate.
Since a small-sized solar cell is formed by forming an S structure and providing a polycrystalline Si layer in a concave portion formed at the same time when the groove is dug, a step on the surface is reduced and troubles in the photoresist processing are reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a power MOSFET element and a small solar cell for explaining a method of manufacturing an optical MOSFET according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a portion of a thyristor element for explaining a method of manufacturing the optical MOSFET of the embodiment.

FIG. 3 shows an optical MO using the optical MOSFET of the above embodiment.
FIG. 3 is a circuit diagram when an S relay is configured.

FIG. 4 is a circuit diagram when an optical MOS relay is configured using the optical MOSFET according to the second embodiment of the present invention.

FIG. 5 is a plan view of an optical MOSFET according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram when an optical MOS relay is configured using the optical MOSFET according to the third embodiment of the present invention.

[Description of Signs] 1,10,20 Photo MOSFET 4 Photovoltaic device 4a Small solar cell 5,13,15,23,25 Power MOSFET element 6 Diode (element constituting discharge circuit) 7 Thyristor element (discharge circuit 101) Substrate 103 Silicon nitride film 105 Oxide film 106c, 106d Polycrystalline Si layer 107a P base region (impurity introduction region) of power MOSFET device 107b P base region of thyristor device 107c P type region of small solar cell 107d Thyristor Anode region of device 108a Source region (impurity introduction region) of power MOSFET device 108b Cathode region of thyristor device 108c N-type contact region of small solar cell 108d N-base contact region of thyristor device 110 Groove

Claims (5)

[Claims] 1. An optical MOS device in which a power MOSFET element and a photovoltaic device for driving the power MOSFET element are formed on the same substrate.
In the FET, the power MOSFET element is a vertical type in which a channel is formed on a side wall of a groove, and the photovoltaic device is formed in a polycrystalline Si layer formed by vapor phase growth on a concave portion formed simultaneously with the formation of the groove. An optical MOSFET characterized in that: 2. The photo-MOSFET includes a discharge circuit for speeding up a response at the time of OFF, and an element constituting the discharge circuit is a polycrystal formed by vapor-phase growth on a recess formed simultaneously with the formation of the groove. The optical MOSFET according to claim 1, wherein the optical MOSFET is formed on a Si layer. 3. An optical MOS device in which a power MOSFET element and a photovoltaic device for driving the power MOSFET element are formed on the same substrate.
In the method for manufacturing an FET, the power MOSFET element is a vertical type having a channel formed on a side wall of a groove, and a part where a small solar cell constituting a photovoltaic device is simultaneously formed when the groove is formed is etched. A step of forming a concave portion, and a step of disposing a polycrystalline Si layer for forming a small solar cell on the concave portion via an oxide film. Forming a photovoltaic cell. 4. An optical MOS device in which a power MOSFET element and a photovoltaic device for driving the power MOSFET element are formed on the same substrate.
In a method of manufacturing an FET, a silicon nitride film is formed on a surface of a substrate made of Si, and a portion of a channel where a channel of a power MOSFET element is formed is removed by etching to form an opening, and a photovoltaic device is formed. A step of etching and removing a portion where the small solar cell is disposed to form an opening, and etching the substrate using the silicon nitride film as a mask to form a concave portion, and then performing selective oxidation using the silicon nitride film as a mask. A step of forming an oxide film, and thereafter, a polycrystalline Si layer is formed over the entire surface by vapor phase growth,
A step of arranging a polycrystalline Si layer on the concave portion for forming a small solar cell by etching to leave a portion necessary for forming a small solar cell; When forming a predetermined impurity introduction region by introducing a n-type impurity and an n-type impurity,
Simultaneously forming a small solar cell by introducing necessary impurities into the polycrystalline Si. 5. An optical MOSFET in which a power MOSFET element, a photovoltaic device for driving the power MOSFET element, and a discharge circuit for quick response at the time of OFF are formed on the same substrate.
Forming a silicon nitride film on the surface of a substrate made of Si, etching and removing a portion corresponding to a groove formed on a side wall of a channel of a power MOSFET device, and forming a photovoltaic device. A step of etching and removing a portion where elements constituting a solar cell or a discharge circuit are arranged, and forming an opening; etching the substrate using the silicon nitride film as a mask to form a concave portion; and then using the silicon nitride film as a mask. Forming an oxide film by selective oxidation, and thereafter forming a polycrystalline Si layer over the entire surface by vapor phase growth,
A step of arranging a polycrystalline Si layer on a recess for forming an element forming a small solar cell or a discharge circuit by etching to leave a portion required for forming an element forming a small solar cell or a discharge circuit; and thereafter, a power MOSFET element When a P-type impurity and an N-type impurity are introduced using the oxide film in the trench as a mask in a formation portion to form a predetermined impurity introduction region,
Forming a device for forming a small solar cell or a discharge circuit by introducing necessary impurities into the polycrystalline Si at the same time.