JPS6322474B2 - - Google Patents
Info
- Publication number
- JPS6322474B2 JPS6322474B2 JP55177830A JP17783080A JPS6322474B2 JP S6322474 B2 JPS6322474 B2 JP S6322474B2 JP 55177830 A JP55177830 A JP 55177830A JP 17783080 A JP17783080 A JP 17783080A JP S6322474 B2 JPS6322474 B2 JP S6322474B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- region
- substrate
- semiconductor light
- series
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- CPLXHLVBOLITMK-UHFFFAOYSA-N Magnesium oxide Chemical compound [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 18
- 239000000395 magnesium oxide Substances 0.000 claims description 14
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- 229910052596 spinel Inorganic materials 0.000 claims description 4
- 239000011029 spinel Substances 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/0475—PV cell arrays made by cells in a planar, e.g. repetitive, configuration on a single semiconductor substrate; PV cell microarrays
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Molecular Biology (AREA)
- Sustainable Development (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Photovoltaic Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体受光装置に関り、特に高出力電
圧が得られる直列もしくは直並列接続構造のモノ
リシツク型半導体受光装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor light receiving device, and more particularly to a monolithic semiconductor light receiving device having a series or series-parallel connection structure capable of obtaining a high output voltage.
半導体集積回路（IC）等に形成される
MOSFETのゲートを制御するためには、通常５
〔Ｖ〕前後の電圧が必要である。従つて光制御IC
を形成する際には、該ICの光制御電源として少
くとも５〔Ｖ〕以上の出力電圧がとり出せる半導
体受光素子（例えば太陽電池）が必要となる。然
し従来の太陽電池に於ては１〔チツプ〕から取り
出し得る電圧は0.5〔Ｖ〕前後であるために、上記
光制御ICは少くとも10〔個〕以上の太陽電池チツ
プを直列に接続するハイブリツド構造で形成せざ
るを得ず、該光制御ICの外形寸法が大型になる
という不都合があつた。又別の方法では、DC―
DCコンバータにより所望の電圧を得る方法があ
るが、パワーロスおよび構成が複雑になる等の欠
点があつた。 Formed in semiconductor integrated circuits (IC), etc.
To control the gate of a MOSFET, typically 5
A voltage around [V] is required. Therefore, the light control IC
When forming an IC, a semiconductor light-receiving element (for example, a solar cell) that can output an output voltage of at least 5 [V] is required as an optically controlled power source for the IC. However, in conventional solar cells, the voltage that can be extracted from one [chip] is around 0.5 [V], so the above-mentioned light control IC is a hybrid system in which at least 10 [solar cell] chips are connected in series. However, there was a disadvantage that the external dimensions of the light control IC became large. In another method, DC-
There is a method of obtaining a desired voltage using a DC converter, but it has drawbacks such as power loss and a complicated configuration.
本発明は上記問題点に鑑み、１〔チツプ〕上に、
互に絶縁分離された複数個の半導体受光素子を形
成し、該受光素子を該チツプ上に於て金属配線層
により直列に接続し、モノリシツク構造で高出力
電圧が得られる半導体受光装置を提供する。 In view of the above problems, the present invention has the following features:
To provide a semiconductor light receiving device which can obtain a high output voltage with a monolithic structure by forming a plurality of semiconductor light receiving elements which are insulated and separated from each other, and connecting the light receiving elements in series through a metal wiring layer on the chip. .
即ち本発明は半導体受光装置に於て、半導体基
板面に設けられた複数の凹部内に、該凹部の内面
に形成されたマグネシア・スピネル（MgO・
Al2O3）層を介し互いに分離されて埋込まれた複
数の単結晶シリコン領域の各々に、該凹部の内面
に沿い且つ端部が該単結晶シリコン領域の表面に
露出して配設された高濃度一導電型領域と該高濃
度一導電型領域に囲まれた低濃度一導電型領域及
び該低濃度一導電型領域内に形成された反対導電
型領域よりなる半導体受光素子が形成され、該複
数の半導体受光素子が該基板上に於て金属配線に
より直列もしくは直並列に接続されてなることを
特徴とする。 That is, the present invention provides a semiconductor light receiving device in which magnesia spinel (MgO.
In each of the plurality of single-crystal silicon regions that are buried and separated from each other via an Al 2 O 3 ) layer, a plurality of single-crystal silicon regions are provided along the inner surface of the recess and with the end portions exposed on the surface of the single-crystal silicon region. A semiconductor light-receiving element is formed, which includes a highly-concentrated one-conductivity type region, a low-concentration one-conductivity type region surrounded by the high-concentration one-conductivity type region, and an opposite conductivity type region formed within the low-concentration one-conductivity type region. , the plurality of semiconductor light-receiving elements are connected in series or in series and parallel on the substrate by metal wiring.
以下本発明を、第１図に示す一実施例に於ける
構造断面図、第２図ａ乃至ｆに示す同実施例に於
ける製造工程断面図、第３図に示す一適用例の構
造断面図を用いて詳細に説明する。 The present invention will be described below with reference to a structural cross-sectional view of an embodiment shown in FIG. 1, a manufacturing process cross-sectional view of the same embodiment shown in FIGS. This will be explained in detail using figures.
本発明の構造を有する半導体受光装置は、例え
ば第１図に示すように、該半導体受光装置と並設
される半導体素子に適した所望の導電型を有する
シリコン（Si）基板１の主面に、半導体受光装置
の電流容量を考慮した所望の大きさを有する深さ
数〔μm〕〜数10〔μm〕程度の複数個の凹部２が
設けられており、該凹部２の内面には例えば１
〔μm〕程度の厚さを有する単結晶マグネシア・ス
ピネル（MgO・Al2O3）層３が形成されている。
そして該MgO・Al2O3層３に覆われた複数個の凹
部２内にはMgO・Al2O3層３に接する領域が、数
〔μm〕程度の厚さを有する高不純物濃度のN+型
シリコン（Si）エピタキシヤル層４で囲まれ該凹
部２を充たすように形成された数〔μm〕〜数10
〔μm〕程度の厚さを有する低不純物濃度のＮ型Si
エピタキシヤル領域５と、該Ｎ型Siエピタキシヤ
ル領域５表面に形成された例えば1000〔Å〕程度
の深さを有するＰ型拡散領域６とからなる太陽電
池７が形成されており、これら複数個の太陽電池
７が該基板上に形成された二酸化シリコン
（SiO2）等からなる絶縁膜８上に形成されたアル
ミニウム（Al）等の金属配線層９によりコンタ
クト窓１０を介して直列に接続されてなつてい
る。 For example, as shown in FIG. 1, the semiconductor photodetector having the structure of the present invention has a main surface of a silicon (Si) substrate 1 having a desired conductivity type suitable for a semiconductor element arranged in parallel with the semiconductor photodetector. A plurality of recesses 2 having a depth of several [μm] to several tens [μm] and having a desired size in consideration of the current capacity of the semiconductor photodetector are provided on the inner surface of the recess 2, for example.
A single crystal magnesia spinel (MgO.Al 2 O 3 ) layer 3 having a thickness of about [μm] is formed.
In the plurality of recesses 2 covered with the MgO.Al 2 O 3 layer 3, a region in contact with the MgO.Al 2 O 3 layer 3 is filled with highly impurity-concentrated N having a thickness of several μm. Number [μm] to number 10 surrounded by + type silicon (Si) epitaxial layer 4 and formed to fill the recess 2
Low impurity concentration N-type Si with a thickness of about [μm]
A solar cell 7 is formed of an epitaxial region 5 and a P-type diffusion region 6 formed on the surface of the N-type Si epitaxial region 5 and having a depth of, for example, about 1000 Å. solar cells 7 are connected in series through a contact window 10 by a metal wiring layer 9 made of aluminum (Al) or the like formed on an insulating film 8 made of silicon dioxide (SiO 2 ) or the like formed on the substrate. It's bright.
なお、太陽電池７が形成される低不純物濃度の
Ｎ型Siエピタキシヤル領域５の周囲を、端部が上
面に露出した高不純物濃度のN+型Siエピタキシ
ヤル層４で囲んだのは、該太陽電池７の内部抵抗
を減少させると同時に、Ｎ型領域に対してオーミ
ツク性が優れ且つ低コンタクト抵抗を有する配線
接続を可能にして該太陽電池７の実効的な光電変
換効率を高めるためである。 The reason why the N type Si epitaxial region 5 with a low impurity concentration, in which the solar cell 7 is formed, is surrounded by the N + type Si epitaxial layer 4 with a high impurity concentration and whose end portions are exposed on the upper surface is that This is to reduce the internal resistance of the solar cell 7, and at the same time, to enable wiring connection with excellent ohmic properties and low contact resistance to the N-type region, thereby increasing the effective photoelectric conversion efficiency of the solar cell 7. .
上記実施例の構造を有する太陽電池は次のよう
な方法によつて形成される。即ち第２図ａに示す
ように先ず該太陽電池と並設される例えばＰチヤ
ネルMOSFETを形成するに適したＮ型Si基板
１′の主面に、水酸化ナトリウム（NaOH）等か
らなる異方性エツチング液を用いて数〔μm〕〜
数10〔μm〕程度の所望の深さを有する所望の大き
さの複数個の凹部２を形成する。次いで通常の
MgO・Al2O3の気相エピタキシヤル成長（VPE）
法を用いて第２図ｂに示すように前記基板上に１
〔μm〕前後の厚さを有する単結晶MgO・Al2O3層
３を形成する。次いで通常のSiのVPE法を用い
て第２図ｃに示すように例えば1018〜1019〔atm／
cm3）程度の高りん（或るいは砒素）濃度を有する
数〔μm〕程度の厚さを有するN+型Siエピタキシ
ヤル層４及び前記凹部２を完全に埋める厚さを有
する例えば1014〜1017〔atm／cm3〕程度の低りん
（或るいは砒素）濃度のＮ型Siエピタキシヤル層
５′を形成する。なお単結晶MgO・Al2O3層上に
は該エピタキシヤル成長に於て単結晶Si層が成長
する。 The solar cell having the structure of the above embodiment is formed by the following method. That is, as shown in FIG. 2a, an anisotropic film made of sodium hydroxide (NaOH) or the like is first applied to the main surface of an N-type Si substrate 1' suitable for forming, for example, a P-channel MOSFET, which is installed in parallel with the solar cell. Several [μm] ~ using etching solution
A plurality of recesses 2 of a desired size and a desired depth of approximately several tens of micrometers are formed. then normal
Vapor phase epitaxial growth (VPE) of MgO・Al 2 O 3
1 on the substrate as shown in FIG.
A single crystal MgO.Al 2 O 3 layer 3 having a thickness of about [μm] is formed. Next, as shown in Fig. 2c, using the usual Si VPE method, for example, 10 18 to 10 19 [atm/
an N + type Si epitaxial layer 4 having a thickness of several [μm] and having a high phosphorus (or arsenic) concentration of the order of cm 3 ) and a thickness of, for example, 10 14 to 10 14 cm, to completely fill the recess 2; An N-type Si epitaxial layer 5' having a low phosphorus (or arsenic) concentration of about 10 17 [atm/cm 3 ] is formed. Note that a single crystal Si layer is grown on the single crystal MgO.Al 2 O 3 layer during the epitaxial growth.
次いで通常用いられるケミカル・ポリツシング
法により該基板面の研摩を行い第２図ｄに示すよ
うにＮ型Si基板１′面を表出せしめ、該基板面に
MgO・Al2O3層３により絶縁分離された複数個の
周囲がN+型Siエピタキシヤル層４で囲まれたＮ
型Siエピタキシヤル領域５を形成する。次いで第
２図ｅに示すように該基板上に形成した熱酸化膜
１１等をマスクとして通常のガス拡散法により硼
素等のＰ型不純物の選択拡散を行つて、前記Ｎ型
Siエピタキシヤル領域５の表面に所望の大きさを
有し、1020〜1021〔atm／cm3〕程度の硼素濃度を有
する数1000〔Å〕以下程度の浅いP+型拡散領域６
を形成する。なお太陽電池７は該P+型拡散領域
６と前記Ｎ型Siエピタキシヤル領域５の接合部に
形成される。次いで第２図ｆに示すように前記
P+型拡散領域６の形成が終つた基板上に形成さ
れている熱酸化膜１１等からなる絶縁膜８に通常
の方法を用いて該基板面に形成されている複数個
のP+型拡散領域６及びN+型Siエピタキシヤル層
４の一部を表出するコンタクト窓１０を形成した
後、通常の配線形成方法を用いて、該絶縁膜８上
に前記コンタクト窓１０を介して複数個の太陽電
池７を直列に接続するAl等の金属配線層９を形
成する。 Next, the substrate surface is polished by a commonly used chemical polishing method to expose the N-type Si substrate 1' surface as shown in FIG. 2d.
A plurality of N layers insulated by MgO・Al 2 O 3 layers 3 are surrounded by an N + type Si epitaxial layer 4.
A type Si epitaxial region 5 is formed. Next, as shown in FIG. 2e, using the thermal oxide film 11 formed on the substrate as a mask, a P-type impurity such as boron is selectively diffused by an ordinary gas diffusion method, and the N-type impurity is selectively diffused.
A shallow P + -type diffusion region 6 having a desired size on the surface of the Si epitaxial region 5 and having a boron concentration of about 10 20 to 10 21 [atm/cm 3 ] and about several thousand Å or less.
form. Note that the solar cell 7 is formed at the junction between the P + -type diffusion region 6 and the N-type Si epitaxial region 5 . Then, as shown in FIG.
A plurality of P + type diffusions formed on the substrate surface using a normal method are applied to an insulating film 8 made of a thermal oxide film 11 etc. formed on the substrate on which the P + type diffusion region 6 has been formed. After forming a contact window 10 exposing the region 6 and a part of the N + type Si epitaxial layer 4, a plurality of contact windows 10 are formed on the insulating film 8 via the contact window 10 using a normal wiring forming method. A metal wiring layer 9 made of Al or the like is formed to connect the solar cells 7 in series.
上記実施例から明らかなように本発明の構造を
有する半導体受光装置に於ては半導体基板の凹部
内にそれぞれが基板と絶縁分離された状態で形成
され、且つ実効的な光電変換効率が高められた複
数個の太陽電池が該基板上で直列に接続されてお
り、高出力電圧が提供されるので、第３図に示す
適用例のように同一Ｎ型Si基板１′上にＰチヤネ
ルMOS・FET１５を形成し、該MOS・FET１
５のゲート電極１６と半導体受光装置の所望の出
力端子１７とを、基板上に於て金属配線層９等を
用いて直接接続することにより、従来のハイブリ
ツド構造に比べて著しく小型化されたモノリシツ
クの光制御ICを形成することができる。なお第
３図に於いて３はMgO・Al2O3層、４はN+型Si
エピタキシヤル層、５はＮ型Siエピタキシヤル領
域、６はＰ型拡散領域、７は太陽電池、８は絶縁
膜、１８はＰ型ソース・ドレイン領域、１９はソ
ース・ドレイン電極を表わす。又本発明の受光装
置は電流容量を増すために直並列接続にする場合
もある。 As is clear from the above embodiments, in the semiconductor photodetector having the structure of the present invention, each of the photodetectors is formed in the recess of the semiconductor substrate insulated and separated from the substrate, and the effective photoelectric conversion efficiency is increased. A plurality of solar cells are connected in series on the substrate, and a high output voltage is provided. Therefore, as in the application example shown in FIG. FET15 is formed, and the MOS/FET1
By directly connecting the gate electrode 16 of No. 5 and the desired output terminal 17 of the semiconductor photodetector on the substrate using a metal wiring layer 9, etc., a monolithic structure that is significantly smaller than the conventional hybrid structure can be realized. can be used to form optical control ICs. In Fig. 3, 3 is MgO・Al 2 O 3 layer, 4 is N + type Si
In the epitaxial layer, 5 is an N-type Si epitaxial region, 6 is a P-type diffusion region, 7 is a solar cell, 8 is an insulating film, 18 is a P-type source/drain region, and 19 is a source/drain electrode. Further, the light receiving device of the present invention may be connected in series and parallel to each other in order to increase the current capacity.
以上説明したように本発明によれば、高光電変
換効率を有するモノリシツク構造の高出力電圧半
導体受光装置が提供される。従つて光制御IC等
の制御用電源を大幅に縮小することができるので
これら半導体ICの小型化が図れる。 As described above, according to the present invention, a monolithic structure high output voltage semiconductor light receiving device having high photoelectric conversion efficiency is provided. Therefore, the control power supply for optical control ICs and the like can be significantly reduced, so that the size of these semiconductor ICs can be reduced.
なお本発明の半導体受光装置は上記実施例と逆
の導電型で形成することもできる。 Note that the semiconductor light receiving device of the present invention can also be formed with a conductivity type opposite to that of the above embodiment.
第１図は本発明の一実施例に於ける構造断面
図、第２図ａ乃至ｆは同実施例に於ける製造工程
断面図、第３図は本発明の一適用例の構造断面図
である。
図に於て、１はシリコン基板、１′はＮ型シリ
コン基板、２は凹部、３はマグネシア・スピネル
層、４はN+型シリコン・エピタキシヤル層、５
はＮ型シリコン・エピタキシヤル領域、５′はＮ
型シリコン・エピタキシヤル層、６はP+型拡散
領域、７は太陽電池、８は絶縁膜、９は金属配線
層、１０はコンタクト窓、１１は熱酸化膜、１５
はＰチヤネルMOSFET、１６はゲート電極、１
７は出力端子、１８はＰ型ソース・ドレイン領
域、１９はソース・ドレイン電極を示す。
Fig. 1 is a structural sectional view of an embodiment of the present invention, Fig. 2 a to f are sectional views of the manufacturing process in the same embodiment, and Fig. 3 is a structural sectional view of an application example of the present invention. be. In the figure, 1 is a silicon substrate, 1' is an N-type silicon substrate, 2 is a recess, 3 is a magnesia spinel layer, 4 is an N + type silicon epitaxial layer, 5
is N type silicon epitaxial region, 5' is N
type silicon epitaxial layer, 6 is a P + type diffusion region, 7 is a solar cell, 8 is an insulating film, 9 is a metal wiring layer, 10 is a contact window, 11 is a thermal oxide film, 15
is a P-channel MOSFET, 16 is a gate electrode, 1
7 is an output terminal, 18 is a P-type source/drain region, and 19 is a source/drain electrode.
Claims (1)
ル（MgO・Al2O3）層を介し互いに分離されて埋
込まれた複数の単結晶シリコン領域の各々に、 該凹部の内面に沿い且つ端部が該単結晶シリコ
ン領域の表面に露出して配設された高濃度一導電
型領域と該高濃度一導電型領域に囲まれた低濃度
一導電型領域及び該低濃度一導電型領域内に形成
された反対導電型領域よりなる半導体受光素子が
形成され、 該複数の半導体受光素子が該基板上に於て金属
配線により直列もしくは直並列に接続されてなる
ことを特徴とする半導体受光装置。[Claims] 1. Embedded in a plurality of recesses provided on the surface of a semiconductor substrate, separated from each other via a magnesia spinel (MgO.Al 2 O 3 ) layer formed on the inner surface of the recesses. In each of the plurality of single-crystal silicon regions, a highly-concentrated one-conductivity type region is provided along the inner surface of the recess with an end portion exposed to the surface of the single-crystal silicon region; A semiconductor light-receiving element is formed of a surrounded low-concentration region of one conductivity type and an opposite conductivity-type region formed within the low-concentration region of one conductivity type, and the plurality of semiconductor light-receiving elements are connected to metal wiring on the substrate. A semiconductor light receiving device characterized by being connected in series or in series and parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55177830A JPS57100761A (en) | 1980-12-16 | 1980-12-16 | Semiconductor light sensitive device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55177830A JPS57100761A (en) | 1980-12-16 | 1980-12-16 | Semiconductor light sensitive device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57100761A JPS57100761A (en) | 1982-06-23 |
| JPS6322474B2 true JPS6322474B2 (en) | 1988-05-12 |
Family
ID=16037848
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55177830A Granted JPS57100761A (en) | 1980-12-16 | 1980-12-16 | Semiconductor light sensitive device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57100761A (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5922360A (en) * | 1982-07-28 | 1984-02-04 | Matsushita Electric Works Ltd | Optical input mos type transistor |
| JPS5936263U (en) * | 1982-08-30 | 1984-03-07 | 日本電気株式会社 | semiconductor equipment |
| JPS6216568A (en) * | 1985-07-15 | 1987-01-24 | Sharp Corp | Light-receiving element incorporated in circuit |
| US5360987A (en) * | 1993-11-17 | 1994-11-01 | At&T Bell Laboratories | Semiconductor photodiode device with isolation region |
| US6228750B1 (en) | 1994-12-30 | 2001-05-08 | Lucent Technologies | Method of doping a semiconductor surface |
| US6936495B1 (en) | 2002-01-09 | 2005-08-30 | Bridge Semiconductor Corporation | Method of making an optoelectronic semiconductor package device |
| US7190060B1 (en) | 2002-01-09 | 2007-03-13 | Bridge Semiconductor Corporation | Three-dimensional stacked semiconductor package device with bent and flat leads and method of making same |
| US6987034B1 (en) | 2002-01-09 | 2006-01-17 | Bridge Semiconductor Corporation | Method of making a semiconductor package device that includes singulating and trimming a lead |
| US6891276B1 (en) | 2002-01-09 | 2005-05-10 | Bridge Semiconductor Corporation | Semiconductor package device |
| US8410568B2 (en) * | 2008-08-29 | 2013-04-02 | Tau-Metrix, Inc. | Integrated photodiode for semiconductor substrates |
| JP5780629B2 (en) * | 2010-12-15 | 2015-09-16 | 学校法人 東洋大学 | Semiconductor device |
-
1980
- 1980-12-16 JP JP55177830A patent/JPS57100761A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57100761A (en) | 1982-06-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6458619B1 (en) | Process for producing an isolated planar high speed pin photodiode with improved capacitance | |
| US4740826A (en) | Vertical inverter | |
| Nakagawa et al. | Breakdown voltage enhancement for devices on thin silicon layer/silicon dioxide film | |
| US6100570A (en) | Semiconductor device having a semiconductor film of low oxygen concentration | |
| US5053083A (en) | Bilevel contact solar cells | |
| US6027956A (en) | Process for producing planar dielectrically isolated high speed pin photodiode | |
| US4847210A (en) | Integrated pin photo-detector method | |
| US4926231A (en) | Integrated pin photo-detector | |
| JPS6159853A (en) | Structure of silicon crystalline body | |
| GB2148591A (en) | Semiconductor device isolation grooves | |
| US6303967B1 (en) | Process for producing an isolated planar high speed pin photodiode | |
| JPS6322474B2 (en) | ||
| JPS5951743B2 (en) | semiconductor integrated device | |
| US4846896A (en) | Solar cell with integral reverse voltage protection diode | |
| JPH04225285A (en) | Silicon photodiode for monolithic integrated circuit use and its manufacture | |
| US8828781B1 (en) | Method for producing photovoltaic device isolated by porous silicon | |
| US4788158A (en) | Method of making vertical inverter | |
| JP2001085731A (en) | Photoelectric voltage generator | |
| US8829332B1 (en) | Photovoltaic device formed on porous silicon isolation | |
| JP3103737B2 (en) | Solar cell element | |
| CN114566557B (en) | Avalanche photodetector and preparation method thereof | |
| JPH10209411A (en) | Semiconductor device and manufacture thereof | |
| JPH07142757A (en) | Manufacture of semiconductor light sensor | |
| JPH02377A (en) | Photoelectric converting device | |
| JPH01205565A (en) | Optical semiconductor device and its manufacture |