JPH10209411A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the light-receiving sensitivity of a photodiode, to lessen the parasitic capacitance of the photodiode to enhance the frequency characteristics of the photodiode and at the same time, to lessen the parasitic capacitance between the collector of a bipolar transistor and a substrate without weakening the resistance of a parasitic thyristor to a latchup in a semiconductor device of a structure, wherein an extremely lightly doped semiconductor layer is provided between P-type and N-type semiconductor regions and the device is provided with a light-receiving element and the bipolar transistor. SOLUTION: An extremely lightly doped semiconductor layer consists of first layers 13 formed on the surface of a P<+> substrate 11 and second layers 15 to come into contact with an N-type semiconductor region 22 formed on the layers 13. An N<+> semiconductor region formed selectively in the surface sides of extremely lightly doped semiconductor regions 13, which have the same conductivity type as that of the layers 13 and have roughly the same depth as that of the layers 13, is used as a collector side region and a bipolar transistor provided with a base and an emitter is provided on the upper side of the collector side region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having at least a light-receiving element having a first or second conductive type ultra-low concentration semiconductor layer between a first conductive type semiconductor and a second conductive type semiconductor. The present invention also relates to a semiconductor device having a bipolar transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art A semiconductor device in which a photodiode as a light receiving element and a bipolar transistor are mounted on one chip is used as an optical sensor for converting an optical signal into an electric signal. Used for signal transmission.

FIG. 5 is a sectional view showing a conventional example of such a semiconductor device. In the drawing, reference numeral 101 denotes a photodiode formation region, which includes an anode common type photodiode formation region 102 and a cathode common photodiode formation region 103. 104 is a bipolar transistor formation region. A P-type semiconductor substrate 111 has an impurity concentration of, for example, about 10 ¹⁵ / cm ³ .

In the anode common type photodiode formation region 102, the P ⁺ type buried layer 112 formed on the semiconductor substrate 111 is used as a common anode, and the N ⁻ type epitaxial layers 115, 115 on the buried layer 112 are formed. To P
Two photodiodes are formed, which are low-concentration regions corresponding to the I (intrinsic) region of the IN photodiode and have the N ⁺ type diffusion layers 122 formed on the regions 115 as cathodes.

Reference numeral 116 denotes a P ⁺ -type isolation layer formed on the surface of the epitaxial layer 115. The isolation layer 116 (and the selective oxide film 130) separates two photodiodes having a common anode. Also, the anode common photodiode formation region 1
02 and the other regions 103 and 104 are also separated by an isolation layer 116. Reference numeral 121 denotes a P ⁺ -type diffusion layer formed on the surface of the isolation layer 116, and a common anode is extracted through the P ⁺ -type diffusion layer 121. 126d is a common anode lead-out line, and 126c and 126c are cathode lead-out lines, respectively. This photodiode has an anode connected to the P-type semiconductor substrate 111 and has a common anode configuration. The cathode common type photodiode forming region 103, the N ⁺ -type buried layer 114 formed on the P-type semiconductor substrate 111 and the cathode, the N ⁺ -type buried layer 1
14 as a low-concentration region corresponding to the I (intrinsic) region in the PIN photodiode,
A photodiode having the P ⁺ type diffusion layer 121 as an anode is formed. Reference numeral 117 denotes an N ⁺ -type plug-in layer for taking out a cathode electrode, which is connected to a cathode take-out region 122 formed of an N ⁺ -type diffusion layer. 126a is a cathode lead-out line, and 126b is a cathode lead-out line. In this photodiode, the cathode is circuit-connected to the power supply terminal (Vcc) to form a cathode common configuration.

In the bipolar transistor formation region 104, an N ⁻ type epitaxial layer 115 formed on an N ⁺ type 114 on a P type semiconductor substrate 111 is used as a collector,
A bipolar transistor having a P-type region formed on the surface thereof as a base and a polysilicon layer as an emitter is formed. Reference numeral 120 denotes a base extraction part, 126e denotes a base extraction wiring, 126f denotes an emitter extraction wiring, 117 denotes an N ⁺ type collector extraction plug-in layer, 122 denotes a collector extraction P ⁺ diffusion layer, and 126g denotes a collector extraction wiring.

Reference numeral 125 is an interlayer insulating film, 127 is an insulating film (SiO ₂ film) covering the entire surface of the substrate, and 128 is a second-layer wiring film, which shields portions other than the light receiving surface of the photodiode from light. Form. 129 is an overpassivation film made of SiN.

[0008]

The semiconductor device shown in FIG. 5 has the following problems. First, there is a problem that it is difficult to increase the sensitivity of the photodiode. More specifically, the low-concentration epitaxial layer 115 shown in FIG. 5 corresponds to the I region of the PIN photodiode and is a region where photoelectric conversion can be effectively performed, but has a thickness of 1 μm or less. That is, in order to form a bipolar transistor having frequency characteristics of several tens of GHz, the thickness of the epitaxial layer 115 must be 1 μm.
m or less, and the resistivity needs to be about 1 Ω · cm, and if the thickness is more than that, the frequency characteristics deteriorate.

On the other hand, carriers (electrons and holes) generated at a depth twice as long as the light absorption length must also contribute to light reception in order to sufficiently secure the light receiving sensitivity of the photodiode. The light absorption length is generally much larger than 1 μm.

This is because the light used for the optical fiber depends on the constituent material of the optical fiber, and a light having a wavelength with the least light loss is selected.
5 μm, light having a wavelength of 0.7 to 0.8 μm for PCF (silica core plastic clad fiber), 0.57 to 0.67 μm for plastic fiber
Is selected.

A plastic fiber is used for light having the shortest wavelength as an optical fiber, and its shortest wavelength is 0.57 μm (570 nm). For example, the light absorption length is calculated as follows. Since the light absorption coefficient (α) is 6.2 × 10 ³ cm ⁻¹ , the light intensity is 1 / e of the silicon surface light intensity (natural logarithm = 2.7182).
81828), that is, the light absorption length (= 1 / α) from the silicon surface is 1.6 μm. In order to sufficiently increase the light receiving sensitivity, it is preferable to detect a carrier having a depth twice as long as the light absorption length as a photocurrent. Therefore, in this case, the carrier at a depth of about 3.2 is detected. Although it is necessary to enable detection, the epitaxial layer 115 is thinner than 1 μm as described above.

[0012] Carriers generated at a position deeper than the epitaxial layer 115 have a high impurity concentration in the buried layer 112 where the carriers are generated (P ⁺ type).
Therefore, the diffusion length is short and recombine before reaching the depletion layer and disappear, and do not contribute to the photocurrent. As a result, sufficient light receiving sensitivity cannot be secured.

A second problem of the conventional semiconductor device shown in FIG. 5 is that although the epitaxial layer 115 has a resistivity of about 1 .mu.m or less, its resistivity is about 1 .OMEGA..cm. Depending on the applied reverse voltage of about 1.5 V, the entire epitaxial layer is not depleted, and the width of the depletion layer is narrow. This is because if the width of the depletion layer is small, the parasitic capacitance of the photodiode is large, and it is difficult to improve the frequency characteristics of the photodiode. Specifically, the frequency characteristic required for a photodiode for an optical disk is about several tens of MHz, but the frequency characteristic required for a photodiode for an optical fiber link is very high, from several hundred MHz to several tens GHz or more. high. Then, the conventional photodiode and bipolar transistor mixed type semiconductor device shown in FIG. 5 can satisfy the demand for an optical disk, but cannot meet the demand for an optical fiber link.

The third problem of the conventional semiconductor device shown in FIG. 5 is that the parasitic capacitance between the N ⁺ type buried layer 114 and the semiconductor substrate 111 is reduced in order to increase the speed of the bipolar transistor. If the impurity concentration of the substrate 111 is reduced as much as possible, the resistance of the parasitic thyristor to latch-up is reduced.

That is, a junction capacitance is parasitic between the N ⁺ type buried layer 114 and the substrate 111, and the higher the parasitic capacitance, the worse the speed of the bipolar transistor. Therefore, in order to increase the speed of the bipolar transistor, it is necessary to reduce the parasitic capacitance thereof. For this purpose, it is effective to lower the impurity concentration of the semiconductor substrate 1. This is because the width of the depletion layer generated by the reverse voltage applied to the junction capacitance can be increased.

However, when doing so, the substrate 111,
The N ⁺ type buried layer 114 and the substrate 111 and the N ⁺ type buried layer 114 and the substrate 111 and another N ⁺
Latch-up of a parasitic thyristor caused by the mold buried layer 114 is likely to occur. Because the substrate 11
If the impurity concentration of 1 is reduced, the parasitic resistance increases, the potential difference generated by the parasitic resistance in the same substrate 111 increases, and the parasitic thyristor is turned on by the potential difference, that is, latch-up easily occurs. .

Therefore, when the impurity concentration of the semiconductor substrate 111 is increased in order to increase the speed of the bipolar transistor, the latch-up resistance of the parasitic thyristor is reduced. That is, the parasitic capacitance is reduced and the latch-up resistance is increased. There was a problem that it would be a trade-off.

SUMMARY OF THE INVENTION The present invention has been made to solve such problems, and a first or second conductive type ultra-low concentration semiconductor layer is provided between a first conductive type semiconductor and a second conductive type semiconductor. Factors that increase the light receiving sensitivity of a photodiode of a semiconductor device provided with at least a light receiving element having a bipolar transistor, or further reduce the parasitic capacitance of the photodiode to increase its frequency characteristic, and lower the frequency characteristic of the bipolar transistor. It is an object of the present invention to reduce the parasitic capacitance between the collector and the substrate without reducing the latch-up resistance of the parasitic thyristor.

[0019]

According to a first aspect of the present invention, in the semiconductor device of the first aspect, the first conductivity type semiconductor is formed of a first conductivity type semiconductor substrate having at least a high concentration on the surface side, and the extremely low concentration semiconductor layer is formed of the first conductivity type semiconductor layer. A first layer formed on the surface of the high-concentration type semiconductor substrate; and a second layer formed on the first layer and in contact with the second conductivity type semiconductor.

Therefore, according to the semiconductor device of the first aspect,
By forming the first layer as a thick layer, the extremely low-concentration semiconductor layer corresponding to the I region in the PIN photodiode can be made considerably thick. The impurity concentration can be made such that the layer is completely depleted by the reverse voltage applied for photodetection, so that the depth is about twice as long as the absorption length of the silicon semiconductor for the received light. The generated carriers can also be made to become photocurrents. Accordingly, the light receiving sensitivity of the photodiode can be increased, and the parasitic capacitance of the photodiode can be reduced, and the frequency characteristics of the photodiode can be improved.

According to a fourth aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the second conductive type high concentration semiconductor region selectively formed on the surface side of the first layer of the ultra low concentration semiconductor layer is provided. A bipolar transistor having a collector side region and a base and an emitter provided above the collector side region is provided.

Therefore, according to the semiconductor device of the fourth aspect,
The first layer has a thickness preferable for obtaining the required characteristics as a photodiode, and the preferred concentration is obtained by setting the impurity concentration to a preferable level, and the second layer has a thickness preferable for obtaining the characteristics required for a bipolar transistor. , A preferable bipolar transistor can be obtained. Since an extremely low-concentration semiconductor layer exists between the first-conductivity-type high-concentration semiconductor substrate and the second-conductivity-type high-concentration semiconductor region, a parasitic layer exists between the substrate and the second-conductivity-type high-concentration semiconductor region. In this case, the capacity of the bipolar transistor can be reduced, and the frequency characteristics of the bipolar transistor can be improved. Since the concentration of at least the surface of the semiconductor substrate is increased, the parasitic resistance on the surface of the substrate can be reduced, and the resistance of the parasitic thyristor to latch-up can be increased. Even if the concentration of the semiconductor substrate is increased, the first layer of the extremely low concentration semiconductor layer is interposed between the semiconductor substrate and the high concentration semiconductor region forming the collector of the bipolar transistor, so that the parasitic capacitance therebetween does not increase. Accordingly, the conventional dilemma of reducing the parasitic capacitance and increasing the latch-up resistance in a conventional manner is a trade-off.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth aspect, a step of depositing a first conductive type semiconductor layer on a first conductive type semiconductor substrate is provided. Selectively etching a portion of the one-conductivity-type semiconductor layer other than the portion to be an element isolation region; and forming the first or second conductivity-type extremely-low-concentration semiconductor layer forming the first layer of the extremely-low-concentration semiconductor layer. Depositing the first conductivity type semiconductor layer on the semiconductor substrate in a state where the first conductivity type semiconductor layer is selectively formed; and selectively removing a portion of the ultra-low concentration semiconductor layer higher than the first conductivity type semiconductor layer surface and smoothing the portion. Making the ultra-low-concentration semiconductor layer separated by the first conductivity-type semiconductor layer, and selectively introducing a second-conductivity-type impurity into the ultra-low-concentration semiconductor layer. Forming a two-conductivity-type semiconductor layer; Depositing a very low concentration semiconductor layer forming the second layer of low-concentration semiconductor layer, and having a.

Therefore, according to the method of manufacturing a semiconductor device of the fifth aspect, it is possible to obtain desired photodiode characteristics of the second conductivity type ultra-low concentration semiconductor layer which forms the first layer of the ultra-low concentration semiconductor layer. Such thickness and low impurity concentration can be achieved. In addition, the first layer of the extremely low-concentration semiconductor layer has a second layer.
If the bipolar transistor is formed in the region where the second conductivity type semiconductor layer is formed by introducing the conductivity type impurity, the extremely low concentration semiconductor layer forming the second layer can obtain desired bipolar transistor characteristics. By setting the thickness and impurity concentration as small as possible, a bipolar transistor having desired characteristics can be obtained. That is, it is possible to satisfy the demands on the characteristics of both the photodiode and the bipolar transistor.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

FIG. 1 is a sectional view showing a first embodiment of the semiconductor device of the present invention. In the drawing, reference numeral 1 denotes a photodiode formation region, which is composed of an anode common type photodiode formation region 2 and a cathode common photodiode formation region 3. 2a is one diode in the area 2 and 2b is another diode. Reference numeral 4 denotes a bipolar transistor formation region. Reference numeral 11 denotes a P ⁺ type semiconductor substrate having an impurity concentration of, for example, about 10 ¹⁸ to 10 ¹⁹ / cm ³ . The first feature of this embodiment is that the semiconductor substrate 11 having a high concentration is used as the semiconductor substrate.

In the anode common type photodiode formation region 2, the P ⁺ type semiconductor substrate 11 is used as a common anode, and the ultra-low concentration (N
^- corresponds to the first layer of Epitashikisharu layer 13 (patent referred to in the claims extremely low concentration semiconductor layer of the mold) .P ^-
It may be a type or an N ^- type. In this example, it is a P ^- type. ) And the ultra-low concentration epitaxial layer 15 on said layers 13, 13;
15 (corresponding to the second layer of the extremely low-concentration semiconductor layer referred to in the claims) corresponds to I in the PIN photodiode.
N-type semiconductor layer 2 formed on the surface of epitaxial layers 15 and 15 as an extremely low-concentration semiconductor layer corresponding to the region.
Photodiodes 2a and 2b using cathodes 2 and 22 as cathodes
Are formed.

Numeral 12 is a P-type epitaxial layer, 16 is a P-type isolation layer, and the anode is from the semiconductor substrate 11 to the P-type epitaxial layer 12 and the P-type isolation layer 1.
6 and via the semiconductor layer 21 for extracting a P-type anode formed on the surface of the layer 16. 26d is an anode lead-out wiring, and 26c and 26c are cathode lead-out wirings. Incidentally, reference numeral 19 denotes a selective oxide film. This photodiode has an anode formed of a P ⁺ type semiconductor substrate 11 and has an anode common configuration through the substrate 11.

In the cathode common type photodiode formation region 103, the N ⁺ type buried layer 14 selectively formed on the ultra low concentration epitaxial layer 13 on the P ⁺ type semiconductor substrate 11 is used as an anode, Is formed as a low-concentration region corresponding to an I (intrinsic) region of the PIN photodiode, and a P ⁺ -type diffusion layer 21 formed on the surface of the epitaxial layer 15 as a cathode. Reference numeral 17 denotes an N ⁺ -type plug-in layer for taking out a cathode electrode, and a cathode take-out region 22 comprising the N ⁺ -type buried layer 14 and the N ⁺ -type diffusion layer.
Connect between 26a is a cathode extraction wiring, 26b
Is an anode extraction wiring. In this photodiode, the cathode is circuit-connected to the power supply terminal (Vcc) to form a cathode common configuration.

The P-type epitaxial layer 12 and the P-type isolation layer 16 perform an element isolation function. That is, by these, the two photodiodes 2a and 2b having a common anode are separated from each other, and the anode common photodiode forming region 2 and the other regions 3 and 4 are separated from each other.

In the bipolar transistor formation region 4,
N ⁺ -type buried layer 14 formed on ultra-low-concentration epitaxial layer 13 formed on P ⁺ -type semiconductor substrate 11 (corresponding to the first layer of ultra-low-concentration semiconductor layer in claims), and N ⁺ -type buried layer 14 A bipolar transistor is formed in which the upper N ^- type well is used as a collector, a P-type region formed on the surface thereof is used as a base, and a polysilicon layer 24 is used as an emitter. Reference numeral 20 denotes a base extraction part, 26e denotes a base extraction wiring, 26f denotes an emitter extraction wiring, and 17 denotes N
^A plug-in layer for taking out the ⁺ type collector, 22 is a P ⁺ type diffusion layer for taking out the collector, and 26 g is a wiring for taking out the collector.

Reference numeral 25 denotes an interlayer insulating film, 27 denotes an insulating film (SiO ₂ film) covering the entire surface of the substrate, and 28 denotes a second-layer wiring film, which shields portions other than the light receiving surface of the photodiode from light. Form. 29 is an overpassivation film made of SiN.

According to the semiconductor device shown in FIG. 1, for the photodiode of the anode common type, first,
This has the advantage that the light receiving sensitivity can be increased. That is, the I region in the PIN photodiode, that is, the region where the carrier recombination is small and the photoelectric conversion can be performed effectively is configured by the extremely low-concentration semiconductor layer including the first layer 13 and the second layer 15. For example, a thickness of 15 μm
It is possible to make it considerably thicker. Therefore, carriers generated at a depth of at least twice the absorption length of the silicon semiconductor with respect to the received light can also be used as a photocurrent. Accordingly, the light receiving sensitivity of the photodiode can be increased.

Second, since the first layer 13 and the second layer 15 have extremely low concentrations, the reverse voltage (for example, 1) applied to the photodiode at the time of light reception even if the sum of the thicknesses is extremely large. .5 V), the depletion layer has a width covering the entire extremely low concentration semiconductor layer including the first layer 13 and the second layer 15, and the width of the depletion layer becomes equal to the width of the extremely low concentration semiconductor layer. Therefore, the parasitic capacitance (depletion layer) of the photodiode
Can be made extremely small, and thus the frequency characteristics of the photodiode can be enhanced.

According to the semiconductor device shown in FIG. 1, the bipolar transistor has an advantage that the parasitic capacitance between the collector and the substrate can be reduced without lowering the latch-up resistance. That is, the epitaxial layer 13 corresponding to the first layer of the extremely low concentration semiconductor layer is interposed between the N ⁺ type buried layer 14 corresponding to the collector side of the bipolar transistor and the P ⁺ type semiconductor substrate 11 according to the present embodiment. And therefore, in the meantime (buried layer 1
4. Between the substrates 11), the parasitic capacitance can be reduced. Conventionally, this parasitic capacitance could not be reduced unless the concentration of the substrate was reduced. However, according to the present embodiment, the presence of the extremely low concentration Even if the concentration is increased, the parasitic capacitance can be reduced. Therefore, it is possible to prevent a reduction in high-speed operation due to a parasitic capacitance between the bipolar transistor and the substrate.

Since the impurity concentration of the semiconductor substrate 11 is extremely high, the parasitic resistance in the substrate 11 can be reduced. Therefore, the potential difference generated in the substrate 11 can be reduced, and in turn, the turn-on of the parasitic thyristor, that is, the latch-up can be suppressed. Therefore, the parasitic capacitance can be reduced without lowering the latch-up resistance.

In the semiconductor device shown in FIG. 1, the extremely low-concentration semiconductor layer is composed of the first layer 13 and the second layer 15 because the second layer 15 is a main part of the bipolar transistor (most of the characteristics). The thickness of the first layer 13 is more than 10 μm, which is suitable for improving the light receiving sensitivity of the anode common type photodiode and reducing the parasitic capacitance (depletion layer capacitance). The thickness is set so that both the transistor and the photodiode can have required good characteristics.

FIGS. 2A to 2C and FIG. 3D,
2E is a cross-sectional view showing a characteristic portion of the method for manufacturing the semiconductor device shown in FIG. 1 in the order of steps (A) to (E).

(A) Boron, for example, 1 as a semiconductor substrate
A P ⁺ type silicon semiconductor substrate 11 containing about × 10 ¹⁸ / cm ³ is prepared, and a P type epitaxial layer (thickness 1
5 μm, resistivity 4 Ω · cm) 12 is grown, and then
The epitaxial layer 12 includes a separation portion between the bipolar transistors, a separation portion between the bipolar transistor and the photodiode, a separation portion between the photodiodes,
Selective etching is performed so as to remain only in a separation portion between the diodes in the common anode type photodiode. This selective etching is performed by applying a photoresist, patterning it by exposing and developing it,
Thereafter, the epitaxial layer 12 is etched by RIE (reactive ion etching) using the mask as a mask. FIG. 2A shows a state after the etching.

(B) Next, as shown in FIG. 2 (B), an epitaxial layer 13 to be the first layer of the extremely low-concentration semiconductor layer is entirely formed. Its thickness is, for example, 20 μm,
The resistivity is, for example, 400 Ω · cm.

(C) Next, by removing the epitaxial layer 13 by a CMP (Chemical Mechanical Polishing) method, as shown in FIG. 2C, the silicon surface is flattened.

(D) Next, 300 nm by a normal thermal oxidation method.
After forming a silicon oxide film having a film thickness of a suitable thickness, portions of the silicon oxide film corresponding to the bipolar transistor formation region 4 and the cathode common type photodiode formation region 3 are etched using hydrofluoric acid (HF) using the photoresist film as a mask. I do. Thereafter, the photoresist film is removed (for example, by using sulfuric acid / hydrogen peroxide).
The N ⁺ -type buried layer 14 is formed by diffusing antimony Sb into the semiconductor surface using the silicon oxide film as a mask by using a solid source of b ₂ O ₃ . The temperature of this heat treatment is, for example, 1200 ° C., and the processing time is, for example, 120 minutes.

Next, the thermal oxide film used as a mask is removed by using hydrofluoric acid HF, and thereafter, an epitaxial layer to be the second layer 15 of the ultra-low concentration semiconductor layer is entirely formed. The layer 15 has a thickness of, for example, 1 μm and a resistivity of, for example, 4 μm.
00 Ω · cm. FIG. 3D shows a state after the formation of the extremely low concentration epitaxial layer 15.

(E) Next, a thermal oxide film (not shown) having a thickness of about 50 nm is formed by thermally oxidizing the surface of the epitaxial layer 15, and thereafter, a P oxide film is formed in the element isolation region.
A mold isolation layer 16 is formed. For example, using a photoresist film as a mask, boron
This is performed by ion implantation at an energy of eV, for example, about 1 × 10 ¹⁵ / cm ² .

An N-type plug-in layer 17 is formed at the portion corresponding to the cathode extraction portion of the cathode common type photodiode and at the portion corresponding to the collector extraction portion of the bipolar transistor. This is done, for example, using a photoresist film as a mask, for example, phosphorus P, for example, 70 Ke.
This is performed by ion implantation at an energy of V, for example, about 5 × 10 ¹⁵ / cm ² . Further, the N-type well layer 18 is formed in the bipolar transistor,
It is formed by ion implantation at, for example, about 5 × 10 ¹² / cm ² with energy of KeV. Thereafter, a heat treatment for activating the ion-implanted boron B and phosphorus P is performed in a nitrogen gas N ₂ atmosphere at a temperature of 1100 ° C. for about 120 minutes. As a result, a P-type isolation layer 16, an N-type plug-in layer 17, and an N-type well layer 18 are formed. FIG. 3E shows a state after these layers 16, 17, and 18 are formed.

After that, the fabrication may be performed in the same process as the fabrication of a normal (double polysilicon structure) bipolar transistor. Incidentally, a method of manufacturing a bipolar transistor having a double polysilicon structure will be briefly described. After the step shown in FIG. 3E, a selective oxide film for element isolation (LOCOS) 19 is used as an oxide-resistant film as a mask. After the oxide film is formed by thermal oxidation and the oxide film in the region where the emitter / base of the transistor is to be formed is selectively removed, a polysilicon layer is formed by CVD, and a P-type impurity is introduced into the polysilicon layer. The silicon layer is etched leaving its base electrode formation portion 20 and a polysilicon resistance portion (not shown) forming, for example, an integrated circuit. Thereafter, a silicon oxide film is formed on the entire surface, a portion corresponding to a portion where the base of the silicon oxide film and the polysilicon layer is to be formed is removed, and a P-type impurity is introduced into the N-type well layer 18 through the removed portion. The base 23 is formed by the introduction.

Then, a silicon oxide film is formed on the entire surface, and a portion where an emitter is to be formed is opened by selective etching of the silicon oxide film. Next, an N-type polysilicon emitter 24 is formed by forming an N-type polysilicon layer and removing a portion of the polysilicon layer other than a portion to be an emitter. Then, a contact hole for making contact between the aluminum-based wiring and silicon is formed in a portion other than the N-type polysilicon emitter 24, and a titanium Ti film (thickness of, for example, 30 nm) for making ohmic contact with silicon is formed. A titanium oxynitride TiON film (thickness, for example, 70 nm), which is a refractory metal, is formed by sputtering, and an aluminum film (thickness, for example, 600 nm) containing 1% of Si is formed by wiring. Formed by sputtering, and then patterned by selective etching by RIE,
The aluminum wiring 26 of the layer is formed. Next, a silicon oxide film (thickness of, for example, 1 μm) 27 is used as an interlayer insulating film.
Is formed by, for example, plasma CVD, the surface of the oxide film 27 is flattened using SOG (spin-on-glass), and a silicon oxide film is deposited by plasma CVD.

Thereafter, a contact hole is formed in the silicon oxide film 27 by RIE, and a titanium film (thickness of, for example, 100 nm) and a second aluminum (Al containing 1% Si) film (thickness of, for example, 1000 nm) are formed. ) 28
Is formed by a sputtering method. Then, the aluminum film 28 is selectively etched including the titanium film (RIE).
By doing so, patterning is performed so that an opening is formed in the light receiving portion of the photodiode. Thereafter, as an overpassivation film, a silicon nitride film (thickness, for example, 7
00 nm) 29 is formed by plasma CVD, and the bonding pad portion of the film 29 is removed by etching by RIE.
Sintering is performed by heat treatment in a mixed gas of ₂ and 5% H ₂ ) for 30 minutes.

The method of manufacturing the semiconductor device shown in FIGS. 2 and 3 can be summarized as follows.
^A P-type epitaxial layer 12 for element isolation is formed on a ⁺ type semiconductor substrate 11 by an epitaxial growth method and a selective etching method, and then the first portion of the extremely low-concentration semiconductor layer is formed on other portions by an epitaxial growth method and a CMP method.
Is formed, and then a bipolar transistor transistor forming region 4 is formed.
In addition, an N ⁺ type buried layer 14 is formed in the cathode common type photodiode formation region 2 so that an appropriate gap is formed between the N ⁺ type buried layer 14 and the substrate 11.

Therefore, the parasitic capacitance between the N ⁺ type buried layer 14 and the P ⁺ type semiconductor substrate 11 can be reduced. What is important here is that the parasitic capacitance between the transistor and the substrate can be reduced even if the impurity concentration of the semiconductor substrate 11 is increased. Because the substrate 11
This is because the latch-up resistance can be increased by increasing the impurity concentration of the semiconductor device, so that the conventional problem that the reduction of the parasitic capacitance and the improvement of the latch-up resistance have a trade-off relationship can be solved.

Then, the first layer 13 of the extremely low concentration semiconductor layer
Can be set to a thickness and a concentration such that the light receiving sensitivity and the parasitic capacitance of the photodiode of the anode common type can be made favorable, and thus a photodiode having favorable characteristics can be obtained. Next, the present manufacturing method
After the formation of the ⁺ type buried layer 14, the second
An extremely low concentration (N ^- type) epitaxial layer 15 is formed. This epitaxial layer 15 can be formed with a thickness and an impurity concentration suitable for forming a bipolar transistor. Therefore, excellent characteristics as a bipolar transistor can be obtained.

FIG. 4 is a sectional view showing a second embodiment of the semiconductor device of the present invention. This embodiment uses a semiconductor substrate in which a P ⁺ -type buried layer is formed on the surface of P-type silicon, and there is no difference from the first embodiment in other points. . Therefore, the description of the same parts as those in the first embodiment will be omitted because they are duplicated.

[0053] 11a is a P-type semiconductor substrate, the impurity concentration of boron (B) is 1 × 10 ¹⁵ / cm ³ and lower than the semiconductor substrate 11 of the first embodiment, it is a conventional example about.

Reference numeral 11b denotes a P ⁺ -type buried layer, in which a thermal oxide film (film thickness, for example, 100 nm) serving as a buffer is formed on the surface of the semiconductor substrate 11a by a thermal oxidation method when boron ions are implanted later. Boron B is for example 30 KeV
About 1 × 10 ¹⁵ / cm ² with the energy of
Next, a heat treatment for activation is performed in a nitrogen N ₂ atmosphere at a temperature of 1100 ° C. for about 120 minutes, and thereafter, oxidation is performed in a wet oxygen O ₂ atmosphere for 60 minutes. Thereafter, a thermal oxide film is removed, and the ion The damaged layer caused by the implantation is removed.

By forming the P ⁺ type buried layer 11b, the parasitic resistance parasitic on the substrate can be reduced. As described above, this enhances the latch-up resistance. Since the semiconductor substrate 11a itself, in other words, the back side of the substrate has a low concentration, the extremely low concentration epitaxial layer 1 is formed.
In forming the layers 3 and 15, the amount of impurity auto-doping generated from the back side can be reduced. That is, when the impurity concentration of the entire substrate is high, the epitaxial layer 13
Since 15 has an extremely low concentration, there is a possibility that a problem may occur that the impurity is auto-doped from the substrate side when forming this. However, by increasing the concentration only on the surface side as in this embodiment instead of increasing the concentration of the entire substrate, the amount of impurities diffused from the substrate side to the epitaxial layer side can be naturally reduced. Therefore, even if the impurity concentration of the epitaxial layer is low, the epitaxial growth for forming the impurity can be easily performed.

It should be noted that the present invention is not limited to the above embodiment, but can be embodied in other forms. In the above embodiment, the bipolar transistor has a double polysilicon structure. May have an epitaxial base structure.

[0057]

According to the present invention, the extremely low-concentration semiconductor layer corresponding to the region I in the PIN photodiode can be considerably thickened by forming the first layer as a thick layer. The impurity concentration of the semiconductor layer can be made such that the semiconductor layer is completely depleted by a reverse voltage applied for photodetection, for example, 1.5 V, so that the silicon semiconductor with respect to the received light can be formed. Carriers generated at a depth of about twice the absorption length can be converted to a photocurrent. Accordingly, the light receiving sensitivity of the photodiode can be increased, and the parasitic capacitance of the photodiode can be reduced, and the frequency characteristics of the photodiode can be improved.

The second conductive type high-concentration semiconductor region selectively formed on the surface side of the ultra-low-concentration semiconductor region of the same conductivity type and substantially the same depth as the first layer is defined as a collector-side region. In the case where a bipolar transistor having a base and an emitter is provided, a preferable photodiode is obtained by making the first layer a preferable thickness and an impurity concentration for obtaining characteristics required as a photodiode, and a second layer is obtained.
By forming the layer with a thickness and a concentration that are preferable for obtaining characteristics necessary for a bipolar transistor, a bipolar transistor having preferable characteristics can be obtained.

And a first conductivity type high concentration semiconductor substrate;
Since the extremely low-concentration semiconductor layer exists between the second-conductivity-type high-concentration semiconductor region and the second-conductivity-type high-concentration semiconductor region, a parasitic capacitance therebetween (between the substrate and the second-conductivity-type high-concentration semiconductor region) can be reduced. The frequency characteristics of the bipolar transistor can be improved. Since the concentration of at least the surface of the semiconductor substrate is increased, the parasitic resistance of the substrate can be reduced, and the resistance of the parasitic thyristor to latch-up can be increased. Even if the concentration of the semiconductor substrate is increased, the first layer of the extremely low concentration semiconductor layer is interposed between the semiconductor substrate and the high concentration semiconductor region forming the collector of the bipolar transistor, so that the parasitic capacitance therebetween does not increase. Accordingly, the dilemma of reducing the parasitic capacitance and increasing the latch-up resistance in the conventional art is incompatible with each other.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of a semiconductor device of the present invention.

2A to 2C are cross-sectional views illustrating steps (A) to (C) of the method for manufacturing the semiconductor device in FIG. 1;

FIG. 3 is a step (D) of the method for manufacturing the semiconductor device in FIG. 1;
It is sectional drawing which shows (E).

FIG. 4 is a sectional view showing a second embodiment of the semiconductor device of the present invention.

FIG. 5 is a cross-sectional view showing a conventional example of a semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Photodiode formation area, 2 ... Anode common type photodiode formation area, 4 ... Bipolar transistor formation area, 11 ... First conductivity type high concentration semiconductor substrate, 11a ... Semiconductor substrate, 11b
1st conductivity type semiconductor layer, 13 ... 1st layer of extremely low concentration semiconductor layer, 14 ... 2nd conductivity type semiconductor layer, 15 ...
The second layer of the extremely low concentration semiconductor layer.

Claims (5)

[Claims] 1. A semiconductor device comprising at least a light receiving element having a first or second conductivity type ultra-low concentration semiconductor layer between a first conductivity type semiconductor and a second conductivity type semiconductor, wherein the first conductivity type is The semiconductor is composed of a first conductivity type semiconductor substrate having at least a high-concentration surface side, and the extremely low-concentration semiconductor layer includes a first layer formed on the surface of the first conductivity-type high-concentration semiconductor substrate; A second layer formed on the second layer and in contact with the second conductivity type semiconductor. 2. The semiconductor device according to claim 1, wherein the back surface side of the first conductivity type semiconductor substrate is lightly doped. 3. The semiconductor device according to claim 1, wherein the ultra-low concentration semiconductor layer is completely depleted when a reverse voltage is applied to the light receiving element. 4. A high-concentration semiconductor region of the second conductivity type selectively formed on the surface of the first layer of the ultra-low-concentration semiconductor layer is defined as a collector-side region, and a second region of the ultra-low-concentration layer on the upper side thereof is formed. 4. The semiconductor device according to claim 1, further comprising a bipolar transistor having a layer provided with a base and an emitter. 5. A step of depositing a first conductivity type semiconductor layer on a first conductivity type semiconductor substrate; and a step of selectively etching a portion of the first conductivity type semiconductor layer other than a portion to be an element isolation region. Depositing a first or second conductivity type extremely low concentration semiconductor layer, which forms a first layer of the extremely low concentration semiconductor layer, on the semiconductor substrate in a state where the first conductivity type semiconductor layer is selectively formed; And selectively removing a portion of the ultra-low-concentration semiconductor layer higher than the surface of the first-conductivity-type semiconductor layer to achieve smoothing, whereby the ultra-low-concentration semiconductor layer is separated by the first-conductivity-type semiconductor layer. Forming a second conductivity type semiconductor layer by selectively introducing a second conductivity type impurity into the extremely low concentration semiconductor layer; and forming a second layer of the very low concentration semiconductor layer. Depositing a very low concentration semiconductor layer to be formed. 5. The method of manufacturing a semiconductor device according to claim 4, wherein