JPH04151873A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize high speed operation by integrating, in a monolithic manner, electronic function elements like a photodiode and a bipolar transistor on the same substrate. CONSTITUTION:A first epitaxial layer 2 of a lowly doped first conductivity type and a second epitaxial layer 7 of a second conductivity type are formed on a semiconductor substrate 1 of a highly doped first conductivity type; the greater part of the epitaxial layer 7 is etched and eliminated so as to surround a specified region; a buried layer 4 is formed by doping the first epitaxial layer 2 in the vicinity of the etched part with impurities of a first conductivity type. As a result, a photodiode wherein a specified region of the left second epitaxial layer 7 is a cathode or an anode, and the buried layer 4 is an anode or a cathode is constituted. An electronic function element like a bipolar transistor is formed in the second epitaxial layer 7 on the buried layer 4. Thereby high speed operation is enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to an integrated circuit (IC) of an electronic functional element such as a bipolar transistor and a PIN photodiode.

[Conventional technology]

A photodiode with a PIN structure is known as a photoelectric conversion element, and for electrical isolation from other types of elements, such as bipolar transistors, and integration with other elements on the same substrate, etc. Various techniques have been proposed. For example, JP-A-62-123783 and JP-A-62-123783
No. 3-93174 discloses a technique for realizing electrical isolation by interposing a dielectric film between a silicon crystal layer forming a photodiode and a silicon substrate.

Furthermore, in JP-A-62-158373, the silicon substrate is thinned in the region where the silicon photodiode is formed,
Techniques have been shown to reduce leakage current. A technique equivalent to this is also disclosed in Japanese Patent Application Laid-Open No. 6218075. Furthermore, JP-A-63-19882 discloses a technique in which the silicon substrate is made thinner in the region where the photodiode is formed, and the photodiode and the transistor are electrically separated by a pn junction to which a reverse bias voltage is applied. has been done. Also, in JP-A No. 621 and 6568,
A technique has been proposed in which a photodiode is isolated from other elements, such as a transistor, by surrounding it with a dielectric layer.

[Problem to be solved by the invention]

However, these conventional techniques have the disadvantage that the manufacturing process for forming the separation layer becomes complicated and costs increase. Furthermore, since the separation layer becomes thick, there is a drawback that the integration efficiency of the device becomes low. Furthermore, if the integration efficiency deteriorates, the wiring made of aluminum or the like becomes long, increasing the parasitic capacitance, making the device unsuitable for high-speed operation.

An object of the present invention is to provide a semiconductor device in which electronic functional elements such as a photodiode and a bipolar transistor are monolithically integrated on the same substrate and capable of high-speed operation.

[Means to solve the problem]

The present invention provides a semiconductor device in which a first epitaxial layer of a lightly doped first conductivity type is formed on a semiconductor substrate of a highly doped first conductivity type, and a second epitaxial layer of a second conductivity type is further formed thereon. Most of the epitaxial layer is etched away so as to surround a predetermined region of the second epitaxial layer, thereby leaving the second epitaxial layer in a partially open closed region, and the predetermined region By doping the first epitaxial layer in the vicinity of the first epitaxial layer with impurities of the first conductivity type to form a buried layer of the first conductivity type, a predetermined region of the second epitaxial layer left in the closed region by etching can be etched. A photodiode is configured with the buried layer as the anode or cathode, and an electronic functional element such as a bipolar transistor is formed in the second epitaxial layer on the buried layer. It is characterized by

[Effect]

According to the present invention, a two-layer structure consisting of a lightly doped first epitaxial layer of the first conductivity type and a second epitaxial layer of the second conductivity type is formed on the highly doped substrate of the first conductivity type. , it becomes possible to integrate a photodiode and a power reservation function element (for example, a bipolar transistor). In addition, since the buried layer of the first conductivity type is formed under the electronic functional element, punch-through can be prevented, and the second epitaxial layer can be removed by etching to form a closed region that is partially open. , it is possible to reduce parasitic capacitance and also facilitate wiring. Furthermore, since the second epitaxial layer in the closed region is directly used as the cathode or anode, the impurity profile can be made favorable.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to the accompanying drawings.

FIG. 1 shows a semiconductor device according to an embodiment, FIG. 1(b) is a plan view of a photodiode portion, and FIG.
It is a sectional view of the whole cut along a line. The detailed configuration will be made clear in the description of the manufacturing process based on FIG.

First, the monolithic IC of the embodiment has the following features. The first feature is that a two-layer structure of a lightly doped p-type epitaxial layer 2 and an n-type epitaxial layer 7 is formed on a p+ type silicon substrate doped with a high concentration of acceptor impurities. be. This allows the PIN photodiode 31 and the npn bipolar transistor 32, which is an example of an electronic functional element, to coexist on the same semiconductor substrate 1.

The second feature is that an NPN bipolar transistor 32 as an example of an electronic functional element is provided on the p-type epitaxial layer 2 used as one layer of the PIN photodiode 31.
is formed, and an n-type buried layer 4 is provided between this epitaxial layer 2 and the transistor 32. Therefore, so-called punch-through is prevented from occurring between the npn bipolar transistor 32 and the photodiode 3 or between other nearby transistors (not shown). In FIG. 1, the n-type buried layer 4 is provided entirely below the npn bipolar transistor 32, so the collector capacitance becomes large or the resistance to the substrate 1 becomes small. On the other hand, if the p-type buried layer is provided only in the lower periphery of the npn bipolar transistor 32, the collector capacitance will be reduced, but the resistance to the substrate 1 will be increased. The third feature is that the n-type epitaxial layer 7 forms the N layer of the PIN photodiode 31, that is, the anode, and by removing the n-type epitaxial layer 7 around the diode region by forward mesa etching except for a portion, the PIN photodiode 31 and the bipolar transistor are isolated.

Therefore, the oxidation conditions for surface oxidation can be reduced, and the profile can therefore be formed favorably. This is a feature of Japanese Patent Application Nos. 1-229589 to 229594, which are earlier applications filed by the present inventor (all unpublished), that is, the formation of a thermal oxide film with a thickness of about 2 μm is essential. This is a very different point. In addition, in the present invention, some parts are not removed by forward mesa etching, so
When wiring to the anode is formed in this portion, its reliability can be increased.

Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS. 2(A) to 2(0).

Specific resistance is 0.02Ωcm or less (e.g. 0.015Ωcm
A lightly doped p-type epitaxial layer 2 with a resistivity of 500 Ωcm or more (for example, about 1 Ωcm) is formed on a highly doped p-type semiconductor (silicon) substrate 1 with a thickness of 20 to 50 μm (see Fig. 2). See A). Although not shown, a 5IO2 film is formed on the back surface of the substrate 1 to prevent autodoping. Next, a SiO2 film is formed on the surface of the epitaxial layer 2, and the S L O2 film is processed using photolithography technology to form a mask 3.
Set it to 01. Boron (B) ions are implanted from above through the mask 301 to form an ion implantation layer 401 that will become the p-well buried layer 4 for the npn bipolar transistor. The impurity concentration of this buried layer 4 is 1015 to 10
”/am” (see Fig. 2 (B)). p
In order to understand the position of the well-buried layer 4, the same figure (B)
Approximately the right half is the n p n I transistor formation region, and the left half is the PIN photodiode formation region.

Next, a SiO2 film is deposited again, this SiO2 film is processed using photolithography technology, etc., and the processed S
i Antimony (S b) using O2 film as mask 302
to diffuse heat. As a result, a diffusion layer 501 that becomes the n-type buried layer 5 for the npn transistor is formed (see FIG. 2(C)). The impurity concentration of the n-type buried layer 5 after profile formation is about 10 to 10<2>[deg.]cm<3>/. Thereafter, the mask 302 on the surface is removed, and an n-type epitaxial layer 7 having a thickness of 2 μm±0.2 μm is formed. Its impurity concentration is about 1015-1.016/cm3 (
(See Figure 2 (D)). This completes the buried diffusion and epitaxial growth steps.

Next, the photodiode separation process will be explained. First, on the entire surface of the n-type epitaxial layer 7,
A SiO2 film is formed to become a mask 30.3 to be described later. Then, a resist is applied thereon to form a resist film (not shown), and the resist material in a desired area is removed using photolithography technology to form a patterned resist film (not shown). Form. Then, using this resist film as a mask, the SiO2 film is removed by etching to form a mask 303. Thereafter, through the mask 303, the n-type epitaxial layer 7 is mesa-etched from the surface to form a groove with sloped sidewalls, and the n-type epitaxial layer 7 is removed at this portion (see FIG. 2(E)). ). Here, the above-mentioned desired area is the remaining area of the area surrounding the light receiving area of the PIN photodiode, excluding the part to be wired to the anode in a later process. Above,
The photodiode separation process is completed.

Next, after removing the mask 303 on the front surface, a SiO2 film which will become a mask 304 to be described later is formed on the entire exposed surface of the epitaxial layers 2 and 7.

Then, a resist is applied thereon to form a resist film (not shown), and resist marks in desired areas are removed using photolithography technology to form a patterned resist film (not shown).

Then, using this resist film as a mask, the 5i02 film is removed by etching to form a mask 304. Thereafter, through the mask 304, the n-type epitaxial layer 7 is wet-etched to a depth of 0.2 μm from the surface (see FIG. 2(F)), and then anisotropic dry-etched to a depth that penetrates the n-type epitaxial layer 7. to form a rectangular groove penetrating the epitaxial layer 7 (see FIG. 2 (G)).
)reference). Here, the above-mentioned desired region is a separation region of an npn transistor, a separation region between a p-type base layer and a collector layer, which will be provided inside the npn transistor in a later step, or the like. Furthermore, in the process of this anisotropic dry etching, the mask 305 is also etched and becomes thinner.

Next, after removing the mask 305 on the surface, the SiN film 26 for oxidation resistance and the S I
An O2 film 27 is formed over the entire surface. Then, polysilicon 28 is deposited on the entire surface (see FIG. 2(H)), and polysilicon except for the rectangular groove is removed by etching (see FIG. 2(H)).
1)). At this time, the 5I02 film 27 other than the rectangular groove
Since the film 26 is also removed at the same time, the term SIN film 26 is used here.

Next, the upper portion of the polysilicon 28 is thermally oxidized to form a second
(see figure (J)) and planarize it by lightly etching it. Hereinafter, insulators will be represented by hatching and detailed illustrations will be omitted (see FIG. 2 (K)).

Next, a resist is applied to the entire surface using a spin code method or the like, and patterned to form a mask 30 having openings in predetermined areas.
6 is formed, and boron ions are implanted. This results in n
Ion implantation layers 701, 702,
703 (see FIG. 2(L)). Here, the above-mentioned predetermined area is the area where the cathode electrode of the PIN photodiode is to be taken out. Thereafter, the p+ layers 71 .
．． Form a profile of 72.73 (Fig. 2 (M)
reference).

Next, steps are performed to form the n+ layer 16 from which the anode electrode of the PI'N photodiode is to be taken out, and to form the bipolar transistor. Forming a bipolar transistor] - The process is carried out by a known method,
- Form the n+ layer 15, the external base 18, and the intrinsic base 19, which will become the collector all of the transistor.

Note that the n-type epitaxial layer 7 remaining below the intrinsic base 19 becomes a collector 23, and the emitter 22 is formed above the base 19. Then, unnecessary layers are removed by dry etching or the like, and a SiO2 film is deposited again by the CVD method (see FIG. 2 (N)). And emitter 22
An opening is formed in the insulating film above the wafer, and an emitter electrode 91 is formed therein using polysilicon (see FIG. 2(0)).

The semiconductor device shown in FIG. 1 is obtained by forming the necessary electrodes 92 on both sides of the interlayer insulating film shown by dots in the figure after going through the above steps, and also includes a PIN photodiode on the same substrate. 31 and an npn transistor 32 are monolithically formed. The PIN photodiode 31 is
The p-type buried layer 4 is a P layer (cathode), the low-doped p-type epitaxial layer 2 is one layer, and the n-type epitaxial layer 7 is an N layer (cathode).
The first PIN-type silicon photodie is used as an anode. A ring-shaped anode electrode (electrode 92A) is connected to the n-type epitaxial layer 7 via a ring-shaped n+ layer 16 for electrode extraction, and a p+ layer for electrode extraction is connected to the p-type buried layer 4. A cathode electrode (electrode 92C) is provided via layer 72.7B. And the anode electrode 9
The wiring from 2A is formed on the n-type epitaxial layer 7 remaining without being mesa-etched, as shown in FIG. 1(b). When light is incident with a reverse bias voltage applied between these electrodes, carriers are generated in the depletion region of the low-dip p-type epitaxial layer 2, and these pairs of electrons and holes are moved by the electric field in the depletion region. It becomes a photocurrent.

Here, the above depletion layer is 30μI at about V from the applied voltage.
Since the width is about n, a significant reduction in capacity can be achieved.

Note that if a back electrode (not shown) is added as an anode electrode, parasitic resistance can be further reduced.

As shown in the figure, the npn transistor 32 is provided with an emitter electrode, a base electrode, and a collector electrode. The p-type buried layer 4 also serves to prevent punch-through with other surrounding elements by compensating the resistivity. According to this semiconductor device, since the PIN photodiode and the npn bipolar transistor are monolithically formed on the same substrate, it has the effect of reducing parasitic capacitance due to wiring.

Therefore, when used in optical communication receiving circuits, etc., it is possible to operate at higher speeds than conventional circuits.

Furthermore, there is no need for an assembly process like that required for hybrid ICs.

In addition, the anode electrode 92A of the PIN photodiode 31
Areas where wiring such as aluminum is drawn from
Since the entire surface including the transistor 32 is flat, the wiring process for aluminum or the like can be carried out smoothly and reliably. That is, when forming a groove surrounding the photodiode 3 to isolate it,
Since the mesa etching is performed so as to leave a part of the n-type epitaxial layer 7, a part of the n-type epitaxial layer 7 is left open as a closed region. Therefore, an anode electrode and wiring can be formed on a flat surface.

Note that the groove surrounding the light-receiving area of the photodiode is not limited to one with sloped side walls, but may be a rectangular groove formed by anisotropic etching. It is also possible to use reverse mesa etching. Furthermore, in each embodiment, the conductivity types of the substrate 1 and the epitaxial layer 2.7 may be reversed. In this case, the anode and cathode of the photodiode are reversed.

According to the embodiment described above, the following effects occur.

The first is the effect of improving high speed and high frequency characteristics by making the first epitaxial layer lightly doped.

That is, the higher the resistance of the first conductivity type (p) epitaxial layer, the wider the depletion layer becomes. For example, the specific resistance of the p layer is 1
If Ωam is set to Ωam and the epitaxial layer is set to a thickness of 30 μm, the epitaxial layer is occupied by a depletion layer with an applied voltage of 5 μm.

Therefore, since the response speed of the photodiode is determined by the carrier transit time in the depletion layer, the cut-off frequency extends to several hundred megahertz.

Second, the sidewall of the second epitaxial layer is sloped.
Alternatively, remove it in a roughly “C”-shaped groove with a vertical surface,
This is the effect of improving high-speed and high-frequency characteristics by isolating the photodiode.

That is, as for the parasitic capacitance effect around the anode, if the separation method of the present invention is applied to, for example, a 1 mm square photodiode, the pn junction area is small, so the overall junction capacitance can be reduced to about 10 PF at OV bias. However, even with a PIN photodiode structure of the same size, if junction capacitance due to pn junction isolation is added surrounding the anode, the parasitic capacitance increases to 13. Increases to about F. In the present invention, the separation capacity can be reduced by using a groove (approximately rCJ-shaped groove with forward mesa etching) in which a portion of the inclined sidewall is open, thereby making it possible to increase the speed of the - layer.

The third effect is that the separation in the photodiode and the separation in the electronic functional element are performed using different methods. In other words, as shown in the example, if photodiodes are separated by sequential mesa etching in addition to trench-type insulator isolation in electronic functional elements such as bipolar transistors, multi-element isolation of the anode of a PIN photodiode is possible. Can be done. That is, it is possible to easily provide a plurality of mesa-shaped anodes while minimizing the influence on other device characteristics and reducing manufacturing costs.

The fourth effect is that variations in characteristics between elements can be suppressed. In the single-element manufacturing method for high-speed PIN photodiodes, an anode is formed by impurity diffusion from an initial P/P type high-resistance epitaxial wafer. Problems such as generation of dark current and variations in photosensitivity are likely to occur. In this invention, the anode is made by dividing the second conductivity type epitaxial layer, and since the impurity concentration and thickness of the epitaxial layer are highly controllable, the dark current, sensitivity characteristics, and yield are improved, and the device is suitable for batch processing. Interval variation is suppressed.

〔Effect of the invention〕

According to the present invention, a two-layer structure consisting of a lightly doped epitaxial layer of the first conductivity type and an epitaxial layer of the second conductivity type is formed on the highly doped substrate of the first conductivity type, so that the photodiode and the bipolar transistor are It becomes possible to integrate such electronic functional elements. In addition, since the buried layer of the first conductivity type is formed under the electronic functional element, punch-through can be prevented, and the isolation region is formed in a partially open closed region. In addition to improving high speed and high frequency characteristics, since the second conductivity type epitaxial layer is directly used as the cathode or anode, the impurity profile can be made favorable. Therefore, it is possible to provide a semiconductor device in which electronic functional elements such as a photodiode and a bipolar transistor are monolithically integrated on the same substrate, and which enables high-speed operation.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the structure of a monolithic IC according to an embodiment of the present invention, and FIGS. 2(A) to (0) are cross-sectional views showing the manufacturing process of the monolithic IC shown in FIG. DESCRIPTION OF SYMBOLS 1...p+ type silicon substrate, 2...p type epitaxial layer, 4...p type buried layer, 7...n type epitaxial layer.

Claims (1)

[Claims] 1. A lightly doped first conductivity type semiconductor substrate on a highly doped first conductivity type semiconductor substrate.
A semiconductor device in which a first epitaxial layer of a conductivity type is formed, and a second epitaxial layer of a second conductivity type is further formed thereon, the semiconductor device comprising a part of a region surrounding a predetermined region of the second epitaxial layer. The epitaxial layer is etched and removed, leaving the epitaxial layer in a partially opened closed region, and the first epitaxial layer near the predetermined region is doped with a first conductivity type impurity. and forming a buried layer of the first conductivity type, a predetermined region of the second epitaxial layer left in the closed region by the etching is used as a cathode or an anode, and the buried layer is used as an anode or a cathode. A semiconductor device comprising a photodiode, and further comprising an electronic functional element formed in the second epitaxial layer above the buried layer. 2. The electronic functional element is a bipolar transistor constituted by a base layer and an emitter layer formed by doping impurities into the second epitaxial layer, and a collector layer formed by the second epitaxial layer itself. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein the entire lower side of the electronic functional element is surrounded by the buried layer. 4. The semiconductor device according to claim 1, wherein the entire lower periphery of the electronic functional element is surrounded by the buried layer.