JP3562282B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP3562282B2
JP3562282B2 JP35257597A JP35257597A JP3562282B2 JP 3562282 B2 JP3562282 B2 JP 3562282B2 JP 35257597 A JP35257597 A JP 35257597A JP 35257597 A JP35257597 A JP 35257597A JP 3562282 B2 JP3562282 B2 JP 3562282B2
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conductivity
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JPH11186555A (en
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仁路 高野
正彦 鈴村
嘉城 早崎
裕二 鈴木
良史 白井
貴司 岸田
岳司 吉田
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Panasonic Electric Works Co Ltd
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Matsushita Electric Works Ltd
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
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Description

【０００１】
【発明の属する技術分野】
本発明は、ＳＯＩ構造型の半導体装置に関するものである。
【０００２】
【従来の技術】
近年、発光素子と受光素子とを光結合し、受光素子の出力によって出力用パワー素子にスイッチング動作を行わせる光結合型半導体リレーにおいて、リレーオフ時の出力端子間容量を低減するために出力用パワー素子にＳＯＩ（Ｓｉｌｉｃｏｎ Ｏｎ Ｉｎｓｕｌａｔｏｒ）技術を利用したＳＯＩ構造型のパワー半導体装置を使用することが注目されている。この種のパワー半導体装置の一つとして、横型二重拡散ＭＯＳ電解効果トランジスタ、いわゆるＬＤＭＯＳＦＥＴ（Ｌａｔｅｒａｌ Ｄｏｕｂｌｅ Ｄｉｆｆｕｓｅｄ ＭＯＳＦＥＴ）がある。
【０００３】
図６は、従来例に係る光結合型半導体リレーの一部を示す概略平面配置図である。受光素子である太陽電池１６と２つの出力用のＭＯＳＦＥＴ１７がＧＮＤ端子フレーム１８上に配設され、太陽電池１６のカソード１６ａ及びＭＯＳＦＥＴ１７のソース電極１７ａがボンディングワイヤ１９によりＧＮＤ端子フレーム１８と電気的に接続されている。これにより、太陽電池１６のカソード１６ａとＭＯＳＦＥＴ１７のソース電極１７ａとは、ＧＮＤ端子フレーム１８を介して電気的に接続されている。なお、ＭＯＳＦＥＴ１７としては、ＳＯＩ構造型のＬＤＭＯＳＦＥＴが用いられる。
【０００４】
また、ＧＮＤ端子フレーム１８の両側に並設された出力端子フレーム２０とＭＯＳＦＥＴ１７のドレイン電極１７ｂとがボンディングワイヤ１９により電気的に接続され、太陽電池１６のアノード１６ｂとＭＯＳＦＥＴ１７のゲート電極１７ｃとがボンディングワイヤ１９により電気的に接続されている。
【０００５】
図７は、従来例に係る光結合型半導体リレーの概略断面図である。光結合型半導体リレーは、図７に示すように、ＧＮＤ端子フレーム１８に対向配置された入力端子フレーム２１上には、発光素子である発光ダイオード２２が配設され、全体を遮光性樹脂２３でモールドされて１パッケージ化されている。そして、太陽電池１６と発光ダイオード２２との間を光を透過する透光性樹脂２４から成る導光路により光結合され、発光ダイオード２２からの光を太陽電池１６で受光できるようにしている。
【０００６】
このように構成された光結合型半導体リレーは、発光ダイオード２２を外部駆動信号で発光させ、その発光ダイオード２２からの光を受光した太陽電池１６は電圧を発生させ、この電圧が一定レベルに達すると、出力用のＭＯＳＦＥＴ１７がスイッチングし、光結合型半導体リレーがオン、またはオフする。
【０００７】
図８は、従来例に係る光結合型半導体リレーの出力端子間容量の容量成分を示す等価回路図である。出力端子間容量は、二つのＳＯＩ構造型のＬＤＭＯＳＦＥＴの出力容量（Ｃｏｓｓ）の直列合成容量で形成され、出力容量（Ｃｏｓｓ）は、ドレイン・ソース間容量（Ｃｄｓ），ゲート・ドレイン間容量（Ｃｇｄ）及びドレイン・基板間容量（Ｃｄｓｕｂ）の並列合成容量で形成される。
【０００８】
図９は、従来例に係るＳＯＩ構造型のＬＤＭＯＳＦＥＴを示す概略構成図であり、（ａ）は上面から見た状態を示す概略平面図であり、（ｂ）は（ａ）におけるＦーＦ’での概略断面図である。このＬＤＭＯＳＦＥＴは、単結晶シリコン等の半導体基板１の一主表面上にシリコン酸化膜等の第一の絶縁層である絶縁層２が形成され、絶縁層２上に第一導電型半導体層であるｎ型半導体層３が形成されてＳＯＩ（Ｓｉｌｉｃｏｎ ＯｎＩｎｓｕｌａｔｏｒ）基板を構成している。
【０００９】
なお、ＳＯＩ基板の形成方法の一例としては、絶縁層上に気相，液相，固相の各相で単結晶シリコンを成長させるＳＯＩ成長法や、基板を貼り合わせる貼り合わせＳＯＩ法や、単結晶シリコン中に酸素をイオン注入して内部に絶縁層を形成するＳＩＭＯＸ（Ｓｅｐａｒａｔｉｏｎ ｂｙ Ｉｍｐｌａｎｔｅｄ Ｏｘｙｇｅｎ）法や、陽極酸化によってシリコンを部分的に多孔質化し酸化することによって形成する方法等がある。
【００１０】
ＳＯＩ基板におけるｎ型半導体層３内に、表面から絶縁層２に達するように高濃度第二導電型素子分離領域であるｐ＋型素子分離領域４が形成され、ｎ型半導体層３は、絶縁層２及びｐ＋型素子分離領域４により絶縁分離された複数の領域に分割される。
【００１１】
そして、絶縁分離されたｎ型半導体層３の表面に露出するように、ｎ型半導体層３内の略中央に高濃度第一導電型ドレイン領域であるｎ＋型ドレイン領域５が形成され、ｎ＋型ドレイン領域５との間で所定の耐圧を保持できる最短の距離だけ離間されるようにｎ＋型ドレイン領域５を囲み、ｎ型半導体層３の表面に露出するようにｎ型半導体層３内に第二導電型ウェル領域であるｐ型ウェル領域６が形成され、ｐ型ウェル領域６に内包され、ｎ型半導体層３の表面に露出するように高濃度第一導電型ソース領域であるｎ＋型ソース領域７が形成されている。
【００１２】
なお、ｎ＋型ドレイン領域５及ぴｎ＋型ソース領域７の形成方法としては、リン（Ｐ）等のｎ型不純物をイオン注入及ぴアニール処理を行うことにより形成することができ、ｐ型ウェル領域６の形成方法としては、ボロン（Ｂ）等のｐ型不純物をイオン注入及びアニール処理を行うことにより形成することができる。
【００１３】
また、ｎ＋型ドレイン領域５とｎ＋型ソース領域７との間に介在するｐ型ウェル領域６上には、薄い膜厚の第二の絶縁層であるゲート酸化膜８を介してポリシリコン等から成る絶縁ゲート９が形成され、ＳＯＩ基板の絶縁ゲート９形成面側にはシリコン酸化膜等の第三の絶縁層であるパッシベーション膜１０が形成されている。ここで、絶縁ゲート９は、ｎ＋型ドレイン領域５とｎ＋型ソース領域７との間でｎ型半導体層３内を流れる主電流を制御するものである。
【００１４】
そして、ｎ＋型ドレイン領域５と電気的に接続されるようにアルミニウム（Ａｌ）等から成るドレイン電極１１が形成され、ｎ＋型ソース領域７及び絶縁ゲート９に囲まれたドレイン電極１１上には、ドレインボンディングパッド１１ａが形成されている。ここで、ドレインボンディングパッド１１ａは、ボンディングワイヤと接続するため通常１００μｍ□（１辺約１００μｍの正方形、以下において同じ）以上の面積を必要とする。
【００１５】
また、ｐ型ウェル領域６及びｎ＋型ソース領域７と電気的に接続されるようにＡｌ等から成るソース電極（図示せず）が形成され、絶縁ゲート９と電気的に接続されるようにＡｌ等から成るゲート電極（図示せず）が形成されている。
【００１６】
ここで、ドレイン・基板間容量（Ｃｄｓｕｂ）は、ＳＯＩ基板の絶縁層２を挟んだドレイン電位とＧＮＤ電位との電位差によって生じる容量であり、ｐ型ウェル領域６によって囲まれた内側のｎ型半導体層３の絶縁層２側の面の面積（以下において、ドレイン面積という）に比例する特性である。そこで、ドレイン面積が大きくなると、出力容量（Ｃｏｓｓ）も大きくなり、結局光結合型半導体リレーの出力端子間容量も大きくなるという欠点を有する。
【００１７】
また、近年では素子の小型化も望まれているが、図９（ａ）に示すように、ドレインボンディングパッド１１ａがｎ＋型ソース領域７及び絶縁ゲート９に囲まれた内側に形成されている構造においては、ＳＯＩ構造型のＬＤＭＯＳＦＥＴをパッド面積以下に小さくすることができないという欠点も有する。
【００１８】
この問題を解決する方法として、図１０に示すように、ｐ型ウェル領域６の内側のドレイン電極１１から絶縁ゲート９及びｎ＋型ソース領域７を跨ぐようにドレイン電極１１を引き出し、ドレインボンディングパッド１１ａを絶縁ゲート９及びｎ＋型ソース領域７の外側に形成すれば良く、この場合、ｐ型ウェル領域６に囲まれた内側のドレイン面積を小さくすることができ、ドレイン・基板間容量（Ｃｄｓｕｂ）を小さくすることができる。また、ＳＯＩ構造型のＬＤＭＯＳＦＥＴもドレインボンディングパッド１１ａの面積に依存せず、小型化することができる。
【００１９】
【発明が解決しようとする課題】
ところが、上述の場合、ドレイン電極１１のドレインボンディングパッド１１ａと、ドレインボンディングパッド１１ａ下部のｐ＋型素子分離領域４との電位差により、パッシベーション膜１０を挟んで新たな寄生容量Ｃ１が生じるという問題があった。
【００２０】
本発明は、上記の点に鑑みて成されたものであり、その目的とするところは、ドレインボンディングパッドを絶縁ゲート及びソース領域の外側に形成した場合の、ドレインボンディングパッドにより形成される寄生容量を小さくし、かつ、出力容量を低減化することのできる半導体装置を提供することにある。
【００２１】
【課題を解決するための手段】
請求項１記載の発明は、半導体基板と該半導体基板上に第一の絶縁層を介して形成された第一導電型半導体層とから成るＳＯＩ基板と、該第一導電型半導体層の表面に露出するように前記第一導電型半導体層内に形成された高濃度第一導電型ドレイン領域と、前記高濃度第一導電型ドレイン領域と離間して囲むとともに、前記第一導電型半導体層の表面に露出するように前記第一導電型半導体層内に形成された第二導電型ウェル領域と、該第二導電型ウェル領域に内包され、前記第一導電型半導体層の表面に露出するように前記第一導電型半導体層内に形成された高濃度第一導電型ソース領域と、前記高濃度第一導電型ドレイン領域と前記高濃度第一導電型ソース領域との間に介在する前記第二導電型ウェル領域上に第二の絶縁層を介して形成された絶縁ゲートと、前記高濃度第一導電型ソース領域を囲むとともに、前記第一導電型半導体層の表面から前記第一の絶縁層に達するように形成された高濃度第二導電型素子分離領域と、前記高濃度第一導電型ドレイン領域と電気的に接続されたドレイン電極と、該ドレイン電極に電気的に接続されたドレインボンディングパッドとを有して成る半導体装置において、前記ドレイン電極が第三の絶縁層を介して前記高濃度第二導電型素子分離領域を跨いで外側まで延設され、前記ドレインボンディングパッドが、前記高濃度第二導電型素子分離領域を跨いだ外側で前記ドレイン電極と電気的に接続されて成ることを特徴とするものである。
【００２２】
請求項２記載の発明は、請求項１記載の半導体装置において、前記高濃度第二導電型素子分離領域を跨いで外側の前記第一導電型半導体層内に、該第一導電型半導体層の表面から前記第一の絶縁層に達する高濃度第二導電型不純物領域が形成され、該高濃度第二導電型不純物領域上に前記第三の絶縁層を介して前記ドレインボンディングパッドが配置され、前記高濃度第二導電型不純物領域が前記高濃度第二導電型素子分離領域と離間して成ることを特徴とするものである。
【００２３】
請求項３記載の発明は、請求項１記載の半導体装置において、前記高濃度第二導電型素子分離領域を跨いで外側の前記第一導電型半導体層内に、該第一導電型半導体層の表面から前記第一の絶縁層に達する高濃度第二導電型不純物領域が形成され、該高濃度第二導電型不純物領域内に、絶縁分離されて成る第一導電型半導体領域が形成され、該第一導電型半導体領域上に、前記第三の絶縁層を介して前記ドレインボンディングパッドが配置され、前記高濃度第二導電型不純物領域が前記高濃度第二導電型素子分離領域と離間して成ることを特徴とするものである。
【００２４】
請求項４記載の発明は、請求項１乃至請求項３のいずれかに記載の半導体装置において、前記ドレインボンディングパッド直下及びその近傍の前記半導体基板に、前記第一の絶縁層に達する貫通孔を形成したことを特徴とするものである。
【００２５】
請求項５記載の発明は、請求項１乃至請求項４のいずれかに記載の半導体装置において、少なくとも前記ドレインボンディングパッド直下の前記第三の絶縁層が、シリコン酸化膜とシリコン窒化膜とから成る多層膜で構成されて成ることを特徴とするものである。
【００２６】
【発明の実施の形態】
以下、本発明の実施形態について図面に基づき説明する。なお、以下の実施形態においては、第一導電型をｎ型、第二導電型をｐ型として説明するが、第一導電型がｐ型、第二導電型がｎ型の場合にも適用できる。
【００２７】
＝実施形態１＝
図１は、本発明の一実施形態に係るＳＯＩ構造型のＬＤＭＯＳＦＥＴを示す概略構成図であり、（ａ）は上面から見た状態を示す概略平面図であり、（ｂ）は（ａ）におけるＡーＡ’での概略断面図であり、（ｃ）はドレインボンディングパッド１１ａ形成箇所の寄生容量の等価回路図である。本実施形態に係るＬＤＭＯＳＦＥＴは、従来例として図１０に示すＬＤＭＯＳＦＥＴにおいて、ドレイン電極１１をｐ＋型素子分離領域４を跨いで引き出し、ｐ＋型素子分離領域４の外部にドレインボンディングパッド１１ａを形成した構成である。
【００２８】
本実施形態に係るＳＯＩ構造型のＬＤＭＯＳＦＥＴにおいては、ドレインボンディングパッド１１ａ形成箇所の寄生容量（Ｃｐａｄ）は、ドレインボンディングパッド１１ａ直下のパッシベーション膜１０による容量Ｃ１に、絶縁層２による容量Ｃ２と、ｐ＋型素子分離領域４との接合による容量Ｃ３との並列容量が直列に結合する直並列回路となるため、従来の技術に示したような容量Ｃ１のみの場合と比べると、ドレインボンディングパッド１１ａ形成箇所の寄生容量（Ｃｐａｄ）は小さくなる。
【００２９】
具体的に示すと、ドレインボンディングパッド１１ａの面積を約１４５μｍ□，ドレインボンディングパッド１１ａ直下のパッシベーション膜１０の厚みを約１μｍ，ｎ型半導体層３の厚みを約２μｍ，ｎ型半導体層３の濃度を約７×１０１５ｃｍ−３，ｐ＋型素子分離領域４の濃度を約１×１０１８ｃｍ−３，ｐ＋型素子分離領域４のジャンクション面積を約３．４×１０−５ｃｍ２，絶縁層２の厚みを約２μｍ，ドレイン面積を約２．９×１０−３ｃｍ２と考えると、Ｃ１≒０．７５ｐＦ，Ｃ２≒５．０ｐＦ，Ｃ３≒１．６ｐＦであり、Ｃｐａｄ≒０．６５ｐＦとなるから、ドレインボンディングパッド１１ａ形成箇所の寄生容量（Ｃｐａｄ）は０．１ｐＦ減少（１３％削減）される。
【００３０】
＝実施形態２＝
図２は、本発明の他の実施形態に係るＳＯＩ構造型のＬＤＭＯＳＦＥＴを示す概略構成図であり、（ａ）は上面から見た状態を示す概略平面図であり、（ｂ）は（ａ）におけるＢーＢ’での概略断面図であり、（ｃ）はドレインボンディングパッド１１ａ形成箇所の寄生容量の等価回路図である。本実施形態に係るＬＤＭＯＳＦＥＴは、実施形態１として図１に示すＬＤＭＯＳＦＥＴにおいて、ドレインボンディングパッド１１ａの下部及びその近傍のｎ型半導体層３内に、表面から絶縁層２に到達するように高濃度第二導電型不純物領域であるｐ＋型浮遊電位領域１２が形成された構成である。ここで、ｐ＋型浮遊電位領域１２とｐ＋型素子分離領域４とは離間されて成る。
【００３１】
本実施形態に係るＳＯＩ構造型のＬＤＭＯＳＦＥＴにおいては、ドレインボンディングパッド１１ａ形成箇所のパッシベーション膜１０による容量Ｃ１と、絶縁層２による容量Ｃ４と、ｐ＋型素子分離領域４による容量Ｃ５と、ｐ＋型浮遊電位領域１２の接合による容量Ｃ６との直並列回路となる。
【００３２】
ここで、本実施形態においては、ｐ＋型浮遊電位領域１２の接合容量Ｃ８にｐ＋型素子分離領域４の接合容量Ｃ７が直列に結合することで、ドレインボンディングパッド１１ａ形成箇所の寄生容量（Ｃｐａｄ）は、実施形態２における寄生容量（Ｃｐａｄ）よりも更に小さくなる。
【００３３】
具体的に示すと、ドレインボンディングパッド１１ａの面積を約１４５μｍ□，ドレインボンディングパッド１１ａ直下のパッシベーション膜１０の厚みを約１μｍ，ｎ型半導体層３の厚みを約２μｍ，ｎ型半導体層３の濃度を約７×１０１５ｃｍ−３，ｐ＋型素子分離領域４の濃度を約１×１０１８ｃｍ−３，ｐ＋型浮遊電位領域１２の側壁の面積を約１．１×１０−５ｃｍ２，絶縁層２の厚みを約２μｍ，ドレイン面積を約１．４×１０−２ｃｍ２と考えると、Ｃ１≒０．７５ｐＦ，Ｃ４≒０．５５ｐＦ，Ｃ５≒１．６ｐＦ，Ｃ６≒０．３４ｐＦであり、Ｃｐａｄ≒０．４０ｐＦとなるから、ドレインボンディングパッド１１ａ形成箇所の寄生容量（Ｃｐａｄ）は０．３５ｐＦ減少（４７％削減）される。
【００３４】
＝実施形態３＝
図３は、本発明の他の実施形態に係るＳＯＩ構造型のＬＤＭＯＳＦＥＴを示す概略構成図であり、（ａ）は上面から見た状態を示す概略平面図であり、（ｂ）は（ａ）におけるＣーＣ’での概略断面図であり、（ｃ）はドレインボンディングパッド１１ａ形成箇所の寄生容量の等価回路図である。本実施形態に係るＬＤＭＯＳＦＥＴは、実施形態２として図２に示すＬＤＭＯＳＦＥＴにおいて、ｐ＋型浮遊電位領域１２内に、ｎ型半導体層３から成る第一導電型半導体領域であるｎ型半導体領域１３を形成し、ｎ型半導体領域１３上にパッシベーション膜１０を介してドレインボンディングパッド１１ａが形成された構成である。ここで、ｐ＋型浮遊電位領域１２とｐ＋型素子分離領域４とは離間されて成る。
【００３５】
本実施形態に係るＳＯＩ構造型のＬＤＭＯＳＦＥＴにおいては、ドレインボンディングパッド１１ａ形成箇所のパッシベーション膜１０による容量Ｃ１と、絶縁層２による容量Ｃ７と、ｐ＋型浮遊電位領域１２のｐ＋型素子分離領域４側の容量Ｃ８と、ｐ＋型浮遊電位領域１２のｎ型半導体領域１３側の容量Ｃ９と、ｐ＋型素子分離領域４の容量Ｃ５との直並列回路となる。
【００３６】
ここで、本実施形態においては、ｐ＋型素子分離領域４の接合容量Ｃ５に、ｐ＋型浮遊電位領域１２の外側及び内側の接合容量Ｃ８，Ｃ９が直列に結合することで、ドレインボンディングパッド１１ａ形成箇所の寄生容量（Ｃｐａｄ）は、実施形態２における寄生容量（Ｃｐａｄ）よりも更に小さくなる。
【００３７】
具体的に示すと、ドレインボンディングパッド１１ａの面積を約１４５μｍ□，ドレインボンディングパッド１１ａ直下のパッシベーション膜１０の厚みを約１μｍ，ｎ型半導体層３の厚みを約２μｍ，ｎ型半導体層３の濃度を約７×１０１５ｃｍ−３，ｐ＋型素子分離領域４の濃度を約１×１０１８ｃｍ−３，ｐ＋型浮遊電位領域１２の側壁の面積を約１．１×１０−５ｃｍ２，絶縁層２の厚みを約２μｍ，ドレイン面積を約１．４×１０−２ｃｍ２と考えると、Ｃ１≒０．７５ｐＦ，Ｃ７≒０．５５ｐＦ，Ｃ５≒１．６ｐＦ，Ｃ８≒０．３４ｐＦ，Ｃ９≒０．３４ｐＦであり、Ｃｐａｄ≒０．３６ｐＦとなるから、ドレインボンディングパッド１１ａ形成箇所の寄生容量（Ｃｐａｄ）は０．３９ｐＦ減少（５２％削減）される。
【００３８】
＝実施形態４＝
図４は、本発明の他の実施形態に係るＳＯＩ構造型のＬＤＭＯＳＦＥＴを示す概略構成図であり、（ａ）は上面から見た状態を示す概略平面図であり、（ｂ）は（ａ）におけるＤーＤ’での概略断面図であり、（ｃ）はドレインボンディングパッド１１ａ形成箇所の寄生容量の等価回路図である。本実施形態に係るＬＤＭＯＳＦＥＴは、実施形態１として図１に示すＬＤＭＯＳＦＥＴにおいて、ドレインボンディングパッド１１ａ下部の半導体基板１に、半導体基板１の裏面側（ＳＯＩ基板のパッシベーション膜１０形成面と異なる面側）から絶縁層２に達する、ドレインボンディングパッド１１ａの大きさと略同様の大きさの貫通孔１４が形成された構成である。ここで、貫通孔１４の開口面積は、ドレインボンディングパッド１１ａの開口面積と同等以上となっている。
【００３９】
なお、貫通孔１４は、ＴＭＡＨ（Ｔｅｔｒａ Ｍｅｔｈｙｌ Ａｍｍｏｎｉｕｍ Ｈｙｄｒｏｘｉｄｅ）等の異方性エッチャントを用いたウェットエッチングや、プラズマを用いたドライエッチングによって形成することができる。
【００４０】
本実施形態に係るＳＯＩ構造型のＬＤＭＯＳＦＥＴにおいては、ドレインボンディングパッド１１ａ直下の半導体基板１に貫通孔１４が形成されているため、絶縁層２による容量が殆ど発生せず、ドレインボンディングパッド１１ａ形成箇所の寄生容量（Ｃｐａｄ）は、ドレインボンディングパッド１１ａ形成箇所のパッシベーション膜１０による容量Ｃ１と、ｐ＋型素子分離領域４による容量Ｃ３との直列結合となり、従来の技術に示したような容量Ｃ１のみの場合と比べると、ドレインボンディングパッド１１ａ形成箇所の寄生容量（Ｃｐａｄ）は小さくなる。
【００４１】
具体的に示すと、ドレインボンディングパッド１１ａの面積を約１４５μｍ□，ドレインボンディングパッド１１ａ直下のパッシベーション膜１０の厚みを約１μｍ，ｎ型半導体層３の厚みを約２μｍ，ｎ型半導体層３の濃度を約７×１０１５ｃｍ−３，ｐ＋型素子分離領域４の濃度を約１×１０１８ｃｍ−３，ジャンクション面積を約３．４×１０−５ｃｍ２と考えると、Ｃ１≒０．７５ｐＦ，Ｃ３≒１．６ｐＦであり、Ｃｐａｄ≒０．５１ｐＦとなるから、ドレインボンディングパッド１１ａ形成箇所の寄生容量（Ｃｐａｄ）は０．２４ｐＦ減少（３２％削減）される。
【００４２】
＝実施形態５＝
図５は、本発明の他の実施形態に係るＳＯＩ構造型のＬＤＭＯＳＦＥＴを示す概略構成図であり、（ａ）は上面から見た状態を示す概略平面図であり、（ｂ）は（ａ）におけるＥーＥ’での概略断面図であり、（ｃ）はドレインボンディングパッド１１ａ形成箇所の寄生容量の等価回路図である。本実施形態に係るＬＤＭＯＳＦＥＴは、実施形態１として図１に示すＬＤＭＯＳＦＥＴにおいて、パッシベーション膜１０と、ドレイン電極１１及びドレインボンディングパッド１１ａとの間にシリコン窒化膜１５を介在させた構成である。
【００４３】
なお、本実施形態においては、パッシベーション膜１０と、ドレイン電極１１及びドレインボンディングパッド１１ａとの間にシリコン窒化膜１５のみを介在させるようにしたが、これに限定されるものではなく、多層膜を介在させるようにしても良い。
【００４４】
本実施形態に係るＳＯＩ構造型のＬＤＭＯＳＦＥＴにおいては、ドレインボンディングパッド１１ａ形成箇所の寄生容量（Ｃｐａｄ）は、ドレインボンディングパッド１１ａ形成箇所のパッシベーション膜１０による容量Ｃ１と、ドレインボンディングパッド１１ａ形成箇所のシリコン窒化膜１５による容量Ｃ１０と、絶縁層２による容量Ｃ２と、ｐ＋型素子分離領域４による容量Ｃ３との直並列回路となる。
【００４５】
本実施形態における寄生容量（Ｃｐａｄ）の低減を具体的に示すと、ドレインボンディングパッド１１ａの面積を約１４５μｍ□，ドレインボンディングパッド１１ａ直下のパッシベーション膜１０の厚みを約１μｍ，ｎ型半導体層３の厚みを約２μｍ，ｎ型半導体層３の濃度を約７×１０１５ｃｍ−３，ｐ＋型素子分離領域４の濃度を約１×１０１８ｃｍ−３，ｐ＋型素子分離領域４のジャンクション面積を約３．４×１０−５ｃｍ２，シリコン窒化膜１４の厚みを約０．５μｍ，絶縁層２の厚みを約２μｍ，ドレイン面積を約１．４×１０−２ｃｍ２と考えると、Ｃ１≒０．７５ｐＦ，Ｃ２≒０．５５ｐＦ，Ｃ３≒１．６ｐＦ，Ｃ１０≒２．６ｐＦであり、Ｃｐａｄ≒０．４６ｐＦとなるから、ドレインボンディングパッド１１ａ形成箇所の寄生容量（Ｃｐａｄ）は０．２９ｐＦ減少（３９％削減）される。
【００４６】
なお、本実施形態において、ドレイン電極１１及びドレインボンディングパッド１１ａと、パッシベーション膜１０との間にシリコン窒化膜１５を介在させるようにしたが、上述の全ての実施形態においても適用でき、シリコン窒化膜１５を介在させることによりさらに寄生容量を低減することができる。
【００４７】
また、実施形態４において、ドレインボンディングパッド１１ａ直下の半導体基板１に貫通孔１４を形成するようにしたが、実施形態１〜３，５においても適用でき、これにより絶縁層２による寄生容量成分をなくすことができる。
【００４８】
【発明の効果】
請求項１記載の発明は、半導体基板と半導体基板上に第一の絶縁層を介して形成された第一導電型半導体層とから成るＳＯＩ基板と、第一導電型半導体層の表面に露出するように第一導電型半導体層内に形成された高濃度第一導電型ドレイン領域と、高濃度第一導電型ドレイン領域と離間して囲むとともに、第一導電型半導体層の表面に露出するように第一導電型半導体層内に形成された第二導電型ウェル領域と、第二導電型ウェル領域に内包され、第一導電型半導体層の表面に露出するように第一導電型半導体層内に形成された高濃度第一導電型ソース領域と、高濃度第一導電型ドレイン領域と高濃度第一導電型ソース領域との間に介在する第二導電型ウェル領域上に第二の絶縁層を介して形成された絶縁ゲートと、高濃度第一導電型ソース領域を囲むとともに、第一導電型半導体層の表面から第一の絶縁層に達するように形成された高濃度第二導電型素子分離領域と、高濃度第一導電型ドレイン領域と電気的に接続されたドレイン電極と、ドレイン電極に電気的に接続されたドレインボンディングパッドとを有して成る半導体装置において、ドレイン電極が第三の絶縁層を介して高濃度第二導電型素子分離領域を跨いで外側まで延設され、ドレインボンディングパッドが、高濃度第二導電型素子分離領域を跨いだ外側でドレイン電極と電気的に接続されて成るので、ドレインボンディングパッド直下の第三の絶縁層による容量に、第一の絶縁層による容量と、高濃度第二導電型素子分離領域による容量との並列回路を直列に容量結合することとなり、ドレインボンディングパッドを絶縁ゲート及びソース領域の外側に形成した場合の、ドレインボンディングパッドにより形成される寄生容量を小さくし、かつ、出力容量を低減化することのできる半導体装置を提供することができた。
【００４９】
請求項２記載の発明は、請求項１記載の半導体装置において、高濃度第二導電型素子分離領域を跨いで外側の第一導電型半導体層内に、第一導電型半導体層の表面から第一の絶縁層に達する高濃度第二導電型不純物領域が形成され、高濃度第二導電型不純物領域上に第三の絶縁層を介してドレインボンディングパッドが配置され、高濃度第二導電型不純物領域が高濃度第二導電型素子分離領域と離間して成るので、高濃度第二導電型素子分離領域の接合容量に高濃度第二導電型不純物領域の接合容量が直列結合されることになり、ドレインボンディングパッドにより形成される寄生容量を小さくし、かつ、出力容量を低減化することができる。
【００５０】
請求項３記載の発明は、請求項１記載の半導体装置において、高濃度第二導電型素子分離領域を跨いで外側の第一導電型半導体層内に、第一導電型半導体層の表面から第一の絶縁層に達する高濃度第二導電型不純物領域が形成され、高濃度第二導電型不純物領域内に、絶縁分離されて成る第一導電型半導体領域が形成され、第一導電型半導体領域上に、第三の絶縁層を介してドレインボンディングパッドが配置され、高濃度第二導電型不純物領域が高濃度第二導電型素子分離領域と離間して成るので、高濃度第二導電型素子分離領域の接合容量に、高濃度第二導電型不純物領域の外側及び内側の接合容量が直列に結合されることになり、ドレインボンディングパッドにより形成される寄生容量を小さくし、かつ、出力容量を低減化することができる。
【００５１】
請求項４記載の発明は、請求項１乃至請求項３のいずれかに記載の半導体装置において、ドレインボンディングパッド直下及びその近傍の半導体基板に、第一の絶縁層に達する貫通孔を形成したので、第一の絶縁層による寄生容量成分が無くなり、ドレインボンディングパッドにより形成される寄生容量を小さくし、かつ、出力容量を低減化することができる。
【００５２】
請求項５記載の発明は、請求項１乃至請求項４のいずれかに記載の半導体装置において、少なくともドレインボンディングパッド直下の第三の絶縁層が、シリコン酸化膜とシリコン窒化膜とから成る多層膜で構成されて成るので、シリコン酸化膜による容量と、シリコン窒化膜による容量とが直列に結合されることになり、ドレインボンディングパッドにより形成される寄生容量を小さくし、かつ、出力容量を低減化することができる。
【図面の簡単な説明】
【図１】本発明の一実施形態に係るＳＯＩ構造型のＬＤＭＯＳＦＥＴを示す概略構成図であり、（ａ）は上面から見た状態を示す概略平面図であり、（ｂ）は（ａ）におけるＡーＡ’での概略断面図であり、（ｃ）はドレインボンディングパッド形成箇所の寄生容量の等価回路図である。
【図２】本発明の他の実施形態に係るＳＯＩ構造型のＬＤＭＯＳＦＥＴを示す概略構成図であり、（ａ）は上面から見た状態を示す概略平面図であり、（ｂ）は（ａ）におけるＢーＢ’での概略断面図であり、（ｃ）はドレインボンディングパッド形成箇所の寄生容量の等価回路図である。
【図３】本発明の他の実施形態に係るＳＯＩ構造型のＬＤＭＯＳＦＥＴを示す概略構成図であり、（ａ）は上面から見た状態を示す概略平面図であり、（ｂ）は（ａ）におけるＣーＣ’での概略断面図であり、（ｃ）はドレインボンディングパッド形成箇所の寄生容量の等価回路図である。
【図４】本発明の他の実施形態に係るＳＯＩ構造型のＬＤＭＯＳＦＥＴを示す概略構成図であり、（ａ）は上面から見た状態を示す概略平面図であり、（ｂ）は（ａ）におけるＤーＤ’での概略断面図であり、（ｃ）はドレインボンディングパッド形成箇所の寄生容量の等価回路図である。
【図５】本発明の他の実施形態に係るＳＯＩ構造型のＬＤＭＯＳＦＥＴを示す概略構成図であり、（ａ）は上面から見た状態を示す概略平面図であり、（ｂ）は（ａ）におけるＥーＥ’での概略断面図であり、（ｃ）はドレインボンディングパッド形成箇所の寄生容量の等価回路図である。
【図６】従来例に係る光結合型半導体リレーの一部を示す概略平面配置図である。
【図７】従来例に係る光結合型半導体リレーの概略断面図である。
【図８】従来例に係る光結合型半導体リレーの出力端子間容量の容量成分を示す等価回路図である。
【図９】従来例に係るＳＯＩ構造型のＬＤＭＯＳＦＥＴを示す概略構成図であり、（ａ）は上面から見た状態を示す概略平面図であり、（ｂ）は（ａ）におけるＦーＦ’での概略断面図である。
【図１０】従来例に係るＳＯＩ構造型のＬＤＭＯＳＦＥＴを示す概略構成図であり、（ａ）は上面から見た状態を示す概略平面図であり、（ｂ）は（ａ）におけるＧーＧ’での概略断面図である。
【符号の説明】
１ 半導体基板
２ 絶縁層
３ ｎ型半導体層
４ ｐ＋型素子分離領域
５ ｎ＋型ドレイン領域
６ ｐ型ウェル領域
７ ｎ＋型ソース領域
８ ゲート酸化膜
９ 絶縁ゲート
１０ パッシベーション膜
１１ ドレイン電極
１１ａ ドレインボンディングパッド
１２ ｐ＋型浮遊電位領域
１３ ｎ型半導体領域
１４ 貫通孔
１５ シリコン窒化膜
１６ 太陽電池
１６ａ カソード
１６ｂ アノード
１７ ＭＯＳＦＥＴ
１７ａ ソース電極
１７ｂ ドレイン電極
１７ｃ ゲート電極
１８ ＧＮＤ端子フレーム
１９ ボンディングワイヤ
２０ 出力端子フレーム
２１ 入力端子フレーム
２２ 発光ダイオード
２３ 遮光性樹脂
２４ 透光性樹脂[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an SOI structure type semiconductor device.
[0002]
[Prior art]
In recent years, in optically coupled semiconductor relays in which a light emitting element and a light receiving element are optically coupled and an output power element performs a switching operation by the output of the light receiving element, the output power is reduced in order to reduce the capacitance between output terminals when the relay is off. Attention has been paid to using an SOI (Silicon On Insulator) SOI structure type power semiconductor device as an element. As one type of such a power semiconductor device, there is a lateral double-diffused MOS field-effect transistor, a so-called LDMOSFET (Lateral Double Diffused MOSFET).
[0003]
FIG. 6 is a schematic plan view showing a part of an optically coupled semiconductor relay according to a conventional example. A solar cell 16 as a light receiving element and two output MOSFETs 17 are disposed on a GND terminal frame 18. A cathode 16 a of the solar cell 16 and a source electrode 17 a of the MOSFET 17 are electrically connected to the GND terminal frame 18 by bonding wires 19. It is connected. Thus, the cathode 16a of the solar cell 16 and the source electrode 17a of the MOSFET 17 are electrically connected via the GND terminal frame 18. As the MOSFET 17, an SOI structure type LDMOSFET is used.
[0004]
Further, the output terminal frame 20 arranged in parallel on both sides of the GND terminal frame 18 and the drain electrode 17b of the MOSFET 17 are electrically connected by a bonding wire 19, and the anode 16b of the solar cell 16 and the gate electrode 17c of the MOSFET 17 are bonded. They are electrically connected by wires 19.
[0005]
FIG. 7 is a schematic sectional view of an optically coupled semiconductor relay according to a conventional example. In the optically coupled semiconductor relay, as shown in FIG. 7, a light emitting diode 22 as a light emitting element is disposed on an input terminal frame 21 opposed to a GND terminal frame 18, and the whole is made of a light shielding resin 23. It is molded and packaged. The light from the light emitting diode 22 can be received by the solar cell 16 by being optically coupled between the solar cell 16 and the light emitting diode 22 by a light guide path made of a light transmitting resin 24 that transmits light.
[0006]
The optically coupled semiconductor relay thus configured causes the light emitting diode 22 to emit light by an external drive signal, and the solar cell 16 receiving the light from the light emitting diode 22 generates a voltage, and this voltage reaches a certain level. Then, the output MOSFET 17 is switched, and the optically coupled semiconductor relay is turned on or off.
[0007]
FIG. 8 is an equivalent circuit diagram showing a capacitance component of a capacitance between output terminals of an optically coupled semiconductor relay according to a conventional example. The capacitance between the output terminals is formed by the series combined capacitance of the output capacitances (Coss) of the two SOI structure type LDMOSFETs, and the output capacitance (Coss) is the drain-source capacitance (Cds) and the gate-drain capacitance (Cgd). ) And a parallel combined capacitance of the drain-substrate capacitance (Cdsub).
[0008]
9A and 9B are schematic configuration diagrams showing a conventional SOI structure type LDMOSFET, in which FIG. 9A is a schematic plan view showing a state viewed from above, and FIG. 9B is an FF ′ in FIG. 9A. FIG. In this LDMOSFET, an insulating layer 2 as a first insulating layer such as a silicon oxide film is formed on one main surface of a semiconductor substrate 1 such as single crystal silicon, and a first conductivity type semiconductor layer is formed on the insulating layer 2. The n-type semiconductor layer 3 is formed to constitute an SOI (Silicon On Insulator) substrate.
[0009]
Note that as an example of a method for forming an SOI substrate, an SOI growth method in which single-crystal silicon is grown in each of a gas phase, a liquid phase, and a solid phase on an insulating layer, a bonded SOI method in which a substrate is bonded, a single SOI method, and the like. There are a SIMOX (Separation by Implanted Oxygen) method in which oxygen is ion-implanted into crystalline silicon to form an insulating layer therein, and a method in which silicon is partially made porous by anodic oxidation to be oxidized.
[0010]
In the n-type semiconductor layer 3 of the SOI substrate, a p + -type element isolation region 4 that is a high-concentration second conductivity-type element isolation region is formed so as to reach the insulating layer 2 from the surface. It is divided into a plurality of regions which are insulated and separated by the 2 and p + type element isolation regions 4.
[0011]
Then, an n + -type drain region 5 that is a high-concentration first conductivity type drain region is formed substantially at the center of the n-type semiconductor layer 3 so as to be exposed on the surface of the n-type semiconductor layer 3 that is insulated and separated. The n + type drain region 5 is surrounded so as to be separated from the drain region 5 by a shortest distance capable of maintaining a predetermined withstand voltage, and is formed in the n-type semiconductor layer 3 so as to be exposed on the surface of the n-type semiconductor layer 3. A p-type well region 6 that is a two-conductivity type well region is formed, is included in the p-type well region 6, and is an n + -type source that is a high-concentration first conductivity type source region so as to be exposed on the surface of the n-type semiconductor layer 3. A region 7 is formed.
[0012]
The n + -type drain region 5 and the n + -type source region 7 can be formed by ion-implanting an n-type impurity such as phosphorus (P) and performing an annealing treatment. 6 can be formed by ion implantation and annealing of a p-type impurity such as boron (B).
[0013]
On the p-type well region 6 interposed between the n + -type drain region 5 and the n + -type source region 7, polysilicon or the like is interposed via a gate oxide film 8, which is a second insulating layer having a small thickness. The insulating gate 9 is formed, and a passivation film 10 as a third insulating layer such as a silicon oxide film is formed on the surface of the SOI substrate on which the insulating gate 9 is formed. Here, the insulated gate 9 controls a main current flowing in the n-type semiconductor layer 3 between the n + -type drain region 5 and the n + -type source region 7.
[0014]
Then, a drain electrode 11 made of aluminum (Al) or the like is formed so as to be electrically connected to the n + type drain region 5. On the drain electrode 11 surrounded by the n + type source region 7 and the insulated gate 9, A drain bonding pad 11a is formed. Here, the drain bonding pad 11a usually requires an area of at least 100 μm square (a square of about 100 μm on a side, the same applies to the following) in order to connect to a bonding wire.
[0015]
A source electrode (not shown) made of Al or the like is formed so as to be electrically connected to p-type well region 6 and n + -type source region 7, and Al is formed so as to be electrically connected to insulated gate 9. A gate electrode (not shown) is formed.
[0016]
Here, the drain-substrate capacitance (Cdsub) is a capacitance generated by a potential difference between the drain potential and the GND potential across the insulating layer 2 of the SOI substrate, and is an n-type semiconductor inside the p-type well region 6. This characteristic is proportional to the area of the surface of the layer 3 on the insulating layer 2 side (hereinafter, referred to as the drain area). Therefore, when the drain area is increased, the output capacitance (Coss) is also increased, and the capacitance between the output terminals of the optically coupled semiconductor relay is eventually increased.
[0017]
In recent years, miniaturization of elements has been desired. However, as shown in FIG. 9A, a structure in which a drain bonding pad 11a is formed inside an area surrounded by an n + type source region 7 and an insulated gate 9 is formed. Has a disadvantage that the SOI structure type LDMOSFET cannot be reduced to a pad area or less.
[0018]
As a method for solving this problem, as shown in FIG. 10, the drain electrode 11 is pulled out from the drain electrode 11 inside the p-type well region 6 so as to straddle the insulating gate 9 and the n + -type source region 7, and the drain bonding pad 11a is formed. May be formed outside the insulating gate 9 and the n + -type source region 7. In this case, the drain area inside the p-type well region 6 can be reduced, and the drain-substrate capacitance (Cdsub) can be reduced. Can be smaller. Also, the SOI structure type LDMOSFET can be downsized without depending on the area of the drain bonding pad 11a.
[0019]
[Problems to be solved by the invention]
However, in the above case, there is a problem that a new parasitic capacitance C1 is generated across the passivation film 10 due to a potential difference between the drain bonding pad 11a of the drain electrode 11 and the p + type element isolation region 4 below the drain bonding pad 11a. Was.
[0020]
The present invention has been made in view of the above points, and has as its object the parasitic capacitance formed by a drain bonding pad when the drain bonding pad is formed outside an insulated gate and a source region. And a semiconductor device capable of reducing output capacitance.
[0021]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided an SOI substrate including a semiconductor substrate and a first conductivity type semiconductor layer formed on the semiconductor substrate via a first insulating layer; A high-concentration first-conductivity-type drain region formed in the first-conductivity-type semiconductor layer so as to be exposed, and surrounds the high-concentration first-conductivity-type drain region separately from the first-conductivity-type semiconductor layer. A second conductivity type well region formed in the first conductivity type semiconductor layer so as to be exposed on the surface, and included in the second conductivity type well region so as to be exposed on the surface of the first conductivity type semiconductor layer. A high-concentration first-conductivity-type source region formed in the first-conductivity-type semiconductor layer; and the second high-concentration first-conductivity-type source region interposed between the high-concentration first-conductivity-type drain region and the high-concentration first-conductivity-type source region. Formed on the two-conductivity type well region via the second insulating layer And a high-concentration second-conductivity-type element isolation formed to surround the high-concentration first-conductivity-type source region and reach the first insulation layer from the surface of the first-conductivity-type semiconductor layer. A semiconductor device comprising: a region; a drain electrode electrically connected to the high-concentration first conductivity type drain region; and a drain bonding pad electrically connected to the drain electrode. A third insulating layer extending to the outside across the high-concentration second conductivity type element isolation region, wherein the drain bonding pad extends outside the high-concentration second conductivity type element isolation region; It is characterized by being electrically connected to an electrode.
[0022]
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the first conductive type semiconductor layer is provided in the first conductive type semiconductor layer outside the high-concentration second conductive type element isolation region. A high-concentration second conductivity type impurity region that reaches the first insulating layer from the surface is formed, and the drain bonding pad is arranged on the high-concentration second conductivity type impurity region via the third insulating layer, The high-concentration second conductivity type impurity region is separated from the high-concentration second conductivity type element isolation region.
[0023]
According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the first conductive type semiconductor layer is formed in the first conductive type semiconductor layer outside the high-concentration second conductive type element isolation region. A high-concentration second-conductivity-type impurity region that reaches the first insulating layer from the surface is formed, and a first-conductivity-type semiconductor region that is insulated and separated is formed in the high-concentration second-conductivity-type impurity region. On the first conductivity type semiconductor region, the drain bonding pad is arranged via the third insulating layer, and the high concentration second conductivity type impurity region is separated from the high concentration second conductivity type element isolation region. It is characterized by becoming.
[0024]
According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, a through hole reaching the first insulating layer is formed in the semiconductor substrate immediately below the drain bonding pad and in the vicinity thereof. It is characterized by having been formed.
[0025]
According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, at least the third insulating layer immediately below the drain bonding pad comprises a silicon oxide film and a silicon nitride film. It is characterized by being constituted by a multilayer film.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the first conductivity type will be described as n-type, and the second conductivity type will be described as p-type. However, the first conductivity type can be applied to p-type and the second conductivity type can be applied to n-type. .
[0027]
= Embodiment 1 =
1A and 1B are schematic configuration diagrams showing an SOI structure type LDMOSFET according to an embodiment of the present invention, wherein FIG. 1A is a schematic plan view showing a state viewed from above, and FIG. It is a schematic sectional view in AA ', and (c) is an equivalent circuit diagram of the parasitic capacitance at the formation location of the drain bonding pad 11a. The LDMOSFET according to the present embodiment has a structure in which the drain electrode 11 is drawn out across the p + -type element isolation region 4 and a drain bonding pad 11 a is formed outside the p + -type element isolation region 4 in the LDMOSFET shown in FIG. 10 as a conventional example. It is.
[0028]
In the SOI structure type LDMOSFET according to the present embodiment, the parasitic capacitance (Cpad) at the formation location of the drain bonding pad 11a includes the capacitance C1 of the passivation film 10 immediately below the drain bonding pad 11a, the capacitance C2 of the insulating layer 2, and p + Since a parallel-parallel circuit in which the parallel capacitance with the capacitor C3 formed by the junction with the pattern element isolation region 4 is coupled in series is formed, compared with the case of only the capacitor C1 as described in the related art, the location where the drain bonding pad 11a is formed Has a small parasitic capacitance (Cpad).
[0029]
More specifically, the area of the drain bonding pad 11a is about 145 μm, the thickness of the passivation film 10 immediately below the drain bonding pad 11a is about 1 μm, the thickness of the n-type semiconductor layer 3 is about 2 μm, and the concentration of the n-type semiconductor layer 3. About 7 × 10 Fifteen cm -3 , P + type element isolation region 4 has a concentration of about 1 × 10 18 cm -3 , P + -type element isolation region 4 has a junction area of about 3.4 × 10 -5 cm 2 The thickness of the insulating layer 2 is about 2 μm and the drain area is about 2.9 × 10 -3 cm 2 Therefore, since C1 ≒ 0.75 pF, C2 ≒ 5.0 pF, and C3 ≒ 1.6 pF, and Cpad ≒ 0.65 pF, the parasitic capacitance (Cpad) at the location where the drain bonding pad 11a is formed is reduced by 0.1 pF. (13% reduction).
[0030]
= Embodiment 2 =
2A and 2B are schematic configuration diagrams showing an SOI structure type LDMOSFET according to another embodiment of the present invention, wherein FIG. 2A is a schematic plan view showing a state viewed from above, and FIG. FIG. 3 is a schematic cross-sectional view taken along line BB ′ of FIG. 3, and FIG. The LDMOSFET according to the present embodiment is the same as the LDMOSFET shown in FIG. 1 according to the first embodiment, except that the high-concentration semiconductor is formed in the n-type semiconductor layer 3 below the drain bonding pad 11a and in the vicinity thereof so as to reach the insulating layer 2 from the surface. In this configuration, a p + type floating potential region 12 which is a two-conductivity type impurity region is formed. Here, the p + type floating potential region 12 and the p + type element isolation region 4 are separated from each other.
[0031]
In the SOI structure type LDMOSFET according to the present embodiment, the capacitance C1 by the passivation film 10 at the formation position of the drain bonding pad 11a, the capacitance C4 by the insulating layer 2, the capacitance C5 by the p + type element isolation region 4, and the p + type floating It becomes a series-parallel circuit with the capacitor C6 due to the junction of the potential region 12.
[0032]
Here, in the present embodiment, the junction capacitance C8 of the p + -type floating potential region 12 and the junction capacitance C7 of the p + -type element isolation region 4 are coupled in series, so that the parasitic capacitance (Cpad) at the location where the drain bonding pad 11a is formed. Is smaller than the parasitic capacitance (Cpad) in the second embodiment.
[0033]
More specifically, the area of the drain bonding pad 11a is about 145 μm, the thickness of the passivation film 10 immediately below the drain bonding pad 11a is about 1 μm, the thickness of the n-type semiconductor layer 3 is about 2 μm, and the concentration of the n-type semiconductor layer 3. About 7 × 10 Fifteen cm -3 , P + type element isolation region 4 has a concentration of about 1 × 10 18 cm -3 , P + type floating potential region 12 has an area of about 1.1 × 10 -5 cm 2 The thickness of the insulating layer 2 is about 2 μm and the drain area is about 1.4 × 10 -2 cm 2 Therefore, C1 ≒ 0.75 pF, C4 ≒ 0.55 pF, C5 ≒ 1.6 pF, C6 ≒ 0.34 pF, and Cpad ≒ 0.40 pF, so that the parasitic capacitance (CpadＣ) at the location where the drain bonding pad 11a is formed ) Is reduced by 0.35 pF (47% reduction).
[0034]
= Embodiment 3 =
3A and 3B are schematic configuration diagrams showing an SOI structure type LDMOSFET according to another embodiment of the present invention, wherein FIG. 3A is a schematic plan view showing a state viewed from above, and FIG. FIG. 4 is a schematic cross-sectional view taken along line CC ′ of FIG. 5, and FIG. 4C is an equivalent circuit diagram of a parasitic capacitance at a location where a drain bonding pad 11a is formed. The LDMOSFET according to the present embodiment is different from the LDMOSFET shown in FIG. 2 as the second embodiment in that an n-type semiconductor region 13 which is a first conductivity type semiconductor region composed of an n-type semiconductor layer 3 is formed in a p + type floating potential region 12. The drain bonding pad 11a is formed on the n-type semiconductor region 13 with the passivation film 10 interposed therebetween. Here, the p + type floating potential region 12 and the p + type element isolation region 4 are separated from each other.
[0035]
In the SOI structure type LDMOSFET according to the present embodiment, the capacitance C1 of the passivation film 10 at the location where the drain bonding pad 11a is formed, the capacitance C7 of the insulating layer 2, and the p + type floating potential region 12 on the p + type element isolation region 4 side , A capacitance C9 of the p + -type floating potential region 12 on the n-type semiconductor region 13 side, and a capacitance C5 of the p + -type element isolation region 4 become a series-parallel circuit.
[0036]
Here, in the present embodiment, the junction capacitances C8 and C9 outside and inside the p + type floating potential region 12 are connected in series to the junction capacitance C5 of the p + type element isolation region 4, thereby forming the drain bonding pad 11a. The parasitic capacitance (Cpad) at the location is smaller than the parasitic capacitance (Cpad) in the second embodiment.
[0037]
More specifically, the area of the drain bonding pad 11a is about 145 μm □, the thickness of the passivation film 10 immediately below the drain bonding pad 11a is about 1 μm, the thickness of the n-type semiconductor layer 3 is about 2 μm, and the concentration of the n-type semiconductor layer 3. About 7 × 10 Fifteen cm -3 , P + type element isolation region 4 has a concentration of about 1 × 10 18 cm -3 , P + type floating potential region 12 has an area of about 1.1 × 10 -5 cm 2 The thickness of the insulating layer 2 is about 2 μm and the drain area is about 1.4 × 10 -2 cm 2 Assuming that C1 ≒ 0.75 pF, C7 ≒ 0.55 pF, C5 ≒ 1.6 pF, C8 ≒ 0.34 pF, C9 ≒ 0.34 pF, and Cpad ≒ 0.36 pF, the drain bonding pad 11a is formed. The parasitic capacitance (Cpad) at the location is reduced by 0.39 pF (52% reduction).
[0038]
= Embodiment 4 =
4A and 4B are schematic configuration diagrams showing an SOI structure type LDMOSFET according to another embodiment of the present invention, wherein FIG. 4A is a schematic plan view showing a state viewed from above, and FIG. FIG. 3 is a schematic cross-sectional view taken along line DD ′ of FIG. 3, and FIG. 4C is an equivalent circuit diagram of a parasitic capacitance at a location where a drain bonding pad 11a is formed. The LDMOSFET according to the present embodiment is different from the LDMOSFET shown in FIG. 1 as the first embodiment in that the semiconductor substrate 1 below the drain bonding pad 11a is provided on the back side of the semiconductor substrate 1 (on the side different from the surface on which the passivation film 10 of the SOI substrate is formed). In this configuration, a through hole 14 having a size substantially the same as the size of the drain bonding pad 11a reaching the insulating layer 2 is formed. Here, the opening area of the through hole 14 is equal to or larger than the opening area of the drain bonding pad 11a.
[0039]
The through hole 14 can be formed by wet etching using an anisotropic etchant such as TMAH (Tetra Methyl Ammonium Hydroxide) or dry etching using plasma.
[0040]
In the SOI structure type LDMOSFET according to the present embodiment, since the through hole 14 is formed in the semiconductor substrate 1 immediately below the drain bonding pad 11a, almost no capacitance due to the insulating layer 2 is generated. Is a series coupling of the capacitance C1 formed by the passivation film 10 at the location where the drain bonding pad 11a is formed and the capacitance C3 formed by the p + type element isolation region 4, and only the capacitance C1 as shown in the prior art is obtained. As compared with the case, the parasitic capacitance (Cpad) at the location where the drain bonding pad 11a is formed is smaller.
[0041]
More specifically, the area of the drain bonding pad 11a is about 145 μm, the thickness of the passivation film 10 immediately below the drain bonding pad 11a is about 1 μm, the thickness of the n-type semiconductor layer 3 is about 2 μm, and the concentration of the n-type semiconductor layer 3. About 7 × 10 Fifteen cm -3 , P + type element isolation region 4 has a concentration of about 1 × 10 18 cm -3 , Junction area is about 3.4 × 10 -5 cm 2 Therefore, C1 ≒ 0.75 pF, C3 ≒ 1.6 pF and Cpad ≒ 0.51 pF, so that the parasitic capacitance (Cpad) at the place where the drain bonding pad 11a is formed is reduced by 0.24 pF (32% reduction). You.
[0042]
= Embodiment 5 =
5A and 5B are schematic configuration diagrams showing an SOI structure type LDMOSFET according to another embodiment of the present invention, in which FIG. 5A is a schematic plan view showing a state viewed from above, and FIG. FIG. 4 is a schematic cross-sectional view taken along line EE ′ of FIG. 5, and FIG. 4C is an equivalent circuit diagram of a parasitic capacitance at a formation location of the drain bonding pad 11a. The LDMOSFET according to this embodiment has a configuration in which a silicon nitride film 15 is interposed between the passivation film 10, the drain electrode 11, and the drain bonding pad 11a in the LDMOSFET shown in FIG.
[0043]
In the present embodiment, only the silicon nitride film 15 is interposed between the passivation film 10, the drain electrode 11, and the drain bonding pad 11a. However, the present invention is not limited to this. You may make it intervene.
[0044]
In the SOI structure type LDMOSFET according to the present embodiment, the parasitic capacitance (Cpad) at the location where the drain bonding pad 11a is formed is equal to the capacitance C1 of the passivation film 10 where the drain bonding pad 11a is formed and the parasitic capacitance (Cpad) at the location where the drain bonding pad 11a is formed. A series-parallel circuit of a capacitor C10 formed by the nitride film 15, a capacitor C2 formed by the insulating layer 2, and a capacitor C3 formed by the p + type element isolation region 4.
[0045]
Specifically, the reduction of the parasitic capacitance (Cpad) in this embodiment is as follows: the area of the drain bonding pad 11a is about 145 μm, the thickness of the passivation film 10 immediately below the drain bonding pad 11a is about 1 μm, The thickness is about 2 μm and the concentration of the n-type semiconductor layer 3 is about 7 × 10 Fifteen cm -3 , P + type element isolation region 4 has a concentration of about 1 × 10 18 cm -3 , P + -type element isolation region 4 has a junction area of about 3.4 × 10 -5 cm 2 The thickness of the silicon nitride film 14 is about 0.5 μm, the thickness of the insulating layer 2 is about 2 μm, and the drain area is about 1.4 × 10 -2 cm 2 Therefore, C1 ≒ 0.75 pF, C2 ≒ 0.55 pF, C3 ≒ 1.6 pF, C10 ≒ 2.6 pF, and Cpad ≒ 0.46 pF, so that the parasitic capacitance (Cpad) at the formation location of the drain bonding pad 11 a is obtained. ) Is reduced by 0.29 pF (39% reduction).
[0046]
In this embodiment, the silicon nitride film 15 is interposed between the drain electrode 11 and the drain bonding pad 11a and the passivation film 10. However, the silicon nitride film 15 can be applied to all of the above embodiments. The parasitic capacitance can be further reduced by interposing 15.
[0047]
In the fourth embodiment, the through hole 14 is formed in the semiconductor substrate 1 immediately below the drain bonding pad 11a. However, the through hole 14 can be applied to the first to third and fifth embodiments. Can be eliminated.
[0048]
【The invention's effect】
According to the first aspect of the present invention, an SOI substrate including a semiconductor substrate and a first conductive type semiconductor layer formed on the semiconductor substrate with a first insulating layer interposed therebetween is exposed to a surface of the first conductive type semiconductor layer. As described above, the high-concentration first-conductivity-type drain region formed in the first-conductivity-type semiconductor layer and the high-concentration first-conductivity-type drain region are spaced apart from each other and are exposed on the surface of the first-conductivity-type semiconductor layer. A second conductivity type well region formed in the first conductivity type semiconductor layer, and a first conductivity type semiconductor layer included in the second conductivity type well region so as to be exposed on the surface of the first conductivity type semiconductor layer. A high-concentration first-conductivity-type source region formed on the second-conductivity-type well region interposed between the high-concentration first-conductivity-type drain region and the high-concentration first-conductivity-type source region; Gate and a high-concentration first conductivity type saw A high-concentration second-conductivity-type element isolation region formed so as to surround the region and reach the first insulating layer from the surface of the first-conductivity-type semiconductor layer, and is electrically connected to the high-concentration first-conductivity-type drain region. Device having a drain electrode and a drain bonding pad electrically connected to the drain electrode, the drain electrode straddles the high-concentration second conductivity type element isolation region via the third insulating layer. And the drain bonding pad is electrically connected to the drain electrode outside the high-concentration second conductivity type element isolation region, so that the capacitance by the third insulating layer immediately below the drain bonding pad is formed. In addition, a parallel circuit of the capacitance formed by the first insulating layer and the capacitance formed by the high-concentration second conductivity type element isolation region is capacitively coupled in series. The case of forming on the outside of the insulated gate and the source region, to reduce the parasitic capacitance formed by the drain bonding pad, and it is possible to provide a semiconductor device capable of reducing the output capacitance.
[0049]
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the first conductive type semiconductor layer extends from the surface of the first conductive type semiconductor layer in the outer first conductive type semiconductor layer across the high-concentration second conductive type element isolation region. A high-concentration second-conductivity-type impurity region reaching one insulating layer is formed, and a drain-bonding pad is disposed on the high-concentration second-conductivity-type impurity region via a third insulating layer. Since the region is separated from the high-concentration second-conductivity-type element isolation region, the junction capacitance of the high-concentration second-conductivity-type impurity region is connected in series to the junction capacitance of the high-concentration second-conductivity-type element isolation region. In addition, the parasitic capacitance formed by the drain bonding pad can be reduced, and the output capacitance can be reduced.
[0050]
According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the first conductive type semiconductor layer extends from the surface of the first conductive type semiconductor layer in the outer first conductive type semiconductor layer across the high-concentration second conductive type element isolation region. A high-concentration second-conductivity-type impurity region reaching one insulating layer is formed, and a first-conductivity-type semiconductor region that is insulated and separated is formed in the high-concentration second-conductivity-type impurity region. On top, a drain bonding pad is arranged via a third insulating layer, and the high concentration second conductivity type impurity region is separated from the high concentration second conductivity type element isolation region. The junction capacitance of the isolation region is coupled in series with the junction capacitance outside and inside the high-concentration second conductivity type impurity region, thereby reducing the parasitic capacitance formed by the drain bonding pad and reducing the output capacitance. Can be reduced Kill.
[0051]
According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, a through hole reaching the first insulating layer is formed in the semiconductor substrate immediately below the drain bonding pad and in the vicinity thereof. Since the parasitic capacitance component due to the first insulating layer is eliminated, the parasitic capacitance formed by the drain bonding pad can be reduced, and the output capacitance can be reduced.
[0052]
According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, at least the third insulating layer immediately below the drain bonding pad comprises a silicon oxide film and a silicon nitride film. Therefore, the capacitance of the silicon oxide film and the capacitance of the silicon nitride film are coupled in series, thereby reducing the parasitic capacitance formed by the drain bonding pad and reducing the output capacitance. can do.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram showing an SOI structure type LDMOSFET according to an embodiment of the present invention, wherein FIG. 1 (a) is a schematic plan view showing a state viewed from above, and FIG. It is a schematic sectional view in AA ', and (c) is an equivalent circuit diagram of the parasitic capacitance at the formation position of the drain bonding pad.
FIG. 2 is a schematic configuration diagram showing an SOI structure type LDMOSFET according to another embodiment of the present invention, where (a) is a schematic plan view showing a state viewed from above, and (b) is (a). FIG. 3 is a schematic cross-sectional view taken along line BB ′ of FIG. 3, and FIG. 3C is an equivalent circuit diagram of a parasitic capacitance at a drain bonding pad formation location.
3A and 3B are schematic configuration diagrams showing an SOI structure type LDMOSFET according to another embodiment of the present invention, wherein FIG. 3A is a schematic plan view showing a state viewed from above, and FIG. FIG. 4 is a schematic cross-sectional view taken along line CC ′ of FIG. 5, and FIG. 4C is an equivalent circuit diagram of a parasitic capacitance at a formation position of a drain bonding pad.
4A and 4B are schematic configuration diagrams showing an SOI structure type LDMOSFET according to another embodiment of the present invention, wherein FIG. 4A is a schematic plan view showing a state viewed from above, and FIG. FIG. 3 is a schematic cross-sectional view taken along the line DD ′ in FIG. 3, and FIG. 4C is an equivalent circuit diagram of a parasitic capacitance at a location where a drain bonding pad is formed.
FIG. 5 is a schematic configuration diagram showing an SOI structure type LDMOSFET according to another embodiment of the present invention, where (a) is a schematic plan view showing a state viewed from above, and (b) is (a). FIG. 3 is a schematic cross-sectional view taken along line EE ′ of FIG. 3, and FIG. 4C is an equivalent circuit diagram of a parasitic capacitance at a location where a drain bonding pad is formed.
FIG. 6 is a schematic plan view showing a part of an optically coupled semiconductor relay according to a conventional example.
FIG. 7 is a schematic sectional view of an optically coupled semiconductor relay according to a conventional example.
FIG. 8 is an equivalent circuit diagram showing a capacitance component of a capacitance between output terminals of an optically coupled semiconductor relay according to a conventional example.
9A and 9B are schematic configuration diagrams showing an SOI structure type LDMOSFET according to a conventional example, in which FIG. 9A is a schematic plan view showing a state viewed from the top, and FIG. 9B is FF ′ in FIG. FIG.
FIG. 10 is a schematic configuration diagram showing an SOI structure type LDMOSFET according to a conventional example, (a) is a schematic plan view showing a state viewed from above, and (b) is GG ′ in (a). FIG.
[Explanation of symbols]
1 semiconductor substrate
2 Insulating layer
3 n-type semiconductor layer
4 p + type element isolation region
5 n + type drain region
6 p-type well region
7 n + type source region
8 Gate oxide film
9 Insulated gate
10 Passivation film
11 Drain electrode
11a Drain bonding pad
12 p + type floating potential region
13 n-type semiconductor region
14 Through hole
15 Silicon nitride film
16 Solar cells
16a cathode
16b anode
17 MOSFET
17a Source electrode
17b drain electrode
17c Gate electrode
18 GND terminal frame
19 Bonding wire
20 Output terminal frame
21 Input terminal frame
22 Light emitting diode
23 Shading resin
24 translucent resin

Claims (5)

半導体基板と該半導体基板上に第一の絶縁層を介して形成された第一導電型半導体層とから成るＳＯＩ基板と、該第一導電型半導体層の表面に露出するように前記第一導電型半導体層内に形成された高濃度第一導電型ドレイン領域と、前記高濃度第一導電型ドレイン領域と離間して囲むとともに、前記第一導電型半導体層の表面に露出するように前記第一導電型半導体層内に形成された第二導電型ウェル領域と、該第二導電型ウェル領域に内包され、前記第一導電型半導体層の表面に露出するように前記第一導電型半導体層内に形成された高濃度第一導電型ソース領域と、前記高濃度第一導電型ドレイン領域と前記高濃度第一導電型ソース領域との間に介在する前記第二導電型ウェル領域上に第二の絶縁層を介して形成された絶縁ゲートと、前記高濃度第一導電型ソース領域を囲むとともに、前記第一導電型半導体層の表面から前記第一の絶縁層に達するように形成された高濃度第二導電型素子分離領域と、前記高濃度第一導電型ドレイン領域と電気的に接続されたドレイン電極と、該ドレイン電極に電気的に接続されたドレインボンディングパッドとを有して成る半導体装置において、前記ドレイン電極が第三の絶縁層を介して前記高濃度第二導電型素子分離領域を跨いで外側まで延設され、前記ドレインボンディングパッドが、前記高濃度第二導電型素子分離領域を跨いだ外側で前記ドレイン電極と電気的に接続されて成ることを特徴とする半導体装置。An SOI substrate comprising a semiconductor substrate and a first conductivity type semiconductor layer formed on the semiconductor substrate with a first insulating layer interposed therebetween; and the first conductive type semiconductor layer exposed on the surface of the first conductivity type semiconductor layer. A high-concentration first-conductivity-type drain region formed in the first-conductivity-type semiconductor layer, and surrounding the high-concentration first-conductivity-type drain region so as to be exposed on the surface of the first-conductivity-type semiconductor layer. A second conductivity type well region formed in the one conductivity type semiconductor layer, and the first conductivity type semiconductor layer included in the second conductivity type well region and exposed on the surface of the first conductivity type semiconductor layer. A high-concentration first conductivity type source region formed in the second conductivity type well region interposed between the high-concentration first conductivity type drain region and the high-concentration first conductivity type source region. An insulating gate formed through the second insulating layer, A high-concentration second-conductivity-type element isolation region formed so as to surround the high-concentration first-conductivity-type source region and to reach the first insulating layer from the surface of the first-conductivity-type semiconductor layer; In a semiconductor device having a drain electrode electrically connected to a first conductivity type drain region and a drain bonding pad electrically connected to the drain electrode, the drain electrode forms a third insulating layer. And the drain bonding pad is electrically connected to the drain electrode outside the high-concentration second conductivity type element isolation region. A semiconductor device characterized by being formed. 前記高濃度第二導電型素子分離領域を跨いで外側の前記第一導電型半導体層内に、該第一導電型半導体層の表面から前記第一の絶縁層に達する高濃度第二導電型不純物領域が形成され、該高濃度第二導電型不純物領域上に前記第三の絶縁層を介して前記ドレインボンディングパッドが配置され、前記高濃度第二導電型不純物領域が前記高濃度第二導電型素子分離領域と離間して成ることを特徴とする請求項１記載の半導体装置。The high-concentration second conductivity-type impurity reaching the first insulating layer from the surface of the first conductivity-type semiconductor layer in the outside of the first conductivity-type semiconductor layer across the high-concentration second conductivity-type element isolation region. A region is formed, and the drain bonding pad is disposed on the high concentration second conductivity type impurity region via the third insulating layer, and the high concentration second conductivity type impurity region is 2. The semiconductor device according to claim 1, wherein the semiconductor device is separated from the element isolation region. 前記高濃度第二導電型素子分離領域を跨いで外側の前記第一導電型半導体層内に、該第一導電型半導体層の表面から前記第一の絶縁層に達する高濃度第二導電型不純物領域が形成され、該高濃度第二導電型不純物領域内に、絶縁分離されて成る第一導電型半導体領域が形成され、該第一導電型半導体領域上に、前記第三の絶縁層を介して前記ドレインボンディングパッドが配置され、前記高濃度第二導電型不純物領域が前記高濃度第二導電型素子分離領域と離間して成ることを特徴とする請求項１記載の半導体装置。The high-concentration second conductivity-type impurity reaching the first insulating layer from the surface of the first conductivity-type semiconductor layer in the outside of the first conductivity-type semiconductor layer across the high-concentration second conductivity-type element isolation region. A region is formed, a first conductivity type semiconductor region that is insulated and separated is formed in the high-concentration second conductivity type impurity region, and the third conductivity layer is interposed on the first conductivity type semiconductor region. 2. The semiconductor device according to claim 1, wherein the drain bonding pad is disposed, and the high concentration second conductivity type impurity region is separated from the high concentration second conductivity type element isolation region. 前記ドレインボンディングパッド直下及びその近傍の前記半導体基板に、前記第一の絶縁層に達する貫通孔を形成したことを特徴とする請求項１乃至請求項３のいずれかに記載の半導体装置。4. The semiconductor device according to claim 1, wherein a through hole reaching the first insulating layer is formed in the semiconductor substrate immediately below the drain bonding pad and in the vicinity thereof. 5. 少なくとも前記ドレインボンディングパッド直下の前記第三の絶縁層が、シリコン酸化膜とシリコン窒化膜とから成る多層膜で構成されて成ることを特徴とする請求項１乃至請求項４のいずれかに記載の半導体装置。5. The method according to claim 1, wherein at least the third insulating layer immediately below the drain bonding pad is formed of a multilayer film including a silicon oxide film and a silicon nitride film. Semiconductor device.
JP35257597A 1997-12-22 1997-12-22 Semiconductor device Expired - Fee Related JP3562282B2 (en)

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