JP2943922B2 - Output contact element for semiconductor relay - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output contact element for a semiconductor relay, and more particularly to an output contact element for realizing low capacitance between output terminals of a semiconductor relay suitable for high frequency signal applications.

[0002]

2. Description of the Related Art Conventionally, contact relays such as mechanical relays, mercury relays, and reed relays having metal contacts have been used as relays. However, long-term use increases the on-resistance and increases the mechanical life of the contacts. There are problems such as reliability at the point of possession, power consumption at the point of requiring large input energy for contact opening / closing, and restrictions on miniaturization.

[0003] Therefore, compared to a contact relay, a contactless relay has advantages such as high reliability and long life of contacts, low power consumption due to low driving energy, miniaturization, and high speed operation. Switching to semiconductor relays is underway.

FIG. 13 is a schematic circuit configuration diagram of a semiconductor relay. A light-emitting element 18 emits light in response to a signal on the input side, and is connected between the input terminals I1 and I2. 1
Reference numeral 9 denotes a photovoltaic element optically coupled to the light emitting element 18, which receives a light signal from the light emitting element 18 and generates a photovoltaic power.
20a and 20b are power MOSFETs used as output contact elements for semiconductor relays.
0b are electrically connected to each other, each drain electrode is connected to the output terminals O1 and O2, and the output terminal O
1, O2 is configured to be able to handle both positive and negative signals.

Further, the gate electrodes of the power MOSFETs 20a and 20b are electrically connected to each other, and the conduction / cutoff state is controlled by the photovoltaic power generated by the photovoltaic element 19.
Reference numeral 21 denotes a control circuit connected to the gate electrodes of the power MOSFETs 20a and 20b.
This realizes a cutoff state. In general, the photovoltaic element 19 and the control circuit 21 are integrated to constitute a photoelectric element.

The power which is the output contact element of a semiconductor relay
As the MOSFETs 20a and 20b, so-called vertical double diffused MOSFETs (VDMOSFETs: Vertikal Double Diffused MOSFETs) are used.
T) is used. FIG. 14 is a schematic sectional view showing the VDMOSFET. N- which is a low concentration first conductivity type semiconductor substrate
An n + type drain region 2 which is a high concentration first conductivity type drain region is formed on one main surface of the
On the two main surfaces of the silicon substrate 22, a p-type well region 3, which is a second conductivity type well region, is formed. And
An n + type source region 4 which is a high concentration first conductivity type source region is formed so as to be included in the well region 3.

On the well region 3 (channel region 5) interposed between the silicon substrate 22 and the source region 4 on the two main surfaces of the silicon substrate 22, a gate oxide film 6 as a thin insulating film is formed. A conductive polysilicon film 7, which is a conductive film, is formed through the substrate.

Then, a gate electrode 10 made of aluminum (Al) or the like is formed so as to be electrically connected to polysilicon film 7, and Al or the like is formed so as to be electrically connected to source region 4 and well region 3. A source electrode 9 made of Al is formed, and a drain electrode (not shown) made of Al or the like is formed so as to be electrically connected to the drain region 2.

When the VDMOSFET is conducting, the drain region 2
Then, a current flows in the vertical direction to the source region 4 through the drift region 23 and the channel region 5 which are the silicon substrate 22. The control of the conduction / cutoff state of the VDMOSFET is performed by a voltage applied to a gate electrode 10 electrically connected to the polysilicon film 7.

One of the main applications in which a semiconductor relay is used is a measuring instrument such as an LSI tester. In measurement equipment, by increasing the frequency of transmission signals that conduct or block at output terminals,
In addition to lowering the on-state resistance during conduction between output terminals, there is a demand for lowering the capacitance when shutting off between output terminals.

In a semiconductor relay, there is a trade-off between the on-resistance and the capacitance between output terminals in terms of the performance of a semiconductor element generally used as an output contact element. From this,
The present inventors have proposed an on-resistance (Ro
We propose the product (C × R) of the product of both n) and the capacitance between output terminals (Cout) when the contact is cut off as a performance index of the contact performance, and improve the performance by lowering the C × R of the semiconductor relay, especially by reducing the output capacity. Is being promoted.

The capacitance between the output terminals of a semiconductor relay (Cout)
Is a power MOSFET 2 connected to the output terminal in two anti-series
0a and 20b are connected to each other.
And the output capacitance (Coss) of the VDMOSFET is represented by Coss = Cds + Cgd.

Conventionally, as a method of reducing the capacitance between output terminals, there is a method disclosed in US Pat. FIG.
FIG. 3 is a schematic sectional view showing a VDMOSFET in which the capacitance between output terminals is reduced. This is a configuration in which diodes 24a and 24b for canceling capacitance are added to a normal VDMOSFET, and thereby the gate-drain capacitance (Cgd) can be reduced. However, in this case, the drain-source capacitance (Cds), which is an essential component of the output capacitance, is not reduced.

Here, the drain-source capacitance (Cds)
In order to reduce the occupation area of the well region, a method of increasing the degree of integration of the channel region by using advanced microfabrication technology has been adopted. FIG. 16 is a schematic cross-sectional view showing a type of UMOSFET which is a type of VDMOSFET to which a fine processing technique is introduced. A trench is formed in a silicon substrate 22 on both sides of a well region 3 of a normal VDMOSFET by using a trench etching technique. In this configuration, a polysilicon film 7 is buried and formed in a groove via a gate oxide film 6. This UM
In the OSFET, similarly to the VDMOSFET, in the conductive state, a current flows from the drain region 2 to the source region 4 through the drift region 23 and the channel region 5 in the vertical direction, and the conduction / cutoff state is controlled by a conductive polysilicon film. 7 is performed by a voltage applied to the gate electrode 10 electrically connected to the gate electrode 7.

However, in the case of a VDMOSFET, the PD formed between the well region 3 and the drift region
There is a limit in reducing the N-junction area, and a limit in reducing the drain-source capacitance (Cds). In addition, the gate-drain capacitance (Cgd) of the UMOSFET using the trench etching technique is increased. As a result, in the method of increasing the degree of integration of the channel region 5 by miniaturizing the VDMOSFET, the effect of reducing the on-resistance (Ron) is advanced, but the reduction of the output capacitance (Coss) is limited.

Also, a lateral double diffusion type is used instead of the VDMOSFET.
MOSFET (LDMOSFET: Lateral Double Diffused MOSFET)
Has also been proposed in Japanese Patent Application Laid-Open No. 9-312392. FIG. 17 shows the LDMO
FIG. 2 is a schematic sectional view showing an SFET. This LDMOSFET is a p-type silicon substrate 25 which is a low-concentration second conductivity type semiconductor substrate.
Is formed on one main surface of n-
Type drift region 26 is formed, and n + type drain region 2 which is a high-concentration first conductivity type drain region and p type well region 3 which is a second conductivity type well region so as to be included in drift region 26. Are formed apart from each other, and an n + -type source region 4 which is a high-concentration first conductivity type source region is formed so as to be included in the well region 3.

On a well region 3 (channel region 5) interposed between the drain region 2 and the source region 4 on one main surface of the silicon substrate 25, a thin gate oxide film 6 is interposed. A conductive polysilicon film 7 is formed.

A drain electrode 8, a source electrode 9, and a gate electrode (not shown) made of aluminum (Al) or the like are electrically connected to the drain region 2, the source region 4, and the polysilicon film 7, respectively. Is formed.

In this LDMOSFET, in the conductive state, a current flows laterally through the silicon substrate 25 from the drain region 2 to the source region 4 through the drift region 26 and the channel region 5,
The control of the conduction / cutoff state is performed by a voltage applied to the gate electrode 10 electrically connected to the conductive polysilicon film 7.

[0020]

However, also in the case of an LDMOSFET, a PN junction is formed between the n-type region of the drift region 26 and the p-type region of the channel region 5 in the well region 3, so that fine processing can be performed. Even if introduced, as in the case of VDMOSFET,
Output capacity (Coss) because area reduction is limited
There is a limit to the reduction of

The present invention has been made in view of the above points, and has as its object the on-resistance (Ron) at the time of contact conduction / interruption and the capacitance (Cout) at the time of contact interruption / conduction. The object of the present invention is to provide an output contact element for a semiconductor relay having a low product.

[0022]

According to the first aspect of the present invention,
As an output contact element for a semiconductor relay driven by energy in response to an input signal on the input side, an SOI substrate including a semiconductor support substrate and a semiconductor layer formed on the semiconductor support substrate via an insulating layer; A high-concentration first-conductivity-type drain region and a second-conductivity-type well region formed separately in a layer; a high-concentration first-conductivity-type source region formed in the second-conductivity-type well region; On the layer surface, a conductive film formed via an insulating film on the second conductivity type well region interposed between the high concentration first conductivity type drain region and the high concentration first conductivity type source region, A drain electrode electrically connected to the high concentration first conductivity type drain region; a source electrode electrically connected to the second conductivity type well region and the high concentration first conductivity type source region; Electricity on membrane Rutotomoni used LDMOSFET of SOI structure type having a gas connected to a gate electrode, the semi
The present invention is characterized in that the potential of the conductor supporting substrate is set .

[0023]

[0024] According to a second aspect of the invention, a semiconductor relay output contact element according to claim 1, wherein, in the plane of the front Symbol semiconductor layer, the high-concentration the second conductivity type well region and the first conductivity type drain region Are arranged so that one surrounds the other,
A surrounding region of the high-concentration first conductivity type drain region and the second conductivity type well region is electrically connected to the semiconductor support substrate.

[0025] According to a third aspect of the invention, a semiconductor relay output contact element according to claim 1, wherein, in the plane of the front Symbol semiconductor layer, the high-concentration the second conductivity type well region and the first conductivity type drain region Are arranged so that one surrounds the other,
Of the high-concentration first-conductivity-type drain region and the second-conductivity-type well region, an outer peripheral portion of a surrounding region is surrounded by an element isolation region made of an insulating film reaching the insulating layer from the surface of the semiconductor layer, In the high-concentration first conductivity type drain region and the second conductivity type well region, the enclosed region and the semiconductor layer on the outer peripheral portion of the element isolation region are electrically connected to the semiconductor support substrate. It is a feature.

The invention according to claim 4, in the semiconductor relay output contact element according to claim 1, wherein, in the plane of the front Symbol semiconductor layer, the high-concentration the second conductivity type well region and the first conductivity type drain region Are arranged so that one surrounds the other,
Of the high-concentration first-conductivity-type drain region and the second-conductivity-type well region, an outer peripheral portion of a surrounding region is a conductive-type impurity region different from the surrounding region reaching the insulating layer from the surface of the semiconductor layer. The high-concentration first conductivity type drain region and the second conductivity type well region, wherein the surrounded region and the device isolation region were electrically connected to the semiconductor support substrate. It is characterized by the following.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the first conductivity type will be described as n-type, and the second conductivity type will be described as p-type. However, the first conductivity type is also p-type and the second conductivity type is also n-type. it can.

Embodiment 1 = FIG. 1 shows an SOI structure type LDMOS according to an embodiment of the present invention.
FIG. 2 is a schematic sectional view showing an FET, and FIG.
4 is a schematic surface layout of an FET. S according to the present embodiment
The OI type LDMOSFET uses an SOI (Silicon On Insulator) substrate in which a semiconductor layer 1c is formed on a semiconductor support substrate 1a via a buried oxide film 1b as an insulating film, and the surface of the semiconductor layer 1c of the SOI substrate is used. An n + -type drain region 2 that is a high-concentration first-conductivity-type drain region and a p-type well region 3 that is a second-conductivity-type well region are formed at a distance from each other and included in the well region 3. An n + type source region 4 which is a high concentration first conductivity type source region is formed.

The well region 3 interposed between the drain region 2 and the source region 4 on the surface of the semiconductor layer 1c.
On the (channel region 5), a thin gate oxide film 6 is formed.
A conductive polysilicon film 7 is formed through the gate electrode to have an insulated gate structure.

Then, a drain electrode 8 made of aluminum (Al) or the like is formed so as to be electrically connected to the drain region 2, and from Al or the like so as to be electrically connected to the source region 4 and the well region 3. Source electrode 9 is formed and electrically connected to polysilicon film 7.
A gate electrode 10 made of Al or the like is formed.

This SOI structure type LDMOSFET is mounted on the mounting substrate 1.
1, a source electrode 9 is electrically connected to a cathode electrode (not shown) of the photoelectric device via a mounting substrate 11. In addition, the gate electrode 10 is electrically connected to an anode electrode (not shown) of the photoelectric device to form a semiconductor relay.

In the device of the SOI structure type, between the semiconductor supporting substrate 1a and the diffusion region formed in the semiconductor layer 1c,
A capacitor structure is formed via the buried oxide film 1b, and is added to the output capacitance as inter-substrate capacitance (Csub). Designing the surface layout of the diffusion region in the semiconductor layer 1c and the potential of the semiconductor support substrate 1a in which the inter-substrate capacitance (Csub) is minimized can be achieved by using an SOI structure type LDMOSFET as an output contact element of a semiconductor relay. This is important in realizing a semiconductor relay having a small capacitance between output terminals.

Therefore, in the present embodiment, in addition to the above-described structure, a surface layout of a racetrack shape in which a well region 3 is formed so as to surround the drain region 2 as shown in FIG.

Here, the SOI structure type LDMOSFET shown in FIG.
FIGS. 3 and 4 show an example of the semiconductor relay mounting of FIG. In the semiconductor relay shown in FIG. 3, the same conductive lead frame 1 is used.
2, one photoelectric element chip A in which a photovoltaic element and a control circuit are integrated and two LDMOSFETs B shown in FIG. 1 are die-bonded, and a source electrode 9 of the LDMOSFET B is wire-bonded to a lead frame 12. I have. Further, each drain electrode 8 is wire-bonded to each of the output terminals O1 and O2, and the gate electrode 10 is wire-bonded to the anode electrode A1 of the photoelectric element chip A. Then, the cathode electrode A2 of the photoelectric element chip A
Are wire-bonded to the lead frame 12.

In the semiconductor relay shown in FIG. 4, the SOI structure type LDMOSFET B shown in FIG. 1 is die-bonded on the conductive lead frames 13a and 13b, and the photoelectric element chip A is die-bonded on the conductive lead frame 13c. ing. The source electrode 9 of the LDMOSFET B is wire-bonded to the lead frames 13a and 13b, respectively, and the drain electrode 8 is connected to the output terminals O1 and O2, respectively.
The gate electrode 10 is wire-bonded to the anode electrode A1 of the photoelectric element chip A. Then, the cathode electrode A of the photoelectric element chip A
2 is wire-bonded to the lead frames 13a and 13b.

In this embodiment, the well region 3 is formed so as to surround the drain region 2 as a SOI structure type surface layout. However, the present invention is not limited to this. As shown, the drain region 2 may be formed so as to surround the well region 3.

FIG. 6 shows an SOI structure type LDMOSFET according to the above figure.
FIG. 3 is a schematic diagram showing an example of a semiconductor relay mounted state of FIG. In this semiconductor relay, two SOI structure type LDMOSFETs B shown in FIG. 5 are die-bonded on conductive lead frames 14a and 14b serving also as output terminals O1 and O2, respectively.
The photoelectric element chip A is die-bonded on the conductive lead frame 14c. The source electrode 9 of the LDMOSFET B is directly wire-bonded to the cathode electrode A2 of the photoelectric element chip A, and the gate electrode 10 is directly wire-bonded to the anode electrode A1. And LD
The drain electrode 8 of the MOSFET B is die-bonded to the lead frames 14a and 14b, respectively.

Conventionally, the performance index of a power MOSFET is a characteristic on-resistance (ARon (Ωcm
² ) is commonly used (eg, IEDM'85, pp736
739) is the power M used for the output contacts of semiconductor relays, etc.
Insufficient as an OSFET performance index
Coss × Ron is proposed as a new performance index of OSFET, that is, output contact performance of semiconductor relays.

FIG. 7 shows a VDMOSFET and an SOI structure type LDMOSFET.
Is a graph showing the dependency of the performance index (Coss × Ron) on the breakdown voltage between the drain and the source, with the solid line indicating the LDMOSFET and the wavy line indicating the VDMOSFET. FIG. 7 shows that the SOI structure type LDMOSFET is superior to the VDMOSFET in terms of performance especially in the low breakdown voltage region of several hundred V or less, and the SOI structure type LDMOSFET is used as the output contact element of the semiconductor relay. By doing
It is expected that a semiconductor relay having excellent contact performance will be realized.

However, in the SOI structure type device, a capacitance component (Csub) is generated between the diffusion region or the metal electrode formed in the semiconductor layer 1c and the semiconductor support substrate 1a. That is, the output capacitance (Coss) of the SOI structure type LDMOSFET is expressed as Coss = Cds + Cgd + Csub. Therefore, the outer periphery of the drain region 2 is
In the surface layout surrounded by the circles or the surface layout surrounded by the drain region 2 around the well region 3, the structure of the potential of the semiconductor support substrate 1a that minimizes the capacitance (Csub) between the semiconductor support substrates is provided.

Table 1 shows an example of the results of experiments conducted by the inventors on the output capacitance (Coss) of the SOI type LDMOSFET under various conditions of the semiconductor support substrate potential (Vsub). FIG. 8 is a schematic cross-sectional view of an SOI structure type LDMOSFET under each condition of Table 1.

[0042]

[Table 1]

As is clear from Table 1, the SOI structure type LDM
It can be seen that the output capacity (Coss) of the OSFET varies greatly depending on the condition of the potential of the semiconductor support substrate 1a. To reduce the output capacity, it is extremely important to set the potential of the semiconductor support substrate 1a having the SOI structure. is there.

Further, when a conventional bidirectional conductive MOSFET integrated in a silicon island of a dielectric isolation substrate is used and the source electrode is directly connected to the cathode electrode of the photoelectric device, the MOSFET may be damaged during switching operation. was there.

Therefore, in this embodiment, an SOI structure type LDMOSFET is used as an output contact element of a semiconductor relay. In the SOI structure type LDMOSFET shown in FIG. 1, the source region 4 and the semiconductor support substrate 1a are the same. Since the potential
No capacitance component is generated, and the inter-substrate capacitance generated between the diffusion region in the semiconductor layer 1c and the semiconductor support substrate 1a is only the drain-substrate capacitance (Cdsub) generated by the capacitor structure including the buried oxide film 1b. It is.

In the SOI structure type LDMOSFET shown in FIG. 5, the inter-substrate capacitance (Csub) excludes the central well region 3 because the drain electrode 8 is electrically connected to the mounting substrate 11. No drain-substrate capacitance (Cdsub) is generated over the entire chip area, and source-substrate capacitance (Cdsub)
ssub) only occurs.

Therefore, the SOI structure type LDM shown in FIGS.
In the OSFET, the inter-substrate capacitance added to the output capacitance can be suppressed without providing a special processing technique or a new isolation region.

Further, a one-chip bidirectional conductive SOI structure type L having a structure in which two drain regions are junction-separated is provided.
In a DMOSFET, even if the source electrode is electrically connected directly to the cathode electrode of the photoelectric element, the LDMOSFET does not break down. In this device, there is no problem even if the SOI structure of the semiconductor support substrate is at a floating potential, so that the conventional photoelectric element can also be integrated into a single chip, making it easy to miniaturize the semiconductor relay. it can.

Second Embodiment FIGS. 9 and 10 are schematic sectional views showing an SOI structure type LDMOSFET according to another embodiment of the present invention. LDMO shown in Fig. 9
In the SFET, in the LDMOSFET shown in FIG. 1, the outer periphery of the well region 3 is insulated from the semiconductor layer 1c outside the element isolation region 15 by the element isolation region 15 formed of an insulating film reaching from the surface of the semiconductor layer 1c to the buried oxide film 1b. Separate and drain electrode 8
The semiconductor layer 1c outside the element isolation region 15 and the mounting substrate 11
And the source electrode 9 is directly electrically connected to the cathode electrode (not shown) of the photoelectric device.
An example of a semiconductor relay mounted state of this SOI structure type LDMOSFET is similar to FIG.

The LDMOSFET shown in FIG. 10 is different from the LDMOSFET shown in FIG. 5 in that the outer periphery of the drain region 2 reaches the buried oxide film 1b from the surface of the semiconductor layer 1c.
5, the semiconductor layer 1c outside the element isolation region 15 is insulated and separated, the drain electrode 8 is not electrically connected to the mounting substrate 11, and the source electrode 9 is isolated from the semiconductor layer 1 outside the element isolation region 15.
c and the mounting substrate 11, and the source electrode 9 is electrically connected to the cathode electrode (not shown) of the photoelectric device via the mounting substrate 11. this
An example of a semiconductor relay mounted state of an SOI structure type LDMOSFET is similar to FIGS.

As a method for forming the element isolation region 15, for example, LOCOS (Localized Oxidation of Silicon)
Is formed.

In the LDMOSFET shown in FIG.
And the semiconductor support substrate 1a have the same potential, so that no capacitance component is generated, and the diffusion region in the semiconductor layer 1c is
The inter-substrate capacitance (Csub) generated between the buried oxide film 1b
Is the source-substrate capacitance (Cssub) generated by the capacitor structure consisting of: The source-substrate capacitance (Cssub) generated in the normal structure is a region over the entire chip region excluding the region surrounded by the well region 3.
An extremely large inter-substrate capacitance (Csub) is added to the output capacitance (Coss).

Therefore, in the present embodiment, the well region 3 is formed with a minimum width that does not affect the electrical characteristics of the SOI structure type LDMOSFET, and the outer periphery of the well region 3 is formed by the element isolation region 15 by the element isolation region 15. By isolating from the outside, the area of the well region that governs the source-substrate capacitance (Cssub) can be minimized. In addition,
The same effect can be obtained in the case of FIG.

Third Embodiment FIGS. 11 and 12 are schematic sectional views showing an SOI structure type LDMOSFET according to another embodiment of the present invention. Shown in FIG.
In the LDMOSFET shown in FIG. 9, an element isolation region 16 which is a first conductivity type impurity region is formed instead of the element isolation region 15 formed by LOCOS, and the drain electrode 8 is connected to the element isolation region 16 and the mounting substrate. 11 is electrically connected. An example of a semiconductor relay mounted state of this SOI structure type LDMOSFET is similar to FIG.

The LDMOSFET shown in FIG. 12 is different from the LDMOSFET shown in FIG. 10 in that an element isolation region 17 which is a second conductivity type impurity region is formed instead of the element isolation region 15 formed by LOCOS. A configuration in which the source electrode 9 is electrically connected to the element isolation region 17 and the mounting substrate 11, and the source electrode 9 is electrically connected to the cathode electrode (not shown) of the photoelectric device via the mounting substrate 11. It is. An example of a semiconductor relay mounted state of this SOI structure type LDMOSFET is similar to FIGS.

In the LDMOSFET shown in FIG. 11, since the drain region 2 and the semiconductor supporting substrate 1a have the same potential, no capacitance component is generated, and the diffusion region in the semiconductor layer 1c and the semiconductor supporting substrate 1a do not.
The inter-substrate capacitance (Csub) generated between the buried oxide film 1
This is the source-substrate capacitance (Cssub) generated by the capacitor structure consisting of b. The source-substrate capacitance (Cssub) generated in the normal structure is a region over the entire region of the chip excluding the region surrounded by the well region 3, and an extremely large substrate-substrate capacitance (Csub) is the output capacitance (Cos).
s).

Therefore, in this embodiment, the well region 3 is formed with a minimum width which does not affect the electrical characteristics of the SOI structure type LDMOSFET, and the outer periphery of the well region 3 is formed by the element isolation region 16 by the element isolation region 16. Insulated from outside 16
Since the element isolation region 16 has the same potential as the semiconductor support substrate 1a, no inter-substrate capacitance (Csub) is generated, and the area of the well region that controls the source-substrate capacitance (Cssub) can be minimized. The same effect can be obtained in the case of FIG.

[0058]

According to the first aspect of the present invention, an output contact element for a semiconductor relay driven by energy in response to an input signal on an input side is formed on a semiconductor support substrate and an insulating layer on the semiconductor support substrate. Semiconductor layer
An SOI substrate, a high-concentration first-conductivity-type drain region and a second-conductivity-type well region formed separately in the semiconductor layer;
A high-concentration first-conductivity-type source region formed in the second-conductivity-type well region, and between the high-concentration first-conductivity-type drain region and the high-concentration first-conductivity-type source region on the semiconductor layer surface. A conductive film formed on the intervening second conductivity type well region via an insulating film, and a drain electrode electrically connected to the high-concentration first conductivity type drain region;
An SOI structure type LDMOSFET having a source electrode electrically connected to the second conductivity type well region and the high-concentration first conductivity type source region, and a gate electrode electrically connected to the conductive film is used. And the power of the semiconductor support substrate
In this case , low on-resistance can be realized with low inter-output capacitance in low-voltage area, and application development for high-frequency signals is possible.
An output contact element for a semiconductor relay having a low product of n) and the capacity (Cout) at the time of contact interruption / conduction can be provided.

[0059]

[0060] According to a second aspect of the invention, a semiconductor relay output contact element according to claim 1, wherein, in the plane of the front Symbol semiconductor layer, the high-concentration the second conductivity type well region and the first conductivity type drain region Are arranged so that one surrounds the other,
Since the surrounding region of the high-concentration first-conductivity-type drain region and the second-conductivity-type well region is electrically connected to the semiconductor support substrate, the same effect as that of claim 1 is obtained.

[0061] According to a third aspect of the invention, a semiconductor relay output contact element according to claim 1, wherein, prior Symbol in the plane of the semiconductor layer, the high-concentration the a first conductivity type drain region second conductivity type well region Are arranged so that one surrounds the other,
Of the high-concentration first-conductivity-type drain region and the second-conductivity-type well region, an outer peripheral portion of a surrounding region is surrounded by an element isolation region made of an insulating film reaching the insulating layer from the surface of the semiconductor layer, Of the high-concentration first conductivity type drain region and the second conductivity type well region, since the enclosed region and the semiconductor layer on the outer periphery of the element isolation region were electrically connected to the semiconductor support substrate, An effect similar to the effect described in claim 1 is obtained.

[0062] The invention of claim 4, wherein, in the semiconductor relay output contact element according to claim 1, wherein, in the plane of the front Symbol semiconductor layer, the high-concentration the second conductivity type well region and the first conductivity type drain region Are arranged so that one surrounds the other,
Of the high-concentration first-conductivity-type drain region and the second-conductivity-type well region, an outer peripheral portion of a surrounding region is a conductive-type impurity region different from the surrounding region reaching the insulating layer from the surface of the semiconductor layer. The high-concentration first conductivity type drain region and the second conductivity type well region, wherein the surrounded region and the device isolation region were electrically connected to the semiconductor support substrate. since, the same effects as claim 1, wherein is obtained.

[Brief description of the drawings]

FIG. 1 shows an SOI structure type LDMOS according to an embodiment of the present invention.
FIG. 3 is a schematic cross-sectional view showing a FET.

FIG. 2 is a schematic surface layout of the LDMOSFET according to the above figure.

FIG. 3 is a schematic view showing an example of a semiconductor relay mounted state of the SOI structure type LDMOSFET shown in FIG. 1;

FIG. 4 is a schematic view showing an example of a semiconductor relay mounted state of the SOI structure type LDMOSFET shown in FIG. 1;

FIG. 5 is an SOI structure type LDM according to another embodiment of the present invention.
FIG. 3 is a schematic sectional view showing an OSFET.

FIG. 6 is a schematic view showing an example of a semiconductor relay mounting state of the SOI structure type LDMOSFET according to the above figure.

Fig. 7 Performance index (C for VDMOSFET and SOI structure type LDMOSFET)
6 is a graph showing the dependence of the drain-source breakdown voltage on the voltage (oss × Ron).

8 is a schematic cross-sectional view of an SOI structure type LDMOSFET under each condition of Table 1. FIG.

FIG. 9 is an SOI structure type LDM according to another embodiment of the present invention.
FIG. 3 is a schematic sectional view showing an OSFET.

FIG. 10 shows an SOI structure type L according to another embodiment of the present invention.
FIG. 3 is a schematic sectional view showing a DMOSFET.

FIG. 11 shows an SOI structure type L according to another embodiment of the present invention.
FIG. 3 is a schematic sectional view showing a DMOSFET.

FIG. 12 shows an SOI structure type L according to another embodiment of the present invention.
FIG. 3 is a schematic sectional view showing a DMOSFET.

FIG. 13 is a schematic circuit configuration diagram of a semiconductor relay.

FIG. 14 is a schematic sectional view showing a VDMOSFET.

FIG. 15 is a schematic sectional view showing a VDMOSFET in which the capacitance between output terminals is reduced.

FIG. 16: UM, a type of VDMOSFET incorporating microfabrication technology
FIG. 3 is a schematic sectional view showing an OSFET.

FIG. 17 is a schematic sectional view showing an LDMOSFET.

[Explanation of symbols]

Reference Signs List A photoelectric element chip A1 anode electrode A2 cathode electrode B LDMOSFET O1, O2 output terminal 1a semiconductor support substrate 1b buried oxide film 1c semiconductor layer 2 drain region 3 well region 4 source region 5 channel region 6 gate oxide film 7 polysilicon film 8 Drain electrode 9 Source electrode 10 Gate electrode 11 Mounting substrate 12, 13a to 13c, 14a to 14c Lead frame 15, 16, 17 Element isolation region 18 Light emitting element 19 Photovoltaic element 20a, 20b Power MOSFET 21 Control circuit 22 Silicon substrate 23 Drift region 24a, 24b Diode 25 Silicon substrate 26 Drift region

Continuing on the front page (72) Inventor Yoshifumi Shirai 1048 Kadoma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Works, Ltd. Nishiro 1048, Kazuma Kadoma, Kadoma City, Osaka Prefecture, Japan Matsushita Electric Works, Ltd. (72) Inventor Takeshi Yoshida 1048, Kazuma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Works, Ltd. (56) References JP-A-9-92821 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 29/78 H01L 31/12 H03K 17/78

Claims (4)

(57) [Claims] 1. An output contact element for a semiconductor relay driven by energy in response to an input signal on an input side,
An SOI substrate including a semiconductor support substrate and a semiconductor layer formed on the semiconductor support substrate via an insulating layer; a high-concentration first-conductivity-type drain region and a second conductive type formed separately in the semiconductor layer; Mold well region, a high concentration first conductivity type source region formed in the second conductivity type well region, and a high concentration first conductivity type drain region and the high concentration first conductivity type source on the semiconductor layer surface. A conductive film formed on an insulating film on the second conductivity type well region interposed between the region, a drain electrode electrically connected to the high-concentration first conductivity type drain region, a source electrode electrically connected to the second conductivity type well region and a heavily doped first conductivity type source region, Ru using LDMOSFET of SOI structure type having a gate electrode electrically connected to the conductive film And
An output contact element for a semiconductor relay , wherein the potential of the semiconductor support substrate is set . In wherein the plane of the front Symbol semiconductor layer, the high-concentration one of said the first conductive type drain region second conductivity type well region is disposed so as to surround the other, the high-concentration first-conductivity-type among the drain region and the second conductivity type well region, a semiconductor relay output contact element according to claim 1, wherein a region surrounding the electrically connected to the semiconductor support substrate. In 3. plane before Symbol semiconductor layer, the high-concentration one of said the first conductive type drain region second conductivity type well region is disposed so as to surround the other, the high-concentration first-conductivity-type Of the drain region and the well region of the second conductivity type, an outer peripheral portion of the surrounding region is surrounded by an element isolation region formed of an insulating film reaching the insulating layer from the surface of the semiconductor layer, and the high-concentration first conductivity type. among the drain region and the second conductivity type well region, according to claim 1, wherein the said semiconductor layer of the outer peripheral portion of the isolation region and the enclosed area that connects the semiconductor support substrate electrically Output contact element for semiconductor relay. Wherein in the plane of the front Symbol semiconductor layer, the high-concentration one of said the first conductive type drain region second conductivity type well region is disposed so as to surround the other, the high-concentration first-conductivity-type Of the drain region and the second conductivity type well region, the outer peripheral portion of the surrounding region is surrounded by an element isolation region formed of a different conductivity type impurity region from the surrounding region reaching the insulating layer from the surface of the semiconductor layer. And wherein the enclosed region and the element isolation region of the high concentration first conductivity type drain region and the second conductivity type well region are electrically connected to the semiconductor support substrate. 2. The output contact element for a semiconductor relay according to 1 .