JPH1065150A - Dmos fet - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently absorb a current which flows through a drift channel and reduce on resistance by forming a drain layer at a position deeper than a drift layer. SOLUTION: In a case where a drift channel length LD and an appropriate concentration value of a drift layer 151 of the DMOS FET are already determined, to further reduce the on resistance, a current path must be enlarged. If the DMOS FET is of horizontal type, an n-type semiconductor drain layer 152a is provided at a position deeper than the drift layer 151. That is, in this case, the surface of the drain layer 152a is at a position a deeper than the surface of the drain layer 152, by an amount d. As a result of this, the same effect as that which is obtained in a case where the areas of the drift channel and the source region are increased can be found. Accordingly, a larger amount of current can be passed between a source electrode 157 and a drain electrode 153 at this time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral DMOS FET switch element used for a switching power supply or a semiconductor relay, and more particularly, to a structure for reducing on-resistance without changing the element size.

[0002]

2. Description of the Related Art FIG. 14 shows an example of a circuit diagram of a semiconductor relay in which a lateral DMOS FET is used as a switching element. An LED 141 converts an input signal applied to the IN1 and IN2 terminals into light. 142 is LE
D141 is a voltage output type photodiode array that receives the generated optical signal and converts it into an electric signal. LED1
41, it is electrically insulated from the input signal source. 143a and 143b are DMOSs that, when the output signal of the voltage output type photodiode array 142 is received by the gate G, the state between the drain D and the source S is turned on or off.
FET. Two are connected in the opposite direction to obtain bidirectional conduction. The resistance between the drain D and the source S when the DMOS FET is conductive is called on-resistance. 14
Reference numeral 4 denotes a control circuit connected in parallel between the gate G and the source S to discharge the charge accumulated in the gate G. The control circuit 144 is configured using a thin film resistor or the like so as not to generate a parasitic transistor. Next, the operation of this semiconductor relay will be described. When an input signal is applied to the IN1 and IN2 terminals, a constant current is generated in the photodiode array 142 via the LED 141 due to the photoelectric effect. All of this current flows into the gate G. When the gate capacitance is charged and a voltage exceeding the threshold value of the DMOS FET is applied to the gate, the DMOS FET reaches the ON state, and the low impedance state between the source S and the drain D is maintained. Therefore, a current determined by the on-resistance can flow between the output terminals OUT1 and OUT2. When transmitting a measurement signal as an input signal, it is desirable that the on-resistance between the source S and the drain D be as small as possible. When a DMOS FET is used for a switching power supply, a sufficient withstand voltage and a particularly low on-resistance are required to reduce power loss.

FIG. 15 is a sectional view of a conventional lateral DMOS FET. 150 is a p-type silicon substrate. Fifteen
Reference numeral 1 denotes an n-type semiconductor drift layer. Reference numeral 152 denotes an n-type semiconductor drain layer. 153 is a drain electrode connected to the drain layer 152. Reference numeral 154 denotes a silicon oxide film (SiO ₂ ) formed by the Locos process. It may be simply called Locos. 155 is the substrate 1
50 is a p-base layer formed inside. p base 15
5 and the drain electrode 153 are called a drift channel length. In the figure, it is indicated by L _D. Although withstand higher the L _D is greater is greater on-resistance increases. If the concentration of the drift channel is increased in order to reduce the on-resistance, the depletion layer is difficult to extend and the breakdown voltage is reduced. Therefore, the optimum value is determined in combination with increasing the width of the drift channel (in the direction perpendicular to the drawing). Reference numeral 156 denotes an n-type semiconductor source layer formed in the p base layer 155. 157 is a source layer 156
Are connected to the source electrode. 158 is a p base layer 1
55 to the drift layer 151.
The gate electrode is formed through the gate electrode 54. 159 is an insulating protective film. The drain D, source S, and gate G described with reference to FIG.
Corresponds to the source electrode 157 and the gate electrode 158. In the figure, the surface of the drain layer 152 is set as a reference point of the digging dimension for convenience of later description, and is indicated by a. DMOS F
ET drift channel length L _D and drift layer 151
In order to further reduce the on-resistance when the optimum value of the concentration has already been determined, it is necessary to increase the chip size in order to secure a current path. As the chip size increases, the package size also increases, resulting in a decrease in the mounting density. In addition, the cost is increased.

FIG. 16 is a simulation graph showing a drain current for a conventional drain. The drain layer 152 has a normal depth of 1 μm and the drift layer 151.
Have a thickness of 4 μm, a thickness of about 10 μm up to the bottom of the substrate, and a width (in a direction perpendicular to the drawing) of 1 μm. Calculating the case where 0V is applied to the source electrode 157, 10V is applied to the gate electrode 158, and 0.2V is applied to the drain electrode 153, the current flowing between the source electrode 157 and the drain electrode 153 is 1.986 × 10 ⁻⁶ A. .

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to sufficiently optimize the drift channel length Ld and the drift channel concentration so that a predetermined lateral breakdown voltage can be obtained and the on-resistance is minimized by the conventional lateral DMOS FET. In case,
Still another object is to further reduce the on-resistance.

[0006]

The present invention focuses on the following points. In order to reduce the on-resistance of the lateral DMOS FET, generally, the width of the gate is increased to enlarge the current path and reduce the on-resistance. Accordingly, the drift channel, the source region, and the like also increase and the chip size increases. Therefore, the same effect as increasing the area by digging the drift layer to a deeper position without increasing the area of the drift channel and the source region is obtained. A lateral DMOS FET according to the present invention includes: a semiconductor drift layer and a p base layer formed on one surface of a silicon substrate; a drain layer formed on a free surface side of the drift layer; and a free surface of the p base layer. Lateral DM including a source layer formed on the side and a gate electrode provided via a silicon oxide film from the p base layer to the drift layer.
In the OSFET, the drain layer is formed at a position dug deeper in the drift layer to reduce on-resistance.

[0007]

FIG. 1 is a structural sectional view of a lateral DMOS FET showing one embodiment of the present invention. The reference numerals are common to all the drawings. 150 is a p-type silicon substrate. 1
Reference numeral 51 denotes an n-type semiconductor drift layer. 152a is an n-type semiconductor drain layer. This part is a conventional DMOS
It is provided at a position deeper in the drift layer 151 than in the FET. 153 is a drain electrode connected to the drain layer 152. Reference numeral 154 denotes a silicon oxide film SiO ₂ formed by the Locos process. Simply Locos
Sometimes called. 155 is a p base layer formed in the substrate 150. p base 155 and drain electrode 1
The length between them is called the drift channel length. In the figure, it is indicated by L _D. Although withstand higher the L _D is greater is greater on-resistance increases. As the concentration of the drift channel is increased in order to lower the on-resistance, the depletion layer is less likely to extend and the breakdown voltage is reduced. Therefore, the optimum value is determined in combination with increasing the width of the drift channel (in the direction perpendicular to the drawing). 156
Is a source layer of an n-type semiconductor formed in the p base layer 155. 157 is a source electrode connected to the source layer 156. 158 is a gate electrode formed from the p base layer 155 to the drift layer 151 via the oxide film 154. 159 is an insulating protective film. The drain D, source S, and gate G described with reference to FIG.
Correspond to the drain electrode 153, the source electrode 157, and the gate electrode 158. In the drawing, the reference point of the depth of the surface of the drain layer 152 is indicated by a, based on the same reference as in FIG.

FIG. 2 is an enlarged sectional view of the structure near the drain layer 152 in FIG. This indicates that the surface of the drain layer 152a of the present invention is located at a position dug down from the surface of the drain layer 152 of the conventional example indicated by a. FIG. 3 is a simulation graph showing the drain current with respect to the depth d of the drain layer 152a according to the present invention. The depth of the drain layer 152a is 2 μm, the thickness of the drift layer 151 is 4 μm, about 10 μm up to the bottom of the substrate, and their width (in the direction perpendicular to the drawing) is 1 μm. When a case where 0 V is applied to the source electrode 157, 10 V is applied to the gate electrode 158, and 0.2 V is applied to the drain electrode 153 as in the case of FIG. 15, the current flowing between the source electrode 157 and the drain electrode 153 is 2.069. × 10 ^-6 A. If other conditions are the same, about 4% more current can flow than the conventional lateral DMOS FET shown in FIG.

FIG. 4 is a simulation graph showing the rate of decrease in on-resistance with respect to the depth d of the drain layer. It can be seen that when the depth d exceeds a certain value, the on-resistance rapidly decreases. Next, the horizontal DMOS of the present invention
The outline of the manufacturing process of the FET will be described. The manufacturing process proceeds according to the drawing numbers. FIG. 5 is a sectional view showing the formation of the drift layer and the Locos oxide film. p-type silicon substrate 150
A drift layer 151 by ion implantation. A thick silicon dioxide film (Lo) is formed thereon by a Locos process.
cos). FIG. 6 is a cross-sectional view showing the photo-etching of the Locos oxide film in the drain portion. A photoresist is applied except for a position where a drain layer is to be formed.
FIG. 7 is a cross-sectional view after the etching of the Locos oxide film. The oxide film in the portion where the drain layer is not coated with the photoresist in the previous step and which is intended for the drain layer is dug down by etching. Then, the photoresist is removed. Here, in the case of manufacturing a conventional DMOS FET, it is sufficient to proceed to the step of FIG.

The following steps are the steps of digging down the drain layer, which is a feature of the present invention. FIG. 8 is a cross-sectional view showing the photo-etching of the Locos oxide film. A photoresist is applied to the substrate manufactured in the process of FIG. FIG. 9 is a cross-sectional view illustrating re-etching of the drift layer by photo-etching. The portion of the drift layer where the drain layer is to be formed is etched again by a predetermined value d and the thickness of the drain layer, and is dug down. FIG. 10 is a sectional view from which the resist has been removed. FIG.
FIG. 3 is a cross-sectional view illustrating formation of a gate electrode. A portion where the drain layer and the source layer of the substrate processed in the process of FIG. 7 or 10 are to be selectively oxidized by the Locos process to form an oxide film. Further, a polysilicon gate electrode is formed at a predetermined position. This process can use a generalized Si gate process. FIG. 12 is a sectional view showing the formation of the p base. A p base layer is formed by ion implantation. FIG. 13 is a cross-sectional view showing the formation of the N ⁺ source region. An N ⁺ drain layer and a source layer are formed by implanting As ions or the like. Next, a drain electrode and a source electrode are formed on both of these layers by a method such as Al-sputtering with Si or dry etching, and after the steps of hydrogen annealing and application of an insulating protective film, the horizontal DMOS FET shown in FIG. Complete.

[0011]

According to the present invention, the current flowing through the drift channel can be efficiently absorbed by digging the N ⁺ region of the drain extraction layer of the lateral type DMOSFET, so that the on-resistance is reduced. Drain extraction N
Approximately 4% reduction in on-resistance due to 2μm deepening of ⁺ area
Could be lowered.

[Brief description of the drawings]

FIG. 1 shows a lateral DMOS FE according to an embodiment of the present invention.
FIG. 3 is a structural sectional view of T.

FIG. 2 is an enlarged sectional view of a structure near a drain layer in FIG. 1;

FIG. 3 is a simulation graph showing a drain current with respect to a depth of a drain layer.

FIG. 4 is a simulation graph showing a rate of decrease in on-resistance with respect to a depth of a drain layer.

FIG. 5 is a sectional view showing the formation of a drift layer and a Locos oxide film.

FIG. 6 is a cross-sectional view showing photoetching of a Locos oxide film in a drain portion.

FIG. 7 is a cross-sectional view after the Locos oxide film is etched.

FIG. 8 is a cross-sectional view showing photoetching of a Locos oxide film.

FIG. 9 is a cross-sectional view illustrating re-etching of the drift layer by photo-etching.

FIG. 10 is a sectional view from which a resist has been removed.

FIG. 11 is a cross-sectional view showing the formation of a gate.

FIG. 12 is a sectional view showing formation of a P base.

FIG. 13 is a cross-sectional view showing the formation of an N ⁺ source region.

FIG. 14 is a circuit diagram of a semiconductor relay.

FIG. 15 is a cross-sectional view of a conventional lateral DMOS FET.

FIG. 16 is a simulation graph showing a drain current for a conventional drain.

[Explanation of symbols]

 141 LED 142 Photodiode array 143a, 143b DMOS FET 144 Control circuit 151 Drift layer 152, 152a Drain layer 153 Drain electrode 154 Silicon dioxide film (Locos) 155 P base layer 156 Source layer 157 Source electrode 158 Gate electrode 159 Intermediate insulating protective film

Claims (1)

[Claims] 1. A drift layer and a p base layer of a semiconductor formed on one surface of a silicon substrate, a drain layer formed on a free surface side of the drift layer, and a free layer side of the p base layer. The drain layer is formed at a position where the drift layer is dug deeper in a lateral DMOS FET including the source layer thus formed and a gate electrode provided via a silicon oxide film from the p base layer to the drift layer. A DMOS FET having a reduced on-resistance.