TWI385802B - High-voltage metal-oxide semiconductor device and fabrication method thereof - Google Patents

Description

High voltage MOS device and manufacturing method thereof

The present invention relates to a high voltage MOS device and a method of fabricating the same, and more particularly to a high voltage MOS device having a vertical well region and a method of fabricating the same.

Among power semiconductor components, metal oxide half field effect transistors (MOSFETs) have high switching speed, low switching loss, and low drive loss, and are widely used for high frequency power conversion. However, as the voltage value required for power semiconductor components increases, the on-resistance increases rapidly, and the proportion of conduction loss is greatly increased, which greatly limits its application.

As shown in Figures 1 and A, the on-resistance (R _DS(on) ) of a conventional high-voltage MOS field-effect transistor is mainly caused by the resistance value of the drift zone (including R _ch , R _a , and R _epi ) decided. Moreover, the voltage blocking capability of the MOS field effect transistor is mainly determined by the distance of the drift region and the doping concentration. In order to improve the voltage blocking capability, it is necessary to increase the thickness of the epitaxial layer and reduce the doping concentration thereof, however, it causes a disproportionate increase in the on-resistance value.

The metal oxide half-field effect transistors with different withstand voltages also have different proportions in the on-resistance. As shown in the figure, for a gold-voltage half-field effect transistor with a withstand voltage of 30V, the epitaxial layer resistance (R _epi ) is only 29% of the total on-resistance; however, the gold-oxygen half-field effect voltage with a withstand voltage of 600V For crystals, the epitaxial layer resistance accounts for 96.5% of the total on-resistance.

In order to reduce the on-resistance of the high-voltage gold-oxygen half-field effect transistor. One method is to increase the cross-sectional area of the transistor to reduce the on-resistance. However, this method leads to a decrease in the positivity of the transistor element, resulting in an increase in cost. Another method is to introduce a minority carrier to conduct electricity to reduce the on-resistance. However, this side In addition to the method, the switching speed is reduced, and a tail current is generated, resulting in an increase in switching loss.

Since the foregoing two methods have their application defects, how to design a high-voltage MOS device not only has low on-resistance but also high voltage blocking capability is a problem to be solved in the field.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high voltage MOS device and a method of fabricating the same, which can effectively reduce on-resistance to reduce wear and have high voltage blocking capability.

Other objects and advantages of the present invention will become apparent from the technical features disclosed herein.

One embodiment of the present invention provides a high voltage MOS device. The high voltage MOS device includes a body of a first conductivity type, a conductive structure, a first well region of a second conductivity type, a source doped region of a first conductivity type, and a second conductivity type Well area. The conductive structure has a first extension and a second extension. The first extension extends from the upper surface of the body toward the interior of the body. The second extension extends along the upper surface of the body. The first well zone is located within the body, below the second extension, and the first well zone is spaced apart from the first extension by a predetermined distance. The source doping region is located in the first well region. The second well region is located within the body and extends from the bottom of the first extension to a vicinity of a drain doped region.

In an embodiment of the invention, the first extension is connected to the second extension and the second extension is connected to a gate.

In an embodiment of the invention, a dielectric layer is disposed between the first extension portion and the second extension portion, the first extension portion is connected to a gate, and the second extension portion is electrically connected to the source doping region. .

The invention also provides a method for fabricating a high voltage MOS device, comprising the steps of: (a) providing a substrate of a first conductivity type; and (b) fabricating a first epitaxial layer of a first conductivity type on the substrate. (c) defining a doping range in the first epitaxial layer by using a mask, and implanting ions of the second conductivity type into the first epitaxial layer to form a first doped region; (d) Repeating the foregoing steps (b) and (c) for at least one cycle; (e) fabricating a second epitaxial layer on the first epitaxial layers; (f) fabricating a first doped region at the top of the trench exposure; g) forming a conductive structure on the second epitaxial layer, the conductive structure having a first extension portion and a second extension portion, the first extension portion is located in the trench, and the second extension portion is along the second epitaxial layer Extending the surface above the layer; (h) masking the conductive structure, implanting ions of the second conductivity type into the second epitaxial layer to form a plurality of first well regions, and the first well region and The first extension is spaced apart by a predetermined distance; (i) defining a position of the source by using a mask, and implanting ions of the first conductivity type into the first well region to constitute a plurality of source doped regions; (j) depositing a dielectric layer, and forming a plurality of contact windows in the dielectric layer, exposing the source doped region and the first well region under the dielectric layer; (k) A second conductivity type ion is implanted through the dielectric layer in the first well region to form a plurality of heavily doped regions of the second conductivity type below the contact windows.

Another embodiment of the present invention provides a high voltage MOS device. The high voltage MOS device includes a first conductivity type body, a gate conductive layer, two second conductivity type first well regions, two first conductivity type source doped regions and a second conductive The second well area of the type. Wherein, the gate conductive layer extends along the upper surface of the body. The first well regions of the two second conductivity types are located within the body and correspond to opposite side edges of the gate conductive layer. The source doping regions of the two first conductivity types are respectively located in the two first well regions and correspond to the lower sides of the opposite side edges of the gate conductive layer. The second well pattern of the second conductivity type is located in the body and extends from below the gate conductive layer to a vicinity of a substrate. This second well is electrically connected to a gate Extreme or a source. The second well zone is separated from the two first well sections by a predetermined distance. Moreover, the distance between the second well region and the gate conductive layer is greater than the depth of the first well region.

Another embodiment of the present invention provides a method of fabricating a high voltage MOS device. The manufacturing method comprises the steps of: (a) providing a substrate; (b) fabricating a first epitaxial layer of a first conductivity type on the substrate; (c) using a photomask on the first epitaxial layer Defining a doping range, and implanting ions of the second conductivity type into the first epitaxial layer to form a first doped region; (d) repeating the foregoing steps (b) and (c) for at least one cycle; (e) fabricating a second epitaxial layer on the first epitaxial layers, the first doped regions are thermally expanded and interconnected to form a vertical well region; (f) a second conductive type of protective ring is formed In the second epitaxial layer, an active region is defined, and the position of the guard ring overlaps with the position of the vertical well region; (g) a gate conductive layer is formed on the upper surface of the second epitaxial layer, and the alignment is vertical a well region; (h) implanting a second conductivity type ion in the second epitaxial layer with the gate conductive layer as a mask, and driving the ions of the second conductivity type to form a plurality of first well regions, The first well zone and the vertical well zone are respectively separated by a predetermined distance, and at the same time, in the step of advancing, the range of the protection ring is downwardly expanded and connected to the vertical well zone. (i) using a mask to define the position of the source and implanting ions of the first conductivity type into the first well region to form a plurality of source doped regions; (j) depositing a dielectric layer and Forming a plurality of contact windows in the dielectric layer, exposing the source doped regions under the dielectric layer to the first well region; (k) implanting ions of the second conductivity type into the first well region through the dielectric layer And forming a plurality of heavily doped regions of the second conductivity type in the first well region.

The above summary and the following detailed description are exemplary in order to further illustrate the scope of the claims. Other objects and advantages of the present invention will be described in the following description and drawings.

Second and second B are schematic views of a preferred embodiment of the high voltage MOS device of the present invention. The following is an example of an N-type MOS field effect transistor (MOSFET). As shown in the figure, the high voltage MOS device has an N-type epitaxial layer 120, a conductive structure 150, a P-type first well 160, an N-type source doped region 170 and A P-type second well region 130. The N-type epitaxial layer 120 is disposed on an N-type substrate 110 as the body of the high-voltage MOS device. The N-type substrate 110 is electrically connected to a drain D, which can be regarded as a drain-doped region of the N-type MOS device. The conductive structure 150 is located on the N-type epitaxial layer 120. The conductive structure 150 is T-shaped and has a first extending portion 152 and a second extending portion 154. The first extension portion 152 extends from the upper surface of the N-type epitaxial layer 120 toward the inside of the N-type epitaxial layer 120. The second extension portion 154 extends along the upper surface of the N-type epitaxial layer 120. The conductive structure 150 is electrically connected to a gate G.

The P-type first well region 160 is located within the N-type epitaxial layer 120 and is located below the second extension 154 of the conductive structure 150. Moreover, the first well region 160 is spaced apart from the first extension 152 of the conductive structure 150 by a predetermined distance. That is, there is an N-type epitaxial layer 120 between the P-type first well region 160 and the first extension portion 152. The N-type source doped region 170 is located within the P-type first well region 160 and corresponds to the lower portion of the second extension 154 of the conductive structure 150. The source doping region 170 is electrically connected to a source S. Further, a P-type first well region 160 is provided between the N-type source doped region 170 and the N-type epitaxial layer 120.

The P-type second well region 130 is located within the N-type epitaxial layer 120 and extends downward from the bottom of the first extension 152 to the vicinity of the N-type substrate 110. It should be noted that the bottom of the second well region 130 of the P-type is separated from the N-type substrate 110 under the P-type substrate by a certain thickness of the N-type epitaxial layer 120, and this P The second well region 130 is not in direct contact with the first extension 152. In a preferred embodiment, at least an oxide layer 140 is spaced between the P-type second well region 130 and the first extension portion 152. However, the P-type second well region 130 is adjacent to the first extension portion 152, ensuring that the potential of the second well region 130 is affected by the potential of the first extension portion 152. In addition, an N-type epitaxial layer 120 of sufficient width must be left between the P-type second well region 130 and the P-type first well region 160 as a conductive path when the MOS device is turned on.

As shown in FIG. 2A, when the voltage difference (VGS) of the gate G of the gate of the MOS device is less than a threshold voltage (VTH), the N-type source doped region 170 and the N-type epitaxial layer are formed. No channels are created in the P-type first well region 160 between the layers 120. At this time, if a forward bias is applied between the drain D (corresponding to the N-type substrate 110) and the source S (corresponding to the source doped region 170), in the P-type first well region 160 (electrically connected to the source) The range of the depletion region between the pole S) and the N-type epitaxial layer 120 (electrically connected to the drain D) is increased (as indicated by the dashed line in the figure).

Meanwhile, when the MOS device is turned off, the potential of the gate G (corresponding to the conductive structure 150) is substantially equal to the potential of the source S (corresponding to the source doping region 170). Therefore, when the forward bias between the drain D and the source S is increased, the P-type second well region 130 (which is electrically connected to the gate G through the conductive structure 150) and the N-type epitaxial layer 120 (electrically connected) The range of the depletion zone between the bungee D) will also increase (as indicated by the dotted line in the figure). The aforementioned depletion region formed between the first well region 160 and the epitaxial layer 120 and between the second well region 130 and the epitaxial layer 120 may pinch off the conductive path between the source doping region 170 and the N-type substrate 110. . Since the depletion region has excellent voltage blocking capability, the withstand voltage of the MOS device can be greatly improved.

As shown in FIG. B, when the voltage difference (VGS) between the gate G and the source S is greater than a threshold voltage (VTH), the P-type between the N-type source doping region 170 and the N-type epitaxial layer 120 is shown. Within the first well region 160 (ie, corresponding to the lower portion of the second extension 154) Generate a channel. At this time, the electrons of the source doping region 170 can enter the depletion region through the channel, and restore the electrical properties of the N-type epitaxial layer 120 to form a conductive path. As shown by the arrows in the figure, the conductive path is from the source doping region 170 below the second extension portion 154, and then to the side of the first extension portion 152 and the second well region 130 vertically downward. To the N-type substrate 110.

In a preferred embodiment, as shown in the figures, the width of the second well region 130 is greater than the width of the first extension portion 152 to avoid the epitaxial layer 120 between the second well region 130 and the first well region 160. The thickness of the epitaxial layer 120 is too high, and the time required for the epitaxial layer 120 to restore conductivity when the component is turned on. Moreover, the upper edge of the second well region 130 covers the bottom of the first extension portion 152. Further, the MOS device of the present invention focuses on its high withstand voltage characteristics, and the withstand voltage value of the MOS device has a positive correlation with the extension distance of the second well region 130. Therefore, in practical terms, the extension distance of the second well region 130 is much larger than the length of the first extension portion 152.

Although the foregoing embodiments are described by taking a high voltage MOS field effect transistor as an example, the scope of application of the present invention is not limited to a MOS field effect transistor. The present invention only needs to change the N-type substrate 110 used in the prior embodiment to a P-type substrate, that is, to form an insulated gate bipolar transistor (IGBT).

The third figure is a schematic view of another preferred embodiment of the high voltage MOS device of the present invention. Different from the embodiment of the second embodiment, the first extension 152' and the second extension 154' of the conductive structure 150' of the embodiment have a dielectric layer 156, such as an oxide layer, to make the first extension. The portion 152' and the second extension portion 154' are electrically separated from each other. Moreover, the second extension 154' of the conductive structure 150' is electrically connected to the gate G, and the first extension 152' is electrically connected to the source S.

In the high voltage MOS device of the second figure, the potential of the second well region 130 is affected by the gate G. In contrast, the second well region 130 of the embodiment The potential is affected by the source S. However, when the voltage difference (VGS) between the gate G and the source S is less than the threshold voltage (VTH), as in the embodiment of the second figure, the present embodiment is in the P-type first well region 160 and the N-type epitaxial layer 120. Between the P-type second well region 130 and the N-type epitaxial layer 120, a depletion region is also formed to pinch off the conductive path between the source doped region 170 and the N-type substrate 110, thereby providing excellent voltage blocking capability.

The fourth to fourth H diagrams show a preferred embodiment of the method of fabricating the high voltage MOS device of the present invention. The following is an example of a fabrication process of an N-type MOS device. As shown in FIG. 4A, first, an N-type substrate 210 is provided. Then, as shown in FIG. 4B, an N-type first epitaxial layer 220a is formed on the substrate 210, and a photoresist pattern is formed on the first epitaxial layer 220a by using a mask (not shown). The layer PR defines a doping range and implants P-type ions in the first epitaxial layer 220a to form a P-type first doping region 230a.

Next, as shown in FIG. 4C, the fabrication steps of the fourth B-graph are repeated for at least one cycle, and the number of repetitions is positively correlated with the high-low voltage value of the high-voltage MOS device to be fabricated. The MOS element fabricated in the present embodiment has a withstand voltage of 600 V. Therefore, the fabrication steps of the fourth B pattern are repeated six times, and six layers of the first epitaxial layer 220a are stacked on the substrate 210, and correspondingly The six first epitaxial layers 220a, in the stack of the first epitaxial layer 220a, also have six first doped regions 230a.

It is worth noting that the fabrication steps of Figure 4B must use a reticle to define the doping range. In this embodiment, the first doping region 230a is formed in each of the first epitaxial layers 220a using the same mask, and the first doping region formed in each of the first epitaxial layers 220a is Align in the vertical direction. In addition, since the high temperature process is involved in the fabrication step of the epitaxial layer, the range of the first doped region 230a is enlarged by the subsequent epitaxial layer fabrication step. As the fourth As shown in FIG. C, in the present embodiment, by appropriately controlling the implantation depth of the dopant of the first doping region 230a, the implantation concentration, and the thickness of the corresponding first epitaxial layer 220a, The first doped regions 230a in an epitaxial layer 220a overlap each other to form a single P-type vertical well region 230 (this P-type vertical well region 230 corresponds to the second well region 130 of the second A and B-pictures) ). However, the P-type vertical well region 230 remains at a distance from the substrate 210 below it.

Then, as shown in FIG. 4D, an N-type second epitaxial layer 220b is formed on the first epitaxial layer 220a, and the second epitaxial layer 220b and the first epitaxial layer 220a form an epitaxial whole. Layer 220 serves as the body of the MOS device. Then, a trench 248 is formed to expose the uppermost first doped region 230a, that is, the upper edge of the P-type vertical well region 230 formed by exposing the first doped regions 230a. Next, at the same time, as shown in FIG. E, an oxide layer 240 is formed to cover the exposed surface of the second epitaxial layer 220b. A polycrystalline germanium layer (not shown) is then deposited altogether and fills the trench 248. Next, the position of the conductive structure 250 is defined by a mask, and the excess polysilicon layer is etched away to form the polysilicon conductive structure 250 on the second epitaxial layer 220b. The conductive structure has a first extension 252 and a second extension 254. The first extension 252 is located in the trench 248, and the second extension 254 extends along the upper surface of the second epitaxial layer 220b.

Next, as shown in the fourth F diagram, the conductive structure 250 is directly used as a mask, and P-type ions are implanted into the second epitaxial layer 220b to form a plurality of P-type first well regions 260. The P-type first well region 260 is spaced apart from the first extension portion 252 by a predetermined distance. That is, an N-type second epitaxial layer 220b is interposed between the first well region 260 and the first extension portion 252. It should be noted that the P-type first well region 260 and the P-type vertical well region 230 under the first extension portion 252 sandwich an N-type epitaxial layer of sufficient width as a guide for conducting the MOS device. Electrical passage.

Subsequently, as shown in the fourth G diagram, a photoresist pattern layer PR is formed on the first well region 260 by using a mask (not shown) to define the position of the source doping region 270 and implanted into the N-type. Ions are within the first well region 260 to form a plurality of source doped regions 270 within the first well region 260. Next, as shown in FIG. H, a dielectric layer 280 is deposited, and a plurality of contact windows 282 are formed in the dielectric layer 280 to expose the source doping region 270 and the first well under the dielectric layer 280. Area 260. Then, P-type ions are implanted into the first well region 260 through the dielectric layer 280 to form a plurality of P-type heavily doped regions 290 in the first well region 260.

As shown in the fourth H, in the foregoing embodiment, each of the first doping regions 230a formed on the epitaxial layer 220 overlap each other to form a vertical well region 230. However, the invention is not limited thereto. As shown in the fifth figure, the first doping regions 330a formed in the epitaxial layer 220 may also be separated from each other. However, the spacing distance of each of the first doping regions 330a must not be too large to ensure that the potentials of the respective first doping regions 330a can sense each other.

6A to 6E are views showing a manufacturing process of another preferred embodiment of the high voltage MOS device of the present invention. Taking the step of the fourth D diagram, as shown in FIG. A, a first oxide layer 241 is formed to cover the exposed surface of the second epitaxial layer 220b. A first polysilicon layer is then deposited altogether and fills the trench 248. Next, the etch back removes the excess first polysilicon layer leaving only the first extension 352 of the conductive structure 350 comprised of polysilicon material within the trench 248.

Next, as shown in FIG. BB, a second oxide layer 242 is formed to cover the exposed surface of the first extension portion 352. Then, a second polysilicon layer is deposited over the entire surface of the second oxide layer 242. Next, a photomask (not shown) is used to define the position of the second extension portion 354, and the excess second polysilicon layer is etched away to form A second extension 354 of conductive structure 350 formed of a polycrystalline germanium material.

Next, as shown in FIG. C, the second extension portion 354 is directly used as a mask, and P-type ions are implanted into the second epitaxial layer 220b to form a plurality of P-type first well regions 260. Subsequently, as shown in FIG. 6D, a photoresist pattern layer PR is formed on the first well region 260 by a photomask (not shown) to define the position of the source doping region 270 and implanted into the N-type. Ions are within the first well region 260 to form a plurality of source doped regions 270 within the first well region 260. Next, as shown in FIG. 6E, a dielectric layer 280 is deposited, and a plurality of contact windows 282 are formed in the dielectric layer 280 to expose the source doping region 270 and the first well under the dielectric layer 280. Area 260. Then, P-type ions are implanted into the first well region 260 through the dielectric layer 280 to form a plurality of P-type heavily doped regions 290 in the first well region 260.

It should be noted that the first extension portion 352 and the second extension portion 354 which are formed through the steps of the sixth and sixth panels are separated from each other. In a preferred embodiment, the second extension 354 can be electrically connected to the gate G to control the operation of the MOS device. The first extension 352 can be electrically connected to the source S. In order to electrically connect the first extension 352 to the source S, in a preferred embodiment, as shown in the seventh figure, the dielectric layer 280 may be adjacent to the edge of the high voltage MOS device. An opening 284 is formed, the first extending portion 352 is exposed, and then the first extending portion 352 is electrically connected to the first extending portion 352 and the source doping region 270 by using a source metal layer 295. Source S.

Figure 8 is a schematic view of still another preferred embodiment of the high voltage MOS device of the present invention. In the figure, a high voltage MOS field effect transistor is taken as an example. As shown in the figure, the high voltage MOS device has an N-type epitaxial layer 120, a gate conductive layer 450, two P-type first well regions 160, two N-type source doping regions 170 and a P-type second well zone 130. Wherein, the N-type epitaxial layer 120 is located in an N-type The substrate 110 serves as a body of the high voltage MOS device. The gate conductive layer 450 extends along the upper surface of the N-type epitaxial layer 120. Two P-type first well regions 160 are located within the N-type epitaxial layer 120 and correspond to opposite sides of the gate conductive layer 450. The two P-type first well regions 160 are spaced apart by a certain distance.

The two N-type source doping regions 170 are respectively located in the two P-type first well regions 160 and are located below the opposite side edges of the gate conductive layer 450. The P-type second well region 130 is located in the N-type epitaxial layer 120 and extends downward from the gate conductive layer 450 to the vicinity of the N-type substrate 110. The N-type substrate 110 can be regarded as an N-type drain-doped region. The P-type second well region 130 and the two P-type first well regions 160 are respectively spaced apart by a predetermined distance. The second well region 130 is electrically connected to a gate G or a source S. Moreover, in a preferred embodiment, the distance between the second well region 130 and the gate conductive layer 450 is greater than the depth of the first well region 160.

Referring to FIGS. 9A and 9B, in order to electrically connect the second well region 130 to the gate G or the source S of the high voltage MOS device, in a preferred embodiment, the high voltage gold can be utilized. A guard ring 460 at the edge of the oxygen semiconductor component is used as a medium for electrical connection. As shown, the P-type guard ring 460 is located within the N-type body and surrounds the P-type first well region 160 located within the active region A. The depth of the guard ring 460 is greater than the depth of the P-type first well region 160. The P-type second well region 130 extends from the active region A of the high voltage MOS device to below the guard ring 460 to interface with the guard ring 460.

As shown in FIG. 9A, in order to electrically connect the P-type second well region 130 connected to the guard ring 460 to the source S, the present embodiment has an opening 186 formed in the dielectric layer 180 to expose the guard ring 460. Also, a source metal layer 195 is deposited on the dielectric layer 180 while being connected to the source doping region 170 and the guard ring 460 to The guard ring 460 is electrically connected to the source S. As shown in FIG. BB, in order to electrically connect the P-type second well region 130 connected to the guard ring 460 to the gate G, the present embodiment directly utilizes the gate conductive layer 450' of the active region A edge. The gate conductive layer 450' is extended to the upper surface of the guard ring 460 to be connected to the guard ring 460 to electrically connect the guard ring 460 to the gate G.

The tenth through tenth through tenth Cth drawings show a preferred embodiment of the method of fabricating the MOS device of the eighth embodiment together with the guard ring 460 thereof. The step of the fourth C is carried out. As shown in FIG. 10A, after the second epitaxial layer 220b is formed, a P-type guard ring 460 is formed in the second epitaxial layer 220b to define an active region A. Viewed from above the second epitaxial layer 220b, the location of the guard ring 460 overlaps with the location of the P-type vertical well region 230 (i.e., the second well region 130 corresponding to the eighth map) located within the epitaxial layer 220. . Subsequently, a gate conductive layer 450 is formed on the upper surface of the second epitaxial layer 220b and aligned with the vertical well region 230.

Next, as shown in FIG. 10B, the gate conductive layer 450 is used as a mask, P-type ions are implanted into the second epitaxial layer 220b, and the P-type ions are driven to form a plurality of P-types. First well zone 260. The P-type first well regions 260 and the P-type vertical well regions 230 are respectively spaced apart by a predetermined distance. It is worth noting that in the step of driving the P-type ions, the P-type ions in the guard ring 460 are also diffused downward, and the range of the guard ring 460 is expanded downward to be connected to the P-type vertical well region 230.

Subsequently, as shown in the tenth C-picture, the position of the source is defined by a mask, and N-type ions are implanted in the first well region 260 to form a plurality of source-doped regions 270. Then, a dielectric layer 280 is deposited, and a plurality of contact windows 282 are formed in the dielectric layer 280 to expose the source doping region 270 and the first well region 260 under the dielectric layer 280. Next, P-type ions are implanted into the first well region 260 through the dielectric layer 280 to form a P-type heavily doped region 290 within the first well region 260.

The high voltage MOS device of the present invention has the following advantages: first, as shown in the second A and B diagrams, when the voltage difference (VGS) between the gate G and the source S is less than a threshold voltage (VTH), if A forward bias is applied between the drain D and the source S, and a N-type epitaxial layer 120 is completely blocked between the first well region 160 and the second well region 130. This depletion region has excellent voltage blocking capability, so that the withstand voltage of the MOS device can be greatly improved. On the other hand, when the voltage difference (VGS) between the gate G and the source S is greater than a threshold voltage (VTH), the first well region 160 between the source doping region 170 and the N-type epitaxial layer 120 will Create a channel. At this time, the electrons of the source doping region 170 can enter the depletion region through the channel, and restore the electrical properties of the N-type epitaxial layer 120 to form a conductive path. Basically, by appropriately increasing the doping concentration of the N-type epitaxial layer 120, excellent on-resistance can be obtained, and the conduction loss can be reduced.

Next, as shown in FIG. 2A, the depletion region formed by the high voltage MOS device of the present invention when turned off is located between the first well region 160 and the second well region 130. The separation distance between the first well region 160 and the second well region 130 is typically less than the separation distance of the gates of adjacent MOS devices. Therefore, after the high voltage MOS device of the present invention is turned off, the speed of filling electrons to the depletion region to return to the conduction state is superior to that of the conventional high voltage MOS device having a lateral PN junction, such as CoolmosTM and Super junction semiconductor components. .

In addition, as shown in FIG. 2A, the high voltage MOS device of the present invention has an intrinsic Zener diode between the heavily doped region 190, the first well region 160 and the N-type epitaxial layer 120. The body also has a Zener diode between the second well region 130 and the N-type epitaxial layer 120. When an avalanche breakdown occurs, the breakdown current is not completely concentrated in the heavily doped region 190, the Zener diode between the first well region 160 and the N-type epitaxial layer 120. Therefore, the high voltage MOS device of the present invention can reduce the lateral resistance flowing under the second extension 154 The current can further prevent the bipolar junction transistor formed between the N-type epitaxial layer 120 and the P-type first well region 160 and the source doping region 170 from being damaged due to excessive current.

As described above, the present invention fully complies with the three requirements of the patent: novelty, advancement, and industrial applicability. The invention has been described above in terms of the preferred embodiments, and it should be understood by those skilled in the art that the present invention is not intended to limit the scope of the invention. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be included within the scope of the present invention. Therefore, the scope of the invention is defined by the scope of the following claims.

110‧‧‧Substrate

120‧‧‧N type epitaxial layer

130‧‧‧P type second well area

140‧‧‧Oxide layer

150,150’‧‧‧Electrical structure

152,152’‧‧‧First Extension

154,154’‧‧‧ Second Extension

156‧‧‧ dielectric layer

450,450'‧‧‧ gate conductive layer

160‧‧‧P type first well area

170‧‧‧ source doped area

180‧‧‧ dielectric layer

186‧‧‧ openings

190‧‧‧P type heavily doped area

195‧‧‧ source metal layer

D‧‧‧汲

G‧‧‧ gate

S‧‧‧ source

460‧‧‧guard ring

A‧‧‧active area

210‧‧‧Substrate

220‧‧‧N type epitaxial layer

220a‧‧‧N type first epitaxial layer

220b‧‧‧N type second epitaxial layer

PR‧‧‧resist pattern layer

230a, 330a‧‧‧P type first doped region

230‧‧‧P type vertical well area

248‧‧‧ Ditch

240‧‧‧Oxide layer

241‧‧‧First oxide layer

242‧‧‧Second oxide layer

250,350‧‧‧Electrical structure

252,352‧‧‧First extension

254,354‧‧‧Second extension

260‧‧‧P type first well area

270‧‧‧ source doped area

280‧‧‧ dielectric layer

282‧‧‧Contact window

284‧‧‧ openings

290‧‧‧P type heavily doped area

295‧‧‧ source metal layer

The first and the first graphs show the difference in the proportion of the respective portions of the overall on-resistance of the gold-oxygen half-field effect transistor with different withstand voltage; the second and second B diagrams are preferably the high-voltage MOS device of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a schematic cross-sectional view showing another preferred embodiment of the high voltage MOS semiconductor device of the present invention; and FIGS. 4A to 4H are diagrams showing a preferred embodiment of the method for fabricating the high voltage MOS device of the present invention. 5 is a schematic cross-sectional view showing still another preferred embodiment of the high voltage MOS device of the present invention; and FIGS. 6A to 6E are diagrams showing another preferred embodiment of the method for fabricating the high voltage MOS device of the present invention; 7 is a schematic view of a preferred embodiment of the first extension of the sixth embodiment of the invention, wherein the first extension is electrically connected to the source doped region; and the eighth embodiment is a further preferred embodiment of the high voltage MOS device of the present invention. FIG. 9 is a cross-sectional view of a preferred embodiment of the second well region electrically connected to the source in the eighth diagram; and the second well region in the eighth diagram is electrically connected to the second well region. A schematic cross-sectional view of a preferred embodiment of the gate; and a preferred embodiment of the method of fabricating the high voltage MOS device of the eighth embodiment and the protection ring of the eighth embodiment.

110‧‧‧Substrate

120‧‧‧N type epitaxial layer

130‧‧‧P type second well area

140‧‧‧Oxide layer

150‧‧‧Electrical structure

152‧‧‧First Extension

154‧‧‧Second extension

160‧‧‧P type first well area

170‧‧‧ source doped area

180‧‧‧ dielectric layer

190‧‧‧P type heavily doped area

D‧‧‧汲

G‧‧‧ gate

S‧‧‧ source

Claims (36)

A high voltage MOS device includes: a first conductivity type body; a conductive structure having a first extension portion and a second extension portion, the first extension portion being oriented from the upper surface of the body toward the body Internally extending, the second extension extends along the upper surface of the body; a first well region of a second conductivity type is located within the body, below the second extension, and the first well The first extension is spaced apart from the first extension by a predetermined distance, wherein the length of the first extension is greater than the depth of the first well; a source doped region of the first conductivity type is located in the first well region; And a second well region of the second conductivity type is located in the body and extends from a bottom of the first extension portion to a vicinity of a drain doping region. The high voltage MOS device of claim 1, wherein the first extension is connected to the second extension. A high voltage MOS device according to claim 2, wherein the conductive structure is connected to a gate. The high voltage MOS device of claim 1, wherein the first extension portion and the second extension portion have a dielectric layer, and the first extension portion is electrically connected to the source doping region. The second extension is electrically connected to a gate. The high voltage MOS device of claim 1, wherein the second well region has a length greater than a length of the first extension. The high voltage MOS device of claim 1, wherein the drain doping region is located at the bottom of the body. The high voltage MOS device according to claim 1, wherein the conductive structure is T-shaped. The high voltage MOS device of claim 1, wherein the second well region is spaced apart from the first extension by at least one oxide layer, and the electrical property of the second well region It is affected by the potential of the first extension. The high voltage MOS device of claim 1, wherein the width of the second well region is greater than the width of the first extension portion. The high voltage MOS device of claim 1, wherein the upper edge of the second well region covers the bottom of the first extension. The high voltage MOS device of claim 1, wherein the ruthenium doped region is of a first conductivity type. The high voltage MOS device according to claim 1, wherein the drain doping region is a second conductivity type. A high voltage MOS device includes: a first conductivity type body; a gate conductive layer extending along an upper surface of the body; and a second conductivity type first well region located in the body Corresponding to opposite side edges of the gate conductive layer; two source-doped regions of the first conductivity type are respectively located in the two first well regions, and are located on opposite sides of the gate conductive layer a second well region of a second conductivity type, electrically connected to a gate or a source, and located in the body, extending from a lower direction of the gate conductive layer to a vicinity of a substrate, The second well zone is spaced apart from the two first well sections by a predetermined distance, and the second well zone is spaced apart from the gate conductive layer by a distance greater than the depth of the first well zone. The high voltage MOS device of claim 14, wherein the high voltage MOS device further comprises a second conductivity type protection ring disposed in the body and surrounding the first well regions, the protection ring The depth is greater than the depth of the first well region, and the lower edge of the guard ring is in contact with the second well region. The high voltage MOS device of claim 15, wherein the guard ring is electrically connected to the source through a source metal layer. The high voltage MOS device of claim 15, wherein the guard ring is electrically connected to the gate through the gate conductive layer. The high voltage MOS device according to claim 14, wherein the substrate is of a first conductivity type. The high voltage MOS device according to claim 14, wherein the substrate is of a second conductivity type. A method for fabricating a high voltage MOS device, comprising: (a) providing a substrate; (b) fabricating a first epitaxial layer of a first conductivity type on the substrate; (c) using a photomask Defining a doping range in the first epitaxial layer, and implanting ions of the second conductivity type into the first epitaxial layer to form a first doped region; (d) repeating the foregoing steps (b) and ( c) at least one cycle; (e) fabricating a second epitaxial layer of a first conductivity type on the first epitaxial layers; (f) fabricating the first doped region at the top of a trench exposure; Forming a conductive structure on the second epitaxial layer, the conductive structure having a first extension portion and a second extension portion, the first extension portion being located in the trench, the second extension portion being along the The surface of the second epitaxial layer extends; (h) the conductive structure is used as a mask, and ions of the second conductivity type are implanted in the second epitaxial layer to form a plurality of first well regions, the first The well region is spaced apart from the first extension by a predetermined distance; (i) defining a position of the source by using a mask, and implanting ions of the first conductivity type into the first well region to form a complex a source doped region; (j) depositing a dielectric layer, and forming a plurality of contact windows in the dielectric layer, exposing the source doped regions under the dielectric layer and the first well region (k) implanting ions of the second conductivity type into the first well region through the dielectric layer to form a plurality of heavily doped regions of the second conductivity type in the first well region. The manufacturing method of claim 19, wherein the step of fabricating the conductive structure comprises: forming a first oxide layer covering a bare surface of the second epitaxial layer; depositing a polycrystalline germanium layer; and using a mask The location of the conductive structure is defined and the excess polysilicon layer is etched away. The manufacturing method of claim 19, further comprising electrically connecting the conductive structure to a gate. The manufacturing method of claim 19, wherein the step of fabricating the conductive structure comprises: forming a first oxide layer covering a bare surface of the second epitaxial layer; and depositing a first polysilicon layer; Etching the first polysilicon layer to form the first extension; forming a second oxide layer covering the exposed surface of the first extension; depositing a second polysilicon layer; and defining the photomask Positioning the second extension and etching away the excess second polysilicon layer. The manufacturing method of claim 22, further comprising electrically connecting the first extension to the source doping region. The manufacturing method of claim 23, further comprising: forming an opening in the dielectric layer to expose the first extension; and forming a source metal layer, and connecting the source doped region through the contact window, And connecting the first extension through the opening. The manufacturing method of claim 19, wherein the first doped regions are thermally expanded and interconnected to form a vertical well region. The manufacturing method of claim 25, wherein the vertical well region and the substrate are separated by a doping region of a first conductivity type. The manufacturing method of claim 19, wherein the conductive structure is T-shaped. The manufacturing method of claim 19, wherein the width of the first doping region is greater than the width of the trench. The manufacturing method of claim 19, wherein the substrate is of a first conductivity type. The manufacturing method of claim 19, wherein the substrate is of a second conductivity type. A method for fabricating a high voltage MOS device, comprising: (a) providing a substrate; (b) fabricating a first epitaxial layer of a first conductivity type on the substrate; (c) using a photomask Defining a doping range in the first epitaxial layer and implanting ions of the second conductivity type a first epitaxial layer to form a first doped region; (d) repeating the foregoing steps (b) and (c) for at least one cycle; (e) fabricating a second epitaxial layer for the first epitaxial layers The first doped regions are thermally expanded and interconnected to form a vertical well region; (f) a second conductive type guard ring is formed in the second epitaxial layer to define an active region, and The position of the guard ring overlaps with the position of the vertical well region; (g) forming a gate conductive layer on the upper surface of the second epitaxial layer and aligning the vertical well region; (h) conducting the gate with the gate The layer is a mask, implanting ions of the second conductivity type into the second epitaxial layer, and driving the ions of the second conductivity type to form a plurality of first well regions, the first well regions and The vertical well areas are respectively separated by a predetermined distance, and the range of the protection ring is expanded downward to be connected with the vertical well area; (i) the position of the source is defined by a mask, and the first conductivity type is implanted Ion ions in the first well region to form a plurality of source doped regions; (j) depositing a dielectric layer, and fabricating a plurality of contact windows in the dielectric layer Locating the source doped regions under the dielectric layer and the first well region; and (k) implanting ions of the second conductivity type into the first well region through the dielectric layer to form a plurality of A heavily doped region of the second conductivity type is within the first well region. The manufacturing method of claim 31, wherein the gate conductive layer formed on the upper surface of the second epitaxial layer is extended to the guard ring. The manufacturing method of claim 31, further comprising: forming a source metal layer on the dielectric layer while connecting the protection ring and the source doped region. The manufacturing method of claim 31, wherein the vertical well zone is spaced apart from the substrate by a predetermined distance. The manufacturing method of claim 31, wherein the substrate is of a first conductivity type. The manufacturing method of claim 31, wherein the substrate is of a second conductivity type.