201011915 九、發明說明： f發明所屬之技術領域】 本發明係關於一種高壓金氧半導 兀件及其製作方法 是-種具錢直井區之絲錢半導场及聽作方法，尤其 【先前技術】 在功率半導體元件中，金氣 ,λ ώ y 牛麥效电晶體（M〇SFET)且右 φ 其應用受到極大的限制 電阻S 不’傳統之高壓金氧半場效電晶體之導通 r ΓΓΐ疋由漂移區（_聰）的電阻值（包括〜、 ❹ :=τ順高蝴之厚度並降低其摻二 而部會¥財通電_不姐例的提高。 比柄m则金氧半場效電晶體，其導通電阻中各部分所佔之 =也如圖中所示，對_3DV之金氧半場效電晶趙 书阻（Repi)僅為總導通電阻的29%;不過，對 電i的=^金乳半場效電晶體而言，蠢晶層電阻則是佔據總導通 為了降低祕金氧半場效電晶體之導通電阻。—個方法是增 加】晶體之截面積崎低導通電阻。不過，此方法會導致電晶體 之積極度降低’而造成成本的提高。另，個方法是引入少數 201011915 載子（minority carrier)導雷,v 收/π 電流（tail current )，而導 合道鉍降低‘通電阻。不過，此方法除了 曰V致開關速度降低，同時會產生拖尾 致開關損耗增加。 -種法都有其應用上的缺陷，因此，如何設計出 同土金乳料粗凡件’不僅具有 壓阻斷能力，是本領_待處理的問題。有㈤ 【發明内容】 同時具有高電壓阻斷 能 =發j之目的在於提供_種高墨金氧半導體元件及 法’可以有效降低導通電阻以降低耗損， 力。 ' 得到的和優點可以從本發明所揭露的技術特徵中 氧丰施峨供—種高壓金氧半導體元件。此高I金 虱+導體元件包括一第—塞φ和丨—丄_ 门土复 電刑2 之本體、—導電結構、—第二導 =、—弟—導電型之源極摻雜區與一第二導電型 ，導電結構具有—第-延伸部與-第二延伸部 係沿著本伸。第二延伸部 蚀部夕ΠΓ+ 、， T弟开區係位於本體内，位於第二延 極俜位2，第—井區與第—延伸部間隔—預設距離。源 :雜£係位於弟—井區内。第二井區係位於本體内，由第 “之底部延伸至—汲極摻雜區附近。201011915 IX. Description of the invention: The technical field of the invention belongs to the invention. The present invention relates to a high-pressure gold-oxygen semiconductor package and a manufacturing method thereof, which are a kind of silk-conducting semi-guide field and listening method in a straight vertical well area, especially [previously Technology] In power semiconductor components, gold gas, λ ώ y 牛麦麦电电晶 (M〇SFET) and right φ its application is greatly limited by the resistance S not 'conventional high voltage gold oxide half field effect transistor conduction r ΓΓΐ疋 The resistance value of the drift zone (_Cong) (including ~, ❹:=τ 顺高毛之厚 thickness and reduce its blending of the two will be the power of the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The transistor, which accounts for the various parts of the on-resistance, is also shown in the figure. For the _3DV, the gold-oxygen half-field effect transistor (Repi) is only 29% of the total on-resistance; however, for the electric i = ^Gold milk half-field effect transistor, the stupid layer resistance is the total conduction in order to reduce the on-resistance of the secret oxygen half-field effect transistor. One method is to increase the cross-sectional area of the crystal with low on-resistance. However, this The method will lead to a decrease in the positive degree of the transistor' In addition, one method is to introduce a few 201011915 carrier carrier to guide the mine, v to receive / π current (tail current), and the conduction switch to reduce the 'on-resistance. However, this method in addition to 曰V-induced switch The speed is reduced, and the tailing loss is increased due to the tailing. - The method has its application defects. Therefore, how to design the same material as the earthen milk emulsion is not only a pressure blocking capability, but also a skill. (5) [Invention] At the same time, there is a high voltage blocking energy = the purpose of sending j is to provide a high-intensity MOS device and method 'can effectively reduce the on-resistance to reduce the loss, force. 'Getting and advantages From the technical features disclosed in the present invention, a high-voltage gold-oxygen semiconductor component can be provided by the oxygen source. The high-I 虱+conductor component includes a body of the first plug-in φ and the 丨-丄_ a conductive structure, a second conductive conductor, a source-doped region of the second conductivity type, and a second conductivity type, the conductive structure having a first extension portion and a second extension portion extending along the extension. Extended eclipse , T brother open area is located in the body, located in the second extension pole position 2, the first well area and the first extension interval - the preset distance. Source: Miscellaneous is located in the brother-well area. The second well The fauna is located in the body and extends from the bottom of the first to the vicinity of the doped region.
在本糾之—實_巾，f—延伸部係賴 亚且，弟二延伸部係連接至一閘極。 、甲I 在本發明之—實施例中，第—延伸部與第二延伸部間具有— 6 201011915 電性連接至 介電層，第-延伸部係連接至一閑極，第二延伸部係 源極摻雜區。 “ 本發明亦提供-種高屢金氧半導體元件之製作方法，包括 2步驟：⑻提供-第-導電型之基材，·⑼於基材上製作一第 J型之:一ΐ晶ΐ二⑹利用一光罩於第-磊晶層中定義-摻雜範 圍，亚植人第—h型之離子於第―蟲晶層内，以構成 雜區；⑼重複前述步驟⑼與⑹至少一個循環；⑹製作石曰/ ❿ φ ，於這些第-蟲晶層上；（f)製作—溝渠曝露最上方之第一: ΐ柚ί)製作—導電結構於第二為層上，此導電結構具有-第二 二第，第一延伸部係位於溝渠内，第二延伸部 咖層之上表面延伸；_此導電結構為遮罩，植入 且二蟲晶層内，以構成複數個第一井區，並 井區/、第一延伸部間隔一預設距離；⑴利用一光罩 2極之位置’並植人第―導電型之離子於第—井_，以構 雜’·ω沈積—介電層’並於介電層中製作複數個 =直㈣之!極掺雜區與第-井區;(_過 導電型之「杜之軒料—賴内，轉賴數個第二 电尘之重摻雜區位於這些接觸窗之下方。 金氧施例提供一種高壓金氧半導體元件。此高廢 第二4==;第:導，本體、一問極導電層、二個 導電型之第-I & —個第—導電型之源極摻雜區與一第二 二個第二^聽!·其中，雜導電層係沿著本體之上表面延伸。 之相對^則體内’且對應於間極導電層 井 ，—们弟導電乂之源極摻雜區分別位於二個第一 "，且對應於閘極導電層之相對兩側邊之下方。第二導電型 7 201011915 j二井區魏於本體内，並由_導電層之下方向下延伸至— ^才=。此第二井區係電性連接至—閘極或—源極。第二井區 .區間分別間隔—職距離。並且，第二井區與閉極 導％層之間隔距離大於第一井區之深度。 本trr之另—貫施例提供-種高壓金氧半導體元件之製作方 法包括下列步驟：⑻提供—基材；（b)於此基材上製 1弟/ 晶層；⑹细—光罩於此H曰曰層中 雜範圍’並植人第二導電型之離子於第—蟲晶層内，以 =二:摻雜；⑼重複前述步驟(b)與⑹至少—個循環；⑹ 擴？F 曰曰層於这些第一羞晶層上，這些第一摻雜區係受熱 區;随作—第二導電細 = 層内，福—主動區域，並且，此保護環之位置與垂 ❿ =井區之位置重疊；⑼製作—閘極導電層於第4晶層之上表 =且對準垂餅區；⑼叫極導電層為遮罩，植人第二導電型 數個=於!4晶層内，並驅人這些第二導電型之離子以構成複 t弟^區，這些第-井區無直賴分_隔—預設距離， =，在趨入步驟中’保護環之範圍係向下擴張舆垂直井區相連 罩定義源極之位置，並植人第—導電型之離子於 =井區内，以構成複數個祕摻雜區；ω沈積-介電層，並於 二=中製作複數個細窗，曝露位於介電層下方之這些源極摻 =與第-井區，·_過介電層植人第二導電型之離子於第一井 ro，以構成魏轉二導電型之重摻纏於第—井區内。 —、以上_述與接下來的詳細綱皆為示範性質，是為了進一 =兄明本發明的申請專利範圍。而有闕本發明的其他目的虚優 ^，將在後續的說明與圖示加以闡述。. 8 201011915 【實施方式】 第二A輿二B_、本發明之絲金氧铸體元件—較佳實施 例之示意圖。以下係以一 N型金氧半導、 盔如¥體％效電晶體（m〇sfet) 12Γ- =1所示’此雜金氧半導體元件財—N型羞晶層 ' ¥“構150、- Ρ型之第一井區（_) 16〇、一 ν型 之源極_區170與-ρ型之第二井區13〇。其中， . _ ❹ 120係位於一 ν型基板11〇上，作 ;:： 體。Ν型基板110係電性連接至一_ η乳牛導體70件之本 導俨亓彳私至雜D，可視為此N型金氧半 W兀件之汲極摻雜區。導電結構係位於 此導電結構150係呈τ型，且右楚…“ 日日層120上 ^ 俅至丨I具旁一第一延伸部152與一第二延伸 延伸部152係由Ν型蟲晶層12〇之上表面朝向Ν型 =:20之内部延伸。第二延伸部154係沿著Ν型蟲晶層12〇 上表面延，。此導電結構15〇係電性連接至一閑極G。 4盖2之第一井區160係位於Ν型蟲晶層120内，且位於導電 ί 3:_Μ54之下方。並且，第—井區糊與導電 弟"'延伸部152間隔一預設距離。也就是說，在Ρ型 _與第一延伸部152之間具有_屋晶層120。Ν 命社;雜1ί 170係位於Ρ型之第一井區160内，且對應於導 姑s之第一延伸部彳54之下方處。此源極摻雜區彳70係電 。並且’在1^型源極摻雜區17_Ν型蠢晶層 120間具有Ρ型之第-賴160。 ，第一井區130係位於Ν型层晶層120内，並且是由第 是，此ρ卩·〗52之底部向下延伸至Ν型基板彳1〇附近。值得注意的 疋 垔之第二井區130之底部與位於其下方之Ν型基板110 9 201011915 間間隔有-定厚度之Ν型蟲晶層12〇，並且，此ρ型第二井區13〇 ，未直接與第-延伸部152相接觸。就—較佳實施例而言，ρ型 第二井區130與第-延伸部152之間至少間隔—氧化層彳4〇。惟二 此ρ型第二井區130係緊鄰於第一延伸部152，確保第二井區伽 之電位會受到第-延伸部152之電位影響。此外，此ρ型第 區130與Ρ型第一井區湖間必須留有足狗寬度的ν型蟲s曰曰層 120，作為此金氧半導體元件導通時之導電通道。 曰 φ ❿ 如第二Α _示，當此金氧半導體元件之職G源極s之屢 差（VGS)小於一臨界電塵（VTH)時，在N型源轉雜區17〇 乂型蟲晶層12〇間之ρ型第一井區飾内不會產生通道 義丨）。此時，若在汲極D (對應於N型基板彻）與源極s 對應於源極摻雜區彳7〇 )間施以順向偏壓，在p型第—井區觸 ^電=連接至源極s)與N型蟲晶層12G (電性連接至沒極⑺ 曰1之j區（d_i0請_)的範圍會加大（如圖中虛線所示）。 削ΓΓ當金氧半導體元件關斷時，閉極G (對應於導電結構 、包位與源極s(對應於源極摻雜㊄17〇) ⑷二導電結構150電性連接至閘極G)與N型磊晶層120 =接，及極D)之間之空之區的範圍亦會加大 形成於第一井區觸與蟲晶層12〇之間以及第二井In this correction - the actual _ towel, the f-extension is the Lai Ya, and the second extension is connected to a gate. In the embodiment of the present invention, the first extension portion and the second extension portion have - 6 201011915 electrically connected to the dielectric layer, the first extension portion is connected to a idle pole, and the second extension portion is Source doped region. The present invention also provides a method for fabricating a high-voltage MOS device, comprising the steps of: (8) providing a substrate of a first-conductivity type, and (9) fabricating a J-type on a substrate: a bismuth crystal (6) using a mask to define a doping range in the first epitaxial layer, the ion of the implanted type h-h is in the first layer of the insect layer to form a miscellaneous region; (9) repeating at least one of the foregoing steps (9) and (6) (6) making sarcophagus / ❿ φ on these first-insect layers; (f) making - the first of the top of the trench exposure: ΐ 柚 ί) making - the conductive structure on the second layer, the conductive structure has - a second extension, the first extension is located in the trench, and the upper surface of the second extension portion extends; the conductive structure is a mask, implanted in the second insect layer to form a plurality of first wells The area, the well area, and the first extension are separated by a predetermined distance; (1) using a photomask 2 pole position 'and implanting the first-conducting type ion in the first well_, to construct the '·ω deposition— Dielectric layer 'and make a plurality of = straight (four) in the dielectric layer! Polar doped region and the first well region; (_ over-conductive type of "Du Zhixuan material - Lai The heavily doped region of the plurality of second electric dusts is located below the contact windows. The gold oxygen embodiment provides a high voltage MOS element. This high waste second 4==; first: guide, body, a question a pole conductive layer, a source-doped region of the first-conducting type of the two conductivity types, and a second two second layer of the second conductive type; wherein the impurity conductive layer is along the upper surface of the body Extending. The relative body is 'in the body' and corresponds to the interpole conductive layer well, the source doping regions of the conductive turns are located in the two first " and correspond to the opposite sides of the gate conductive layer Below the second conductivity type 7 201011915 j two wells Wei Wei in the body, and extended from the direction below the _ conductive layer to - ^ only =. This second well is electrically connected to - gate or - source The second well zone is separated by a distance - the distance between the second well zone and the closed pole guide layer is greater than the depth of the first well zone. The other embodiment of the trr provides a high pressure gold oxide The method for fabricating a semiconductor device comprises the steps of: (8) providing a substrate; (b) forming a crystal/layer on the substrate; (6) The mask is in the H 曰曰 layer in the impurity range and implants the second conductivity type ions in the first layer of the insect layer, with the second: doping; (9) repeating the foregoing steps (b) and (6) at least one cycle; (6) expanding the F layer on the first imaginary layer, the first doped regions are heated regions; the following - the second conductive thin = the inner layer, the fu-active region, and the position of the guard ring Coveted = the position of the well is overlapped; (9) Manufacture - the gate conductive layer is above the fourth crystal layer = and is aligned with the vertical cake area; (9) the pole conductive layer is the mask, and the second conductivity type is implanted = In the !4 layer, and driving the second conductivity type ions to form a complex region, these first well regions have no direct lag-separation-preset distance, =, in the step of penetration The range of the ring is downwardly expanded. The vertical well zone is connected to the source to define the source position, and the first conductivity type ion is implanted in the well area to form a plurality of secret doping regions; the ω deposition-dielectric layer, And in the second = in the production of a plurality of fine windows, exposed to the source layer below the dielectric layer = and the first well region, · _ over the dielectric layer implanted the second conductivity type of ions in the first Well ro, Wei revolutions to form the heavily doped second conductivity type to the first wrapped around - well region. —, the above _ and the following detailed outlines are exemplary in nature, and are intended to be in the scope of the patent application of the present invention. Other purposes of the present invention will be explained in the following description and illustration. 8 201011915 [Embodiment] The second embodiment of the present invention is a schematic diagram of a preferred embodiment of the present invention. The following is an N-type gold-oxygen semiconductor, helmet, such as a body-effect transistor (m〇sfet) 12Γ- =1 'this hybrid gold-oxygen semiconductor component - N type shame layer' ¥ "structure 150, - The first well region of the Ρ type (_) 16 〇, the source of the ν type _ region 170 and the second well region of the -ρ type 13 〇. Among them, the _ ❹ 120 is located on a ν-type substrate 11 The Ν-type substrate 110 is electrically connected to a _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The conductive structure is located at the conductive structure 150 in a τ-type, and is right-handed... "the day-to-day layer 120 has a first extension 152 and a second extension 152. The upper surface of the wormhole layer 12 Ν extends toward the inside of the Ν type =:20. The second extension portion 154 is extended along the upper surface of the serpentine layer 12 . The conductive structure 15 is electrically connected to a idler G. The first well region 160 of the cover 2 is located within the serpentine layer 120 and is located below the conductive ί 3:_Μ54. Also, the first well area paste and the conductive brother " extension 152 are spaced apart by a predetermined distance. That is, there is a _ housemaline layer 120 between the Ρ-type _ and the first extension 152.杂命社; Miscellaneous 1ί 170 is located in the first well region 160 of the Ρ type and corresponds to the lower portion of the first extension 彳 54 of the guide s. This source doped region 彳70 is electrically charged. And, there is a 第-type ray 160 between the 1 - type source doping regions 17 Ν type dope layer 120. The first well region 130 is located in the germanium-type layered layer 120, and is extended from the bottom of the layer Ν 〗 52 to the vicinity of the 彳-type substrate 彳 1 。. It is noted that the bottom of the second well region 130 is separated from the Ν-type substrate 110 9 201011915 located below it by a 定-type worm layer 12 〇, and the ρ-type second well region 13 〇 It is not in direct contact with the first extension portion 152. In the preferred embodiment, the p-type second well region 130 and the first extension portion 152 are at least spaced apart from each other by an oxide layer. However, the p-type second well region 130 is adjacent to the first extension portion 152, ensuring that the potential of the second well region is affected by the potential of the first extension portion 152. In addition, between the p-type region 130 and the first well region of the Ρ type, a v-type insect worm layer 120 having a foot width must be left as a conductive path when the MOS element is turned on.曰φ ❿ as shown in the second Α _, when the gamma s of the MOS device is less than a critical electric dust (VTH), the worm is in the N-type source There is no channel in the first well area of the p-type between the layers 12. At this time, if a forward bias is applied between the drain D (corresponding to the N-type substrate) and the source s corresponding to the source doping region 彳7〇), in the p-type first well region, the contact is connected to Source s) and N-type worm layer 12G (electrically connected to the immersion (7) 曰1 j region (d_i0 please _) will increase the range (as shown by the dotted line in the figure). When turned off, the closed pole G (corresponding to the conductive structure, the package and the source s (corresponding to the source doping of 5 17 〇) (4) the two conductive structures 150 are electrically connected to the gate G) and the N-type epitaxial layer 120 = The range of the space between the junction and the pole D) is also increased between the first well zone and the insect layer 12〇 and the second well.
:芙杯’彻日日層12Q之間的空乏區’會夾斷源極摻雜區170至N 力"此導電奴。祕空乏區具錢異的賴阻斷能 力’因而可以大幅提高金氧半導體元件之财壓。 臨界與源極S之壓差_)大於- 变·源極摻雜區170與N型蠢晶層120間 201011915 土第井區160 θ (即對應於第二延伸部下方處）會產 生-通道。此時’源極摻雜區170白勺電子可透過前述通道進入空 乏區中，恢復N型蟲晶層120之電性，進而形成一導電路徑。如 圖中前頭所示，此導電通道係由源極摻雜區17〇沿著第二延伸部 =下方，再轉而沿著第—延伸部152與第二井區13〇之侧邊 垂直向下至N型基板11〇。 籲 大於’如圖中所示，第二井區13◦之寬度係 間之石曰声120的厂^見度，避免第二井區130與第一井區160 復導導通時侧-恢 此外，本二=== 壓之特性’亚且，此金氧半導體元件之 (之 延伸，有正相關。因此，就實際應用上匕井= 之延伸距f係遠大於第-延伸部152之長度。 130 雖然前揭實施例係以高壓金氧 明，不過，本_之如^ 牛導體％效電晶體為例進行說 發η將關不限於金氧半導體場效電晶體。本 發明，、而要將剛揭貫施例所使用之 日肽本 即構成-絕緣鬧雙極性電晶體〇GBT)。板110,改為ρ型基板， 第三圖係本發明高壓金衰 圖。不同於第二圖之實施锏， —另一較佳實施例之示意 延伸部152,與第二延伸部154 ^=構·之第一 氧化層，以使第-延伸部152, /電層伽，例如一 離。ϋ且，此導f結構彳5〇’ : 申邛154互相電性分 極G，第-延伸部152，則是、=°n54係電性連接至閘 第二圖之高壓金氡半導體:接;源=。 几仵中弟—井區13〇之電位是受 201011915 到閘極G的影響。相#交之下，本實施例之第二井區13〇之電位則 疋受到源極S影響。不過，當閘極〇與源極s之壓差（vgs); 於臨界電壓（VTH)時，如同第二圖之實施例，本實施例在p型 第-井區160舆N型蟲晶層120間以及p型第二井區13〇與n 型;ee晶層120間亦會產生空乏區夾斷源極摻雜區至N型基板 110間之導電通道，提供優異的電壓阻斷能力。 土 第四A至四Η圖顯示本發明高壓金氧半導體元件之製作方法 之-較佳實麵。以下係以-Ν型金氧轉體元件势 •例。如第四Α圖所示，首先，提供一 Ν型基材21〇。然】:：J 四B圖所示，於此基材210上製作一 N型第一遙晶層島，利 用一光罩（未圖示）於此第一蟲晶層2咖上方製作一光阻圖案層 PR，以定義-掺雜範圍，並植人P型離子於此第—蠢晶層22〇^ 内’以構成一 P型第一摻雜區230a。 下來’如第四C圖所示，重複第四B圖之製作步驟至少一 個’重翻次數的多寡與所欲製作之紐錢半導體元件之 耐塵值的高低呈正棚。在本實施射所製作之金氧半導體元件 ❹之耐麼值為600V，因此，重複六次第四8圖之製作步驟，而在基 材210上堆疊六層第一蠢晶層22〇a，並且對應於六 在此W晶層咖3之堆疊中，亦具有六轉一推^ 230a 〇 ^值传注意献，第四B圖之製作步驟必碰用光罩以定義換 。在本貫施例中，在各個第一遙晶層令逢形成第一推雜 …a所使用的是同—個光罩，並且，各個第一蟲晶層2咖中 所:成之第-摻雜區是沿著垂直方向對齊。此外，由於在蟲晶層 之製作步驟中涉及高溫製程，因此，第-摻雜區230a的範圍會因 12 201011915 為後續之磊晶層製作步驟而擴大。如第四c圖所示，在本，施 中，透過適當控制第一摻雜區230a之摻_勿的植人澤卢、、植入、，曲 度、以及相對應之第-蟲晶層220a之厚度，可以使各^第一蟲^ 層220a内之第-摻雜區230a互相重疊’而形成單一個p型垂直 井區230(此P型垂直井區23〇即對應於第^與二8圖之第二 井區130)。*過，此P型垂直井區23〇與其下方之基材21〇 ^ 然保持一定距離。 P遺後，如第四D圖所示，製作—N型第二蟲晶層2池於這 φ些第一麻晶層220a上，此第二蠢晶層22〇b與這些第一蠢晶声 220a整體構成1晶層220作為此金氧半導體元件之本體。秋 後’製作-溝渠248曝露最上方之第一摻雜區23〇a，也就是曝^ 這些第一摻雜區230a所構成之p型垂直井區23〇之上緣。接下 來’同時請參照第四E圖所示，製作_氧化層240，覆蓋該第二 磊晶層220b之裸露表φ。然後’全面沈積一多晶石夕層（未圖示）， 並填滿溝渠248。接下來’糊—光罩絲出導電結構25〇之位 置，並蝕刻去除多餘之多晶矽層，以形成多晶矽導電結構25〇於 ❹第二磊晶層220b上。此導電結構具有一第一延伸部252與一第 二延伸部254，第一延伸部252係位於溝渠248内，第二延伸部 254係沿者第二蠢晶層220b之上表面延伸。 接下來，如第四F圖所示，直接利用此導電結構250為遮罩， 植入P型離子於第二磊晶層220b内，以構成複數個p型之第一 井區260。此P型第-井區260與第-延伸部252係間隔-預設 距離。也就是說，在第一井區26〇與第一延伸部252間夾有N型 之第二磊晶層220b。值得注意的是，此p型第一井區260與位於 第一延伸部252下方之p型垂直井區23〇間夾有足夠寬度之n型 13 201011915 磊晶層，作為金氧半導體元件導通時之導電通道。 隧後，如第四G圖所示，利用一光罩（未圖示）於第一井區 260上製作—光賴案層pR，以定義源極摻雜區別之位置，並 植N麵子於第-井區内，以構成複數個源轉雜區27ό 於第井區260内。接下來，如第四Η圖所示，沈積一介電層28〇, 並於"電層280巾製作複數個接觸窗282，曝露位於介電層28〇 下方之源極摻雜區27Q與第—井區260。然後，透過介電層280: The vacant area between the 12#Q of the Fu Cup's day will pinch off the source doping area 170 to N force " this conductive slave. The lack of blocking power in the secret space of the straits can greatly increase the financial pressure of MOS components. The voltage difference between the critical and source S is greater than - between the source-doped region 170 and the N-type doped layer 120. 201011915 The soil well region 160 θ (ie corresponding to the lower portion of the second extension) will generate a channel . At this time, electrons in the source doping region 170 can enter the depletion region through the aforementioned channel, and restore the electrical properties of the N-type silicon oxide layer 120, thereby forming a conductive path. As shown in the front of the figure, the conductive path is from the source doped region 17〇 along the second extension=down, and then rotates along the side of the first extension 152 and the second well 13〇. Down to the N-type substrate 11〇. The appeal is greater than the factory visibility of the stone humming sound 120 between the widths of the second well region 13 ,, avoiding the side-recovery of the second well region 130 and the first well region 160 during the re-conduction conduction. , the second === characteristics of the pressure 'Asian, the extension of the MOS device, there is a positive correlation. Therefore, in practical applications, the extension distance f of the well = is much larger than the length of the first extension 152 Although the foregoing embodiment is based on a high-pressure gold oxide, the present invention is not limited to a MOSFET, but the present invention is not limited to a MOSFET. It is necessary to form the peptide used in the application of the invention - the insulated bipolar transistor 〇 GBT). The plate 110 is changed to a p-type substrate, and the third figure is a high-pressure gold failure diagram of the present invention. Different from the implementation of the second figure, the schematic extension 152 of another preferred embodiment, and the first oxide layer of the second extension 154 are configured such that the first extension 152, / electrical layer gamma , for example, a departure. Moreover, the structure f is 彳5〇': the 邛 154 is mutually electrically polarized, and the first extension 152 is Δn54 electrically connected to the high voltage 氡 semiconductor of the second diagram of the gate: Source=. A few squats - the potential of the 13 井 in the well area is affected by the 201011915 to the gate G. Under the phase #, the potential of the second well region 13本 of the present embodiment is affected by the source S. However, when the voltage difference between the gate 〇 and the source s (vgs) is at the threshold voltage (VTH), as in the embodiment of the second figure, the present embodiment is in the p-type first well region 160舆N type worm layer 120 and p-type second well regions 13〇 and n-type; ee crystal layer 120 also creates a conductive region between the source-doped region and the N-type substrate 110 in the depletion region, providing excellent voltage blocking capability. The fourth to fourth figures show the preferred embodiment of the method for fabricating the high voltage MOS device of the present invention. The following is an example of a - Ν type gold oxy-transformer element. As shown in the fourth diagram, first, a crucible substrate 21 is provided. However, as shown in Fig. 4B, an N-type first remote layer island is formed on the substrate 210, and a light mask (not shown) is used to make a light above the first insect layer 2 The pattern layer PR is patterned to define a doping range and implant a P-type ion in the first-stitch layer 22 to form a P-type first doping region 230a. As shown in the fourth C diagram, the steps of the fourth B picture are repeated to at least one of the number of times of re-turning and the level of the dust resistance of the desired Nieki semiconductor component. The resistance value of the MOS device fabricated in the present embodiment is 600V. Therefore, the fabrication steps of the fourth FIG. 8 are repeated six times, and six layers of the first stray layer 22〇a are stacked on the substrate 210. And corresponding to the six in the stack of W crystal layer coffee 3, also has six turns and one push ^ 230a 〇 ^ value transfer note, the fourth B picture production steps must touch the mask to define the change. In the present embodiment, in each of the first remote crystal layers, the first smear is formed by using the same photomask, and each of the first smectite layers 2 is: The doped regions are aligned in the vertical direction. In addition, since the high temperature process is involved in the fabrication step of the crystal layer, the range of the first doped region 230a is expanded by 12 201011915 for the subsequent epitaxial layer fabrication step. As shown in FIG. 4C, in the present application, by appropriately controlling the doping of the first doping region 230a, the implantation, the curvature, and the corresponding first-worm layer The thickness of 220a may be such that the first doped regions 230a in the first layer 220a overlap each other to form a single p-type vertical well region 230 (this P-type vertical well region 23 corresponds to the second The second well area of the second figure is 130). *Over, the P-type vertical well area 23〇 is kept at a certain distance from the substrate 21〇 below it. After P, as shown in FIG. 4D, a N-type second smectic layer 2 is formed on the first phasing layer 220a, and the second stray layer 22 〇b and the first stupid crystal The sound 220a integrally constitutes a single crystal layer 220 as a body of the MOS device. After the fall, the fabrication-ditch 248 exposes the uppermost first doped region 23a, that is, the upper edge of the p-type vertical well region 23 formed by the first doped regions 230a. Next, please refer to the fourth E diagram to form an oxide layer 240 covering the bare surface φ of the second epitaxial layer 220b. A polycrystalline layer (not shown) is then deposited altogether and fills the trench 248. Next, the paste-mask is placed at a position of the conductive structure 25, and the excess polysilicon layer is etched away to form a polysilicon conductive structure 25 on the second epitaxial layer 220b. The conductive structure has a first extension 252 and a second extension 254. The first extension 252 is located within the trench 248, and the second extension 254 extends along the upper surface of the second amorphous layer 220b. Next, as shown in the fourth F diagram, the conductive structure 250 is directly used as a mask, and P-type ions are implanted into the second epitaxial layer 220b to form a plurality of p-type first well regions 260. The P-type well region 260 is spaced apart from the first extension portion 252 by a predetermined distance. That is, an N-type second epitaxial layer 220b is interposed between the first well region 26A and the first extension portion 252. It should be noted that the p-type first well region 260 and the p-type vertical well region 23 below the first extension portion 252 sandwich an n-type 13 201011915 epitaxial layer of sufficient width as the MOS device is turned on. Conductive channel. After tunneling, as shown in the fourth G diagram, a photomask (not shown) is used to fabricate a light-receiving layer pR on the first well region 260 to define a source-doping difference position and implant a N-face. In the first well region, a plurality of source turnaround regions 27 are formed in the well region 260. Next, as shown in the fourth figure, a dielectric layer 28 is deposited, and a plurality of contact windows 282 are formed on the "electric layer 280, and the source doped region 27Q under the dielectric layer 28 is exposed. First - well area 260. Then, through the dielectric layer 280
魯 植入Ρ型離子於第—井區26Q内，以構成複數個ρ型重掺雜區 於第一井區260内。 ^如第四Η騎示，在前揭實施例中，形成於蟲晶層22〇之各 個第=摻雜區230a係互相重疊以構成一垂直井區23〇。不過，本 發明亚不限於此。如第五騎示，製作於蟲晶層挪各個第一推 亦可以互相分離。不過，各個第-摻缝33Qa之間隔 传太大’以確保各個第一摻雜區33〇a的電位可以互相感 第六A至六E難本發鴨壓金氧轉體元件另 ^製作流程。承接第四D圖之步驟，如第六A圓所示，製作一 =氧化層241 ’覆蓋該第二蟲晶層22〇b之裸露表面。然^，全 二積層，並且填滿溝渠248。接下來，回银⑽h 二==一多_ ’僅留下位於溝渠248内由多晶 夕材科所構成之導電結構35Q之第—延伸部352。 接下來’如第六B圖所示，费作—筮_备 -延伸邻352 w史 弟-乳化層242，覆蓋第 ^ 2TT ° ^5 ^ t 二弟一乳化層242。接下來，利用—光罩（未圖 伸糊之位置，並侧去除多餘，=二 14 201011915 晶矽材料所構成之導電結構350之第二延伸部354。 接下來，如第六c圖所示，直接利用第二延伸部354為遮罩， 植入P型離子於第二蟲晶層2施内，以構成複數個p型之第— 井區260。隨後，如第六DgI所示，利用—光罩（未圖示）製 -光阻圖案層PR於第—井區26G上，以定義源極摻雜㈣〇之 亚植^ N型離子於第一井區26〇内，以構成複數個源極摻 二品270於第-井區内。接下來，如第六e圖所示，沈積— ’丨电層280 ’並於介電層28〇中製作複數個接觸窗，曝露位 於介電層28Q下方之源極摻雜區27Q與第—井區26q。然後 认p型之離子於第—井11 内，以構成複數個 p型之重摻雜區290於第一井區26〇内。 值得注意岐，透過前述第六A與六B圖之步驟所製作之第 丄延=部352舆第二延伸部354是彼此分離。就一較佳實施例而 二=伸，可電性連接至閑極G，以控制此金氧半導體 …一 k弟延伸部352則可電性連接至源極S。為了將此 ^ ^伸部3=性連接至源極s，就—較佳實施例而言 ’可在介電層鄰近於此縫金氧半導體元件之邊緣 曝露此第一延伸部352，然後再利用-源極 " 5 T接至第一延伸部352與源極摻雜區270，即可 使第—延伸部352電性連接至源極S。 圖。本判緒錢轉航件又—健實補之示意 :二:。型第，6。、二個二二電層。 型罘二井區130。M專丨丨石B ^ r /、 N i猫日日層120係位於一 n型基材 15 201011915 上，作為此高I金氧半導體元件之本體。間極導電層係 .N型蟲晶層120之上表面延伸。二個p型第一井區棚係位於n 型蟲晶層J2◦内’且對應於難導電層之相對兩側邊。此二 個P型第一井區160係間隔一定距離。 -個N型源極摻雜區17〇分別位於二個p型第一井區· 内，且位於難導電層之姆_邊之下方處。p型第 區130係且位於N型蠢晶層12〇内，由間極導電層45〇之下方， 型基材11Q附近。此N型基材彻可視為一 n型 區。P型第二井區13Q與二個p型第—井區間分 別間隔一預設距離。此第-并pr i 弟一井£ 130係電性連接至一閘極G或- 源極S。亚且，就—較佳實施 層咖之間隔距離係大於第一井區16〇弟之;130與閉極導電 至此’為了將第：井請電性連接 46〇作為齡心Λ 件之邊緣處之保護環（g咖d _) ❿ 作為媒"以進仃電性連接。如 =_本_，且魏錄主祕域糸 鄉之錄料奴叙料輯心伸至保魏 卜万而與保護環460相接。 如第九A圓所示，為了使連接 130電性連餘馳3，材_在介ii8Q6mr二井區 以曝露保護環460。並且，在介電層18曰 衣作有開口 186 扣5,同時連接L原極換雜區 ^ 上沈積有源極金屬層 電性連接至源極S。如第九所、保；460 ’以使保護環460 θ斤不，為了使連接至保護環‘460 16 201011915 之P型第二井區130電性連接至閘極G，本實施例直接利用主動 區域A邊緣之閉極導電層45〇，。將此閘極導電層45〇,延伸至 保護核460之上表面而與保護環相連接，以使保護環* 性連接至閘極G。 电 ，第十A至十C_顯示第人圖之金氧半導體元件連同其保 裱460之製作方法之一較佳實施例。承接第四 十A圖所示，在製作第二蟲晶層島之後，製作— 裱460於第二蟲晶層22〇b内，定義出一主動區域a。由第二层晶 層220b之上方觀之，此保護環46〇之位置係與位於蟲晶層挪 内之P型垂直井區230 (即對應於第八圖之第二井區13〇)的位 置重疊。隨後，製作-祕導電層於第二蟲晶層22〇b之上 表面，且對準垂直井區230。 接下來，如第十3圖所示，以此閘極導電層45〇為遮罩，植 入P型離子於第二层晶層220b内，並驅人這些P型離子，以構 成複數個P型第-井區260。這些p型第一井區26〇與p型垂直 井區230分別間隔一預設距離。值得注意的是，在驅入p型離子 ❿之步驟中’保護環· _ p 子也會向下擴散，而使保護環 460的範圍向下擴張與p型垂直井區23〇相連接。 、 隨後，如針C圖所示，侧-光罩定義源極之位置，並植 入N型離子於第—井區26Q内，以構成複數個源極摻雜區挪。 然後，沈積一介電層280，並於介電層280中製作複數個接觸窗 282，曝露位於介電層28〇下方之源極摻雜區27〇與第一井區 260。接下來，透過介電層28〇植入p型離子於第一井區26〇内， 以構成p型重摻雜區290於第一井區260内。 本發明之高壓金氧半導體元件具有下列優點·· · 201011915 首先，如第二A與二B圖所示，當閘極G與源極s之壓差 (VGS)小於一臨界電壓（VTH)時，若在汲極d與源極s間 以順向偏壓’在第—井區湖與第二井區彳3〇間會產生空乏區完 王阻斷其間之N型|晶層12〇。此空乏區具有優異的電壓阻斷能 力’因而可以大幅提高金氧半導體元件之耐壓。另—方面，Lu implants the erbium-type ions in the first well region 26Q to form a plurality of p-type heavily doped regions in the first well region 260. As shown in the fourth embodiment, in the foregoing embodiment, each of the doped regions 230a formed in the germanium layer 22 is overlapped with each other to constitute a vertical well region 23A. However, the present invention is not limited to this. For example, in the fifth riding, the first pushes made in the insect layer can be separated from each other. However, the interval of each of the first dopings 33Qa is too large to ensure that the potentials of the respective first doping regions 33a can be mutually sensible. The sixth A to the sixth E are difficult to make the duck pressure metal oxide rotating body component. . Taking the step of the fourth D picture, as shown in the sixth A circle, an oxide layer 241' is formed to cover the exposed surface of the second crystal layer 22〇b. However, all two layers are stacked and filled with trenches 248. Next, the returning silver (10) h == one more _ ' leaves only the first extension 352 of the electrically conductive structure 35Q formed by the polycrystalline sapphire in the trench 248. Next, as shown in Fig. 6B, the fee--筮_备-extends the adjacent 352 w-small-emulsified layer 242, covering the second TT ° ^ 5 ^ t two-different layer 242. Next, a second mask 354 of the conductive structure 350 composed of the wafer material is removed by using a photomask (not shown in the position of the paste and removing the excess, = 2 14 201011915. Next, as shown in the sixth c-graph The second extension portion 354 is directly used as a mask, and P-type ions are implanted into the second crystal layer 2 to form a plurality of p-type first well regions 260. Subsequently, as shown in the sixth DgI, a photomask (not shown) - a photoresist pattern layer PR on the first well region 26G to define a source doping (four) 〇 sub-planting N-type ions in the first well region 26 , to constitute a plurality One source is doped with the second product 270 in the first well region. Next, as shown in the sixth e-graph, the deposition - 'tantalum layer 280' is formed and a plurality of contact windows are formed in the dielectric layer 28〇, and the exposure is located in the dielectric layer 28〇. The source doping region 27Q and the first well region 26q under the electrical layer 28Q. The p-type ions are then identified in the first well 11 to form a plurality of p-type heavily doped regions 290 in the first well region 26〇 It is noted that the second extensions 354 formed by the steps of the sixth and sixth diagrams are separated from each other. For example, two extensions can be electrically connected to the idler G to control the MOS semiconductor. The KK extension 352 can be electrically connected to the source S. In order to connect the extension 3 to the sexual connection The source s, as in the preferred embodiment, can expose the first extension 352 to the edge of the dielectric layer adjacent to the slot MOS, and then use the -source " 5 T to the first The extension portion 352 and the source doping region 270 can electrically connect the first extension portion 352 to the source S. Figure 2. The judgment of the money transfer member is again - the indication of the health supplement: two: type type, 6. Two or two electric layers. The type I 罘 two well area 130. M special meteorite B ^ r /, N i cat day layer 120 is located on an n-type substrate 15 201011915, as this high I gold oxygen The body of the semiconductor component. The interpolar conductive layer extends over the surface of the N-type wormhole layer 120. The two p-type first well zone sheds are located in the n-type wormhole layer J2◦' and correspond to the opposite of the difficult-to-conducting layer. The two P-type first well regions 160 are spaced apart by a certain distance. - An N-type source doping region 17〇 is located in the two p-type first well regions, and is located in the hard conductive layer. _Bianzhi In the lower part, the p-type region 130 is located in the N-type stray layer 12〇, and is located below the inter-polar conductive layer 45, near the type substrate 11Q. The N-type substrate can be completely regarded as an n-type region. The second well zone 13Q is spaced apart from the two p-type first well sections by a predetermined distance. The first and the pr i brothers are electrically connected to a gate G or a source S. Therefore, the interval between the better implementation layer is greater than that of the first well area; 130 and the closed pole are electrically conductive to this point. In order to electrically connect the first well to the 46, the protection at the edge of the core part is Ring (g coffee d _) ❿ as a media " to enter the electrical connection. Such as =_ this _, and Wei Lu's main secret domain 乡 乡 乡 乡 乡 乡 乡 乡 乡 乡 乡 乡 乡 乡 乡 乡 乡 乡 乡 乡 乡 乡 乡 乡 乡 乡 乡 乡 乡 乡As shown in the ninth A circle, in order to electrically connect the connection 130, the material is exposed to the protective ring 460 in the second well region of the ii8Q6mr. Moreover, the dielectric layer 18 is provided with an opening 186 buckle 5, and the deposited source metal layer is electrically connected to the source S. As in the ninth, the protection; 460 'to make the protection ring 460 θ 不, in order to electrically connect the P-type second well region 130 connected to the protection ring '460 16 201011915 to the gate G, the embodiment directly utilizes the initiative The closed-pole conductive layer 45〇 on the edge of the region A. The gate conductive layer 45 is extended to the upper surface of the protective core 460 to be connected to the guard ring to connect the guard ring to the gate G. Electric, 10A to 10C_ show a preferred embodiment of the method of fabricating the MOS device of the first figure together with the 460 thereof. Following the creation of the fourth smectic layer island, the 裱460 is formed in the second wormhole layer 22〇b to define an active region a. Viewed from above the second layer 220b, the position of the guard ring 46 is associated with the P-type vertical well region 230 located in the insect layer (ie, corresponding to the second well region 13 of the eighth figure). The positions overlap. Subsequently, a conductive layer is formed on the surface of the second insect layer 22〇b and aligned with the vertical well region 230. Next, as shown in FIG. 3, the gate conductive layer 45 is used as a mask, P-type ions are implanted in the second layer 220b, and the P-type ions are driven to form a plurality of P. Type first well area 260. The p-type first well regions 26 and the p-type vertical well regions 230 are each spaced apart by a predetermined distance. It is worth noting that in the step of driving the p-type ion enthalpy, the 'protective ring _ p sub-diffusion also diffuses downward, and the range of the guard ring 460 is expanded downward to be connected to the p-type vertical well region 23 。. Subsequently, as shown in pin C, the side-mask defines the position of the source and implants N-type ions in the first well 26Q to form a plurality of source doped regions. Then, a dielectric layer 280 is deposited, and a plurality of contact windows 282 are formed in the dielectric layer 280 to expose the source doping region 27 and the first well region 260 under the dielectric layer 28A. Next, p-type ions are implanted into the first well region 26 through the dielectric layer 28 to form a p-type heavily doped region 290 in the first well region 260. The high voltage MOS device of the present invention has the following advantages: 201011915 First, as shown in the second A and B diagrams, when the voltage difference (VGS) between the gate G and the source s is less than a threshold voltage (VTH) If there is a forward bias between the bungee d and the source s, a N-type | crystal layer 12〇 will be formed between the first well zone and the second well zone. This depletion region has excellent voltage blocking capability, which can greatly increase the withstand voltage of the MOS device. Another aspect,
極G與源極S之壓差（VGS)大於—臨界電壓（vth)時，^ 極摻雜區170與Ν型蠢晶層12Q間之第—井區内會產生通 迢。—此時，源極摻雜區17〇的電子可透過前述通道進入空乏區中， 恢復N型蟲晶層12〇之電性，進而形成一導電路徑。基本上，遷 過適度提冋_蟲晶層i2Q之摻雜濃度，可以獲致優異的導 阻，達到降低導通損耗的目的。 …其次’如第二A _示’本發明之高壓金氧半導體元件在關 ，所形成之空乏區是位於第一井區彻與第二井區⑽之間。 區160舆第H 130之間隔距離通常是小於相鄰二金氧 半導體元狀·之間隔麟。因此，本發明之高壓金氧半導體 =件關斷後，填充電子至空乏區㈣復至導通狀態的速度會優於 專統之具有橫向ΡΝ接面的高麗金氧半導體元件，例如 00丨mosTM與Super junction半導體元件。 此外’如第二A圖所示’本發明之高屢金氧半導體元件除了 在重摻雜區190、第-井區彻與N型屋晶層12〇間具有一盘生 j之齊納二極體，在第二井區13◦與N型遙晶層12〇間亦具有 、主二納—極體。當雪崩崩潰（avalanche breakdown)產生時，崩 潰電流不會完全集中於重摻雜區、第-井區與N型蟲晶 層120間之齊納二極體。因此，本發明之高驗氧半導體元件可 、減力”士第__延伸部154下方之橫向電阻的電流，進而可以防 201011915 止形成於N型磊晶層彳20、P型第一井區160與源極掺雜區170 間之雙極性接面電晶體因為過大的電流而毀損。 如上所述，本發明完全符合專利三要件：新穎性、進步性和 ，業上的彻性。本發明在上文中已以較佳實施例揭露，然熟習 讀例僅用於描緣本發明，而不應解 護範圍當町文之中請ΐ利範圍. 化與置換，均應設舉凡與該實施例等效之變 祕々一 、 於本發明之靶疇内。因此，本發明之保 馨 所界定者為準。When the voltage difference (VGS) between the pole G and the source S is greater than the -threshold voltage (vth), a pass is generated in the first well region between the gate doping region 170 and the germanium doped layer 12Q. - At this time, electrons in the source doped region 17〇 can enter the depletion region through the aforementioned channel, and restore the electrical properties of the N-type germane layer 12, thereby forming a conductive path. Basically, the doping concentration of the moderately raised 冋 虫 晶 layer i2Q can achieve excellent resistance and reduce the conduction loss. Next, as in the second A-shower, the high voltage MOS device of the present invention is turned off, and the formed depletion region is located between the first well region and the second well region (10). The spacing distance between the region 160 and the H 130 is usually smaller than that of the adjacent two oxynitrides. Therefore, after the high voltage MOS device of the present invention is turned off, the filling electrons to the depletion region (4) can be turned to the conduction state at a faster rate than the specialized Koryo MOS device having a lateral splicing surface, such as 00 丨 MOSTM and Super junction semiconductor components. In addition, as shown in FIG. 2A, the high-frequency MOS device of the present invention has a disk-like Zener in the heavily doped region 190, the first well region and the N-type roof layer 12 〇. The polar body also has a main di-nano pole body between the second well region 13◦ and the N-type remote crystal layer 12〇. When avalanche breakdown occurs, the collapse current is not completely concentrated in the Zener diode between the heavily doped region, the first well region and the N-type silicon oxide layer 120. Therefore, the high oxygen-supplied semiconductor device of the present invention can reduce the current of the lateral resistance under the extension 154, and can prevent the formation of the N-type epitaxial layer 彳20 and the P-type first well region from 201011915. The bipolar junction transistor between the 160 and the source doped region 170 is destroyed by excessive current. As described above, the present invention fully complies with the three requirements of the patent: novelty, advancement, and industrial clarity. In the above, the preferred embodiments have been disclosed, but the familiar readings are only used to describe the present invention, and should not be used as a scope for the benefit of the application. The equivalent of the example is one of the target domains of the present invention. Therefore, the definition of the present invention is based on the definition of the present.
19 201011915 【圖式簡單說明】 第-與- A圖顯示不同耐屢之金氧半場 雕 通電阻中各部分所佔之比例的差異； 电曰日肢，其整體導 第二A與二B_本购絲錢 之剖面示意圖； 還凡件—較佳實施例 ==係本發明高祕氧半半導體元料 面不意圖； 子乂1土只％例之剖 第四A至四Η ®㈣本翻縫金氧 之一較佳實施例； 體兀件之製作方法 第^係本㈣高#錢半導體元敎 示思圖，·以及 佳貝知例之剖面 弟六A至六E圖顯示本發明高氧 之另一較佳實施例； V版兀件之製作方法 第七圖係第六E圖中之第—延伸部電 較佳實施例之示意圖； "接至源極#雜區一 ❹ 第八圖係本發明高屋金氧半 示意圖； ' 一h佳實施例之剖面 第九A圖係第八圖中之第二井區 例之剖面示意圖； 連接至源極一較佳實施 第九B圖係第八圖中 例之剖面示意圖；以及——性連接至閉極一較佳實施 第十A至十c圖係第八圖 之製作方法之-較佳實施例。玉乳+導體轉及其保護環 20 201011915 【主要元件符號說明】 •基板110 N型磊晶層120 P型第二井區130 氧化層140 導電結構150,150’ 第一延伸部152,152’ 第二延伸部154,154’ 參 介電層156 閘極導電層450,450’ P型第一井區160 源極摻雜區170 介電層180 開口 18619 201011915 [Simple description of the diagram] The first and the -A diagrams show the difference in the proportion of each part of the resistance of the different resistances of the gold-oxide half-field; the electric prosthesis, its overall guide second A and two B_ Schematic diagram of the cross-section of the purchase of silk money; also the parts - the preferred embodiment == is not intended for the high-oxygen semi-semiconductor element of the present invention; sub-乂1 soil only part of the section of the fourth A to four Η ® (four) A preferred embodiment of the crimping gold oxide; the method for fabricating the body member is the first embodiment of the body (four) high #钱 semiconductor yuan 思思图, and the profile of the Jiabei example, six A to six E, showing the invention Another preferred embodiment of high oxygen; a method for fabricating a V-plate element; a seventh embodiment is a schematic diagram of a preferred embodiment of the first-extension portion of the sixth E-figure; "connected to the source #杂区一❹ Figure 8 is a schematic view of a high-rise gold-oxygen half of the present invention; 'A section of the second embodiment of the preferred embodiment is a schematic cross-sectional view of the second well region in the eighth figure; a preferred embodiment of the connection to the source The figure is a schematic cross-sectional view of the example in the eighth figure; and - the sexual connection to the closed pole, the preferred embodiment, the tenth to tenth c, the eighth figure The manufacturing method - the preferred embodiment. Jade milk + conductor turn and its guard ring 20 201011915 [Description of main components] • Substrate 110 N-type epitaxial layer 120 P-type second well region 130 Oxide layer 140 Conductive structure 150, 150' First extension 152, 152' Second extension 154, 154 ′ dielectric layer 156 gate conductive layer 450, 450 ′ P-type first well region 160 source doped region 170 dielectric layer 180 opening 186
P型重摻雜區190 源極金屬層195 汲_極D 閘極G 源極S 保護環（guard ring) 460 主動區域A 基材210 N型磊晶層220 N型第一磊晶層220a 21 201011915 N型第二磊晶層220b -光阻圖案層PR , P型第一摻雜區230a，330a P型垂直井區230 溝渠248 氧化層240 第一氧化層241 第二氧化層242 Φ 導電結構25〇,35〇 第一延伸部252,352 第二延伸部254,354 P型第一井區260 源極摻雜區270 介電層280 接觸窗282 開口 284 參 P型重摻雜區290 源極金屬層295 22P-type heavily doped region 190 source metal layer 195 汲_pole D gate G source S guard ring 460 active region A substrate 210 N-type epitaxial layer 220 N-type first epitaxial layer 220a 21 201011915 N-type second epitaxial layer 220b - photoresist pattern layer PR, P-type first doping region 230a, 330a P-type vertical well region 230 trench 248 oxide layer 240 first oxide layer 241 second oxide layer 242 Φ conductive structure 25〇, 35〇 first extension 252, 352 second extension 254, 354 P-type first well region 260 source doped region 270 dielectric layer 280 contact window 282 opening 284 reference P-type heavily doped region 290 source metal layer 295 twenty two