JP2006093684A - Semiconductor device and optical semiconductor relay device using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having an SOI structure in which capacitance Coff between output terminals at the time of signal cutting off is reduced and further on-resistance Ron is reduced, and an optical semiconductor relay device using it. <P>SOLUTION: In a power MISFET 20, a BOX layer (an oxide film layer) 2 is formed on the surface of a first silicon substrate 1, and an N<SP>+</SP>source layer 7, a P layer 6, an offset layer 5 of low impurity concentration and an N<SP>+</SP>drain layer 8 are provided in this order on the surface of the BOX layer 2. A first gate electrode 10 is provided on the P layer 6 through a gate insulating film 9. A second gate electrode 15 with the BOX layer 2 as a gate insulating system is provided on the rear surface of the first silicon substrate 1 while facing the Player 6. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to a semiconductor device, and in particular, a power MISFET (metal insulator semiconductor field effect transistor) having an SOI (silicon on insulator) structure suitable for an optical semiconductor relay device used in a circuit for transmitting a high frequency signal such as a semiconductor memory tester and the like. The present invention relates to the used optical semiconductor relay device.

In recent years, in an optical semiconductor relay device using a light emitting element (LED) on the input side and a photodiode array (PV) and a power MISFET on the output side, the power MISFET is used in a circuit for transmitting a high frequency signal such as a semiconductor memory tester. When the signal processing speed is increased, for example, GHz or higher, the output-terminal capacitance Coff and the on-resistance Ron when the signal is interrupted.
Reduction is required.

Up to now, power MISFETs of SOI structure have been used as power MISFETs used in optical semiconductor relay devices (see, for example, Patent Document 1). Such power M
In the ISFET, while maintaining the gate-drain breakdown voltage, the output terminal capacitance Coff at the time of signal interruption is reduced, and the on-resistance Ron is reduced to further increase the CR product (CoffxRon) required in the optical semiconductor relay device. ) Cannot be achieved.
Japanese Patent Laid-Open No. 11-74539 (page 8, FIG. 1)

The present invention provides an SOI structure semiconductor device in which the output terminal capacitance Coff at the time of signal interruption is reduced and the on-resistance Ron is reduced, and an optical semiconductor relay device using the same.

A semiconductor device according to an embodiment of the present invention includes a semiconductor substrate, an oxide film layer provided on the first main surface of the semiconductor substrate, a first conductivity type semiconductor layer provided on the oxide film layer, An offset layer having a lower impurity concentration than the first conductivity type semiconductor layer provided on the oxide film layer in contact with one end of the first conductivity type semiconductor layer; and The second conductivity type source layer having a higher impurity concentration than the first conductivity type semiconductor layer provided on the oxide film layer in contact with the other end, in contact with the offset layer, and the first conductivity type A second conductivity type drain layer having a higher impurity concentration than the first conductivity type semiconductor layer provided on the oxide film layer and spaced apart from the semiconductor layer; and on the first conductivity type semiconductor layer A first gate insulating film provided, and the first conductor through the first gate insulating film. A first gate electrode provided on the semiconductor layer of the mold, and a second main surface opposite to the first main surface of the semiconductor substrate, the first conductive layer through the oxide film layer and the semiconductor substrate. And a second gate electrode provided to face the semiconductor layer of the mold.

The semiconductor relay device according to an embodiment of the present invention includes a light emitting element to which a relay control signal is input, a photodiode array that receives light emitted from the light emitting element and generates a voltage,
A semiconductor substrate, an oxide film layer provided on the first main surface of the semiconductor substrate, a first conductivity type semiconductor layer provided on the oxide film layer, and one end of the first conductivity type semiconductor layer An offset layer having a lower impurity concentration than the first conductivity type semiconductor layer provided on the oxide film layer and in contact with the other end of the first conductivity type semiconductor layer; The second conductive type source layer having a higher impurity concentration than the first conductive type semiconductor layer and the oxide film layer in contact with the offset layer and spaced apart from the first conductive type semiconductor layer A second conductivity type drain layer having a higher impurity concentration than the first conductivity type semiconductor layer, a gate insulating film provided on the first conductivity type semiconductor layer, and the gate insulation; A first gate electrode provided on the semiconductor layer of the first conductivity type via a film; A second gate electrode provided on the second main surface opposite to the first main surface of the semiconductor substrate so as to face the semiconductor layer of the first conductivity type via the oxide film layer and the semiconductor substrate. And a semiconductor element in which a voltage generated by the photodiode array is supplied to the first gate electrode and the second gate electrode.

According to the present invention, the output terminal capacitance Coff at the time of signal interruption is reduced, and the on-resistance Ron is reduced.
It is possible to provide a semiconductor device having an SOI structure with reduced resistance and an optical semiconductor relay device using the same.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the description, parts common to all the drawings are denoted by common reference numerals.

[First Embodiment]
First, a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings.
This embodiment is an SOI power MISFET applied to, for example, an optical semiconductor relay device.
FIG. 1 is a cross-sectional view showing a power MISFET, and FIG. 2 is a schematic view showing the power MISFET.

As shown in FIG. 1, the power MISFET 20 has a BOX layer (buried oxide film layer) 2 formed on the first main surface (surface) of the first silicon substrate 1, and the first main surface (surface) of the BOX layer 2. ) Has an SOI substrate 4 on which a second silicon substrate 3 is formed. Here, SOI substrate 4
Are formed by bonding the first silicon substrate 1 and the second silicon substrate 3 through a BOX layer (buried oxide film layer) 2 which is a silicon oxide film (formed by high-temperature oxidation of silicon). Here, the first silicon substrate 1 has an N-type impurity, but may have a P-type impurity.

The second silicon substrate 3 includes a BOX layer 2 from the first main surface (front surface) of the second silicon substrate 3.
P ^- offset layer 5 and P layer 6 having a low impurity concentration and a high resistance, which are formed until they are in contact with the first main surface.
, N ⁺ source layer 7 and N ⁺ drain layer 8 are provided. The P layer 6 has one end in contact with the P ⁻ offset layer 5 and the other end in contact with the N ⁺ source layer 7. The N ⁺ drain layer 8 is in contact with the P ⁻ offset layer 5. The P layer 6 functions as a base layer of the power MISFET 20.

Here, the P ^- offset layer 5 improves the breakdown voltage between the source and the drain,
It serves to reduce the drain-to-drain capacitance (Cgd) and the drain-source capacitance (Csd). The thickness of the second silicon substrate 3 is as thin as 0.1 μm, for example, in order to reduce the capacitance such as the gate-drain capacitance (Cgd) and the source-drain capacitance (Csd). The output terminal capacitance (Coff) at the time of signal interruption is
Coff = Cgd + Csd + Cg2d Expression (1)
Cgd and Csd occupy a large proportion.

On the first main surface (front surface) of the P layer 6, a first gate electrode 10 made of polycrystalline silicon is disposed on the N ⁺ source layer so as to be adjacent to at least the P layer 6 via the gate insulating film 9. 7 and N
^The drain layer 8 is provided to extend to a part on the first main surface (surface) of the drain layer 8. A contact opening 12 a is provided in the insulating film 11 covering the first gate electrode 10 so as to expose a part of the N ⁺ source layer 7, and the contact opening 12 b exposes a part of the N ⁺ drain layer 8. It is provided as follows. Here, in order to maintain the withstand voltage of the power MISFET, the gate insulating film 9 is formed thicker than a gate insulating film used in a digital semiconductor integrated circuit such as a memory device or a logic circuit, for example.

A source electrode 13 is formed on the exposed N ⁺ source layer 7, and a drain electrode 14 is formed on the exposed N ⁺ drain layer 8. Then, the second main surface of the first silicon substrate 1 (
A second gate electrode 15 having the BOX layer 2 as a gate insulating film is provided on the back surface.

As shown in FIG. 2, the power MISFET 20 includes a first channel portion 16 in a first main surface (surface) portion of the second silicon substrate 3 that is generated when a voltage is applied to the first gate electrode 10.
The second of the second silicon substrate 3 that is generated when a voltage is applied to the second gate electrode 15.
And a second channel portion 17 of a main surface (back surface) portion.

Here, the film thickness of the BOX layer 2 is thicker than the film thickness of the gate insulating film 9. For example, the film thickness of the BOX layer 2 is 3 μm and one digit or more with respect to 0.14 μm. It is formed thick. Therefore, the threshold voltage of the power MISFET 20 when the (+) voltage is applied to the second gate electrode 15 and the drain electrode 14 (the second channel portion 17 is in a conductive state, that is, turned on).
Vth2 is larger than the threshold voltage Vth1 of the power MISFET 20 when the (+) voltage is applied to the first gate electrode 10 and the drain electrode 14 (the first channel portion 16 is on), for example, four times or more. Become.

The threshold voltage of the power MISFET 20 when the (+) voltage is applied to the first gate electrode 10, the second gate electrode 15, and the drain electrode 14 (the first channel portion 16 and the second channel portion 17 are turned on) ) Vth3 is
Vth3 <Vth1 <Vth2 Equation (2)
And can be lower than Vth1.

Here, since the thickness of the BOX layer 2 is one digit or more larger than the thickness of the gate insulating film 9, the gate-drain capacitance (Cgd) when a (+) voltage is applied to the second gate electrode 15. ), Increase in capacitance such as source-drain capacitance (Csd) can be suppressed. The second
When the interface state, mobility and the like of the channel portion 17 of the first and second channels deteriorate, the characteristics of the power MISFET 20 using the second gate electrode 15 as a gate electrode deteriorate. Therefore, the second channel portion 17
It is preferable that the crystallinity of the part is equivalent to that of the first channel part 16 parts.

Next, the characteristics of the power MISFET will be described with reference to FIG. Figure 3 shows power MI
It is a characteristic view which shows the ON resistance of SFET. Here, the conventional characteristics are obtained when a (+) voltage is applied to the first gate electrode and the drain electrode. In the present embodiment, the (+) voltage is applied to the first gate electrode, the second gate electrode, and the drain electrode. It is a characteristic at the time of applying the voltage of.

As shown in FIG. 3, the power MISFET conventionally has a large on-resistance (Ron). On the other hand, in this embodiment, the same (+) voltage is applied to the first gate electrode 10 and the second gate electrode 15, and the (+) voltage is applied to the drain electrode 14. For this reason, since the first channel portion 16 and the first channel portion 16 are simultaneously turned on, the on-resistance (Ron) of the power MISFET 20 can be reduced as compared with the conventional case.

As described above, in the semiconductor device of the present embodiment, the offset layer 5 having a low impurity concentration and a high resistance is provided on the drain side in order to improve the breakdown voltage between the source and the drain. The offset layer 5 having a low impurity concentration and a high resistance can be replaced with a super-junction structure having a fine pitch designed to be depleted in a thermal equilibrium state where the applied voltage of the gate and drain is zero V. A first gate electrode 10 formed on the P layer 6 via a gate insulating film 9 and a second main surface (back surface) of the first silicon substrate 1 with a BOX layer 2 as a gate insulating film A power MISFET 20 having a gate electrode 15 is provided. And
The threshold voltage when the (+) voltage is applied to the first gate electrode 10 and the second gate electrode 15 and the first channel portion 16 and the second channel portion 17 are turned on is expressed as the first gate electrode. (+) Is applied to 10 and the threshold voltage when the first channel section 16 is turned on can be made smaller. Accordingly, the capacitance Coff between the output terminals when the signal is interrupted is reduced, and the on-resistance R
A power MISFET having an SOI structure with reduced on can be obtained.

In this embodiment, the P ⁻ offset layer 5 is used. However, as shown in FIG. 4, a low impurity concentration and high resistance N ⁻ offset layer may be used. As a modification of the present embodiment, as shown in FIG. 5, the BOX layer 2 under the P layer 6 has a first gate insulating film 9 and a first gate electrode 10 having substantially the same shape as the first gate electrode 10. By providing the third gate insulating film 90 and the third gate electrode 100, the on-resistance can be further reduced. Further, the second gate electrode 15 is provided on the second main surface (back surface) of the first silicon substrate 1, but the power MISFET
20 is resin-encapsulated in a resin-encapsulated semiconductor device, a second gate electrode is not provided on the second main surface (rear surface) of the first silicon substrate 1 and is connected to a lead via a solder material. A voltage may be applied to the lead. Further, instead of the power MISFET 20 having a gate as an insulating film, a power MOSFET having a gate as a silicon oxide film may be used.

[Second Embodiment]
Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings.
FIG. 6 is a plan view showing the power MISFET. In the present embodiment, an N ⁺ source layer 7 and a P ⁺ back gate layer 21 are provided in the source portion of the power MISFET of the first embodiment, and a super junction structure semiconductor layer is provided in the offset portion of the drain portion.

Hereinafter, in the present embodiment, the configuration other than the semiconductor layer of the super junction structure is the first.
The same components as those of the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and only different portions will be described.

As shown in FIG. 6, the power MISFET 20a has a super junction structure in an offset portion provided in a portion of the drain portion facing the gate portion. In the source part,
N ⁺ source layer 7 and P ⁺ back gate layer 21 having a fine width are repeatedly formed facing the gate portion, while N layer 23 and P layer 22 having a fine width are formed in the gate portion at the offset portion. It is repeatedly formed facing each other. In the illustrated case, the N ⁺ source layer 7 and the P ⁺ back gate layer 21 are arranged such that the width of the N ⁺ source layer 7 is wider than the width of the P ⁺ back gate layer 21, but may be equally spaced depending on the design. . Further, the width of the N ⁺ source layer 7 is P ⁺ back gate layer 21.
Narrower than the width is also possible. The same applies to the arrangement of the N layer 23 and the P layer 22.

The P ⁺ back gate layer 21 is electrically connected to the P base layer 6 and the source electrode.
It acts as a back gate that stabilizes the potential.

In the offset portion having the super junction structure, the stripe widths of the N layer 23 and the P layer 22 are designed to be sufficiently smaller than the width of the depletion layer generated in the pn junction in the thermal equilibrium state. Therefore, the drain-source capacitance (Cds) when the power MISFET 20a is off.
, And the drain-gate capacitance (Cgd) can be made smaller than in the first embodiment. When a (+) voltage is applied to the gate, the depleted super junction structure portion is filled with electrons generated by the gate voltage and the resistance is lowered.
The on-resistance Ron of the FET 20a is reduced.

Next, the characteristics of the power MISFET will be described with reference to FIG. FIG. 7 shows the power MI
It is a characteristic view which shows the ON resistance of SFET. Here, the conventional characteristics are obtained when a (+) voltage is applied to the first gate electrode and the drain electrode. In the present embodiment, the (+) voltage is applied to the first gate electrode, the second gate electrode, and the drain electrode. It is a characteristic at the time of applying the voltage of.

As shown in FIG. 7, conventionally, the on-resistance (Ron) of the power MISFET is large. On the other hand, in this embodiment, the same (+) voltage is applied to the first gate electrode 10 and the second gate electrode 15, and the (+) voltage is applied to the drain electrode 14. For this reason, since the first channel portion 16 and the second channel portion 17 are simultaneously turned on, the on-resistance (Ron) of the power MISFET 20a can be reduced as compared with the conventional case. Further, when a voltage of (+) is applied to the gate, the depleted super junction structure portion is filled with electrons generated by the gate voltage and has a low resistance, so that it is lower than in the first embodiment shown by the broken line. Power MISFET
The on-resistance (Ron) of 20a can be reduced.

As described above, in the semiconductor device of this embodiment, the superjunction structure semiconductor layer is formed by repeatedly reducing the width of the stripe compared to the width of the depletion layer generated in the pn junction in the thermal equilibrium state and repeatedly facing the gate portion. An offset portion having a first gate electrode 10;
A power MISFET 20 a having a second gate electrode 15 is provided. And
The threshold voltage when the (+) voltage is applied to the first gate electrode 10 and the second gate electrode 15 is smaller than the threshold voltage when the (+) is applied to the first gate electrode 10. can do. Therefore, an SOI structure power MISFET in which the output terminal capacitance Coff at the time of signal interruption is reduced and the on-resistance Ron is reduced as compared with the first embodiment can be obtained.

[Third Embodiment]
Next, an optical semiconductor relay device according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a diagram illustrating a circuit configuration of the optical semiconductor relay device. In the present embodiment, the power MISFET having the SOI structure of the first embodiment is used.

As shown in FIG. 8, the optical semiconductor relay device 30 includes a light emitting element (LED) 31, a photodiode array (PV) 32, a control circuit 33, and power MISFETs 35 and 36.
It is sealed in a 4 pin resin sealed package.

The light emitting element 31 is composed of a GaAs infrared light emitting diode, and is connected to the input terminals IN1 and IN2. When a relay control signal is applied between the input terminals IN1 and IN2, the light emitting element 3
1 emits light. The emitted light is received by a photodiode array 32 that faces the light emitting element 31 and is spaced apart.

The photodiode array 32 includes n photodiodes 32a, 32b,.
Are connected in cascade. The photodiode array 32 receives the light emitted from the light emitting element 31, so that n times the electromotive force of each of the photodiodes 32a, 32b,. DC voltage is generated. This DC
The voltage is supplied to the input side of the control circuit 33.

The control circuit 33 uses the DC voltage output from the photodiode array 32 as the output signal OP of the control circuit, and the first gate electrode G11, the second gate electrode G21 of the power MISFET 35, and the first gate electrode of the power MISFET 36. G12, second gate electrode G
22 to send. In addition, the control circuit 33 includes a discharge circuit 34 for quickly discharging charges accumulated in the power MISFETs 35 and 36 when the DC voltage output from the photodiode array 32 is not supplied.

In the power MISFET 35, the source electrode S1 and the substrate electrode Sub1 are connected to the low potential side power source Vss of the control circuit 33, and the drain electrode D1 is connected to the output terminal OUT1.
In the power MISFET 36, the source electrode S2 and the substrate electrode Sub2 are connected to the low potential side power source Vss of the control circuit 33, and the drain electrode D2 is connected to the output terminal OUT2.

When the output signal OP of the control circuit is input to the first gate electrode G11, the second gate electrode G21 of the power MISFET 35, and the first gate electrode G12 and the second gate electrode G22 of the power MISFET 36, the power MISFET 35 The first channel portion 16, the second channel portion 17, and the first channel portion 16 and the second channel portion 17 of the power MISFET 36 are turned on, and the output terminals OUT 1 and OUT 2 become conductive, and the optical semiconductor relay The device 30 is turned on.

When the relay control signal is no longer applied between the input terminals IN1 and IN2, the light emitting element 31 stops emitting light, and the DC voltage across the photodiode array 32 becomes zero V. For this reason, the output signal OP of the control circuit becomes zero V, the power MISFETs 35 and 36 are turned off, the output terminals OUT1 and OUT2 are turned off, and the optical semiconductor relay device 30 is turned off.

As described above, in the optical semiconductor relay device of this embodiment, the light in the on state is obtained by using the power MISFET having the SOI structure in which the output-terminal capacitance Coff at the time of signal interruption is reduced and the on-resistance Ron is reduced. The electrical resistance between the output terminals of the semiconductor relay device can be reduced.

Further, since the source-drain capacitance (Csd) of the MISFET is small in the off state of the optical semiconductor relay device, the amount of charge accumulated in the on state can be reduced. Therefore, the switching time from the on state to the off state of the optical semiconductor relay device can be shortened.

[Fourth Embodiment]
Next, a semiconductor device according to a fourth embodiment of the present invention will be described with reference to the drawings.
FIG. 9 is a cross-sectional view showing the semiconductor device. In this embodiment, the power MISFET and the logic MISFET are provided on the same SOI substrate.

Hereinafter, in the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted, and only different portions will be described.

As shown in FIG. 9, the semiconductor device 60 includes a BOX layer (buried oxide film layer) 2 a having a buried silicon layer 37 selectively provided on the first main surface (front surface) of the first silicon substrate 1.
Is formed, and the second silicon substrate 3 is formed on the first main surface (front surface) of the BOX layer 2.
An I substrate 4a is provided. The logic unit 53 includes an Nch MISFET (first MISFE).
T) 51 and Pch MISFET (second MISFET) 52 are provided, and the power MIS
The FET section 54 is provided with a power MISFET 20b.

Here, the buried silicon layer 37 is provided inside the BOX layer 2a. SOI substrate 4
a is formed by bonding the first silicon substrate 1 and the second silicon substrate 3 through a BOX layer (buried oxide film layer) 2a which is a silicon oxide film (formed by high-temperature oxidation of silicon). . Note that the buried silicon layer 37 has N-type impurities.

The second silicon substrate 3 includes an Nch MISFET 51, a Pch MISFET 52,
In addition, an element isolation layer 18 for isolating the power MISFET 20b is embedded so as to be in contact with the BOX layer 2a. Between the element isolation layers 18, a P ^- offset layer 5a and a P layer (first layer) formed from the first main surface (front surface) of the second silicon substrate 3 to the first main surface of the BOX layer 2a. Semiconductor layer) 6a, P layer (second semiconductor layer) 6b, N ⁺ source layer (first
Source layer) 7a, N ⁺ source (second source layer) layer 7b, N ⁺ drain layer (first drain layer) 8a, N ⁺ drain layer (second drain layer) 8b, N layer (third Semiconductor layer) 39
, A P ⁺ source (third source layer) layer 41, a P ⁺ drain layer (third drain layer) 42, and a plug 38 are provided. The plug 38 is made of an N ⁺ polycrystalline silicon film and is in contact with the buried silicon layer 37.

One end of the P layer 6a of the power MISFET 20b is in contact with the P ⁻ offset layer 5a and the other end is in contact with the N ⁺ source layer 7a. The N ⁺ drain layer 8a is in contact with the P ⁻ offset layer 5a. One end of the P layer 6b of the Nch MISFET 51 is in contact with the N ⁺ source layer 7b, and the other end is in contact with the N ⁺ drain layer 8b. The N layer 39 of the Pch MISFET 52 part has one end in contact with the P ⁺ source layer 41 and the other end in contact with the P ⁺ drain layer 42.

Here, the thickness of the second silicon substrate 3 is set to reduce the capacitance such as the gate-drain capacitance (Cgd), the source-drain capacitance (Csd), and the drain-substrate capacitance (Cdsub), for example. The thickness is as thin as 0.1 μm. The buried silicon layer 37 is buried in a region immediately below the P ⁻ offset layer 5a, the P layer 6a, the N ⁺ source layer 7a, and the N ⁺ drain layer 8a, but the P layer 6a and the second channel portion are formed. The minimum possible P ⁻ offset layer 5 a and N ⁺ source layer 7 a may be provided only in the region immediately below.

On the first main surface (surface) of the P layer 6 of the power MISFET 20b portion, at least the first gate electrode 10a made of polycrystalline silicon is adjacent to the P layer 6 via the first gate insulating film 9a. The N ⁺ source layer 7a and the N ⁺ drain layer 8a are provided so as to extend to a part on the first main surface (surface). First main surface (surface) of the P layer 6b of the Nch MISFET 51 part
The third gate electrode 1 made of polycrystalline silicon is disposed above the second gate insulating film 9b.
N ⁺ source layer 7 b and N ⁺ drain layer 8 b so that 0 b is at least adjacent to P layer 6 b
Extending to a part of the first main surface (surface).

On the first main surface (front surface) of the N layer 39 of the Pch MISFET 52 part, at least the fourth gate electrode 10c made of polycrystalline silicon is provided via the second gate insulating film 9b.
Are extended to a part on the first main surface (surface) of the P ⁺ source layer 41 and the P ⁺ drain layer 42 so as to be adjacent to each other. Here, the first gate electrode 10a, the third gate electrode 1
0b and the fourth gate electrode 10c have the same structure and are formed in the same process.

In the insulating film 11 covering the first gate electrode 10a, the third gate electrode 10b, and the fourth gate electrode 10c, contact openings are N ⁺ source layer 7a, N ⁺ drain layer 8a, N ⁺ source layer 7b, N ⁺ drain layer 8b, P ⁺ source layer 41, P ⁺ drain layer 42, and plug 3
8 are respectively provided so as to expose a part of them. Here, the thickness of the first gate insulating film 9a is, for example, larger than that of the second gate insulating film 9b used in the digital semiconductor integrated circuit provided in the logic unit 53 in order to maintain the breakdown voltage of the power MISFET. It is formed thick.

A source electrode 13a is formed on the exposed N ⁺ source layer 7a, a drain electrode 14a is formed on the exposed N ⁺ drain layer 8a, and a source electrode 13b is formed on the exposed N ⁺ source layer 7b. A drain electrode 14b is formed on the exposed N ⁺ drain layer 8b. A source electrode 13 c is formed on the exposed P ⁺ source layer 41, and a drain electrode 14 c is formed on the exposed P ⁺ drain layer 42. A second gate electrode 15 a is formed on the exposed plug 38.

As described above, the semiconductor device according to the present embodiment includes the first gate electrode 10a and the second gate electrode 15a, reduces the inter-output-terminal capacitance Coff when the signal is interrupted, and has an on-resistance R.
A power MISFET portion 54 having a power MISFET 20b with reduced on and a logic portion including an Nch MISFET 51 and a Pch MISFET 52 that operate at a low voltage are formed on the SOI substrate 4a. The first gate electrode 10a, the third gate electrode 10b, and the fourth gate electrode 10c have the same structure and are manufactured in the same process, and the elements are separated from each other by the element isolation layer 18.

Therefore, power MISFE operating at a high speed with a low CR product (CoffxRon).
T, MISFETs that operate at high speed with low voltage and low power consumption can be realized relatively inexpensively in the same chip.

[Fifth Embodiment]
Next, a semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIGS. FIG. 10 is a cross-sectional view showing the semiconductor device, FIG. 11 is an operation explanatory view of the semiconductor device, and FIG. 12 is a plan view showing the arrangement of each part.

In the present embodiment, the source portion of the power MISFET 20 has a high impurity concentration and a low resistance N.
^In addition to the ⁺ layer 7, a P ⁺ back gate layer 21 having a high impurity concentration and a low resistance is provided, and the offset portion 5 is composed of only a P ⁻ layer having a low impurity concentration and a high resistance. Figure 12 is a plan view thereof, ^{P +} width of the back gate layer 21 and the ^{N +} source layer 7 is at substantially equal intervals, the length of the ^{P +} back gate layer 21 is longer than the ^{N +} source layer 7, ^{N +} They can be arranged so as to surround the source layer 7. Other configurations are the same as those of the first embodiment. Back gate part 2
1 is connected to a predetermined voltage in order to keep the substrate potential constant.

Now, when the voltage of the first gate 10 is increased, channel portions 16 and 17 are formed from the P layer 6 to the P ^- offset layer 5 in the ON state as shown in FIG. P ^- in the offset layer 5, the electron reaches the ^{N +} drain region by diffusion, the P ^- the offset layer 5 P
^- it may be referred to as a drift layer. Further, as described above, since the P ⁻ offset layer 5 also has a function of improving the breakdown voltage, it can also be called a RESURF layer.

[Sixth Embodiment]
Next, a semiconductor device according to a sixth embodiment of the present invention will be described with reference to FIGS. FIG. 13 is a cross-sectional view showing a semiconductor device, FIG. 14 is an operation explanatory view of the semiconductor device, and FIG. 15 is a plan view showing the arrangement of each part.

In the present embodiment, the source portion of the power MISFET 20 has a high impurity concentration and a low resistance N.
^In addition to the ⁺ layer 7, a P ⁺ back gate layer 21 having a high impurity concentration and a low resistance is provided, and the offset portion 5 is composed of only an N ⁻ layer having a low impurity concentration and a high resistance. Figure 15 is a plan view thereof, ^{P +} width of the back gate layer 21 and the ^{N +} source layer 7 is at substantially equal intervals, the length of the ^{P +} back gate layer 21 is longer than the ^{N +} source layer 7, ^{N +} They can be arranged so as to surround the source layer 7. Other configurations are the same as those of the first embodiment. Back gate part 2
1 is connected to a predetermined voltage in order to keep the substrate potential constant.

Now, when the voltage of the first gate 10 is increased, channel portions 16 and 17 are formed from the P layer 6 to the N ^- offset layer 5 in the on state as shown in FIG. In the N ⁻ offset layer 5, electrons reach the N ⁺ drain portion by diffusion, and therefore the N ⁻ offset layer 5 may be referred to as an N ⁻ drift layer. Further, as described above, the N ⁻ offset layer 5 also has a function of improving the breakdown voltage, and can be called a RESURF layer.

In the above-described embodiment, the SOI substrate including the first silicon substrate, the BOX layer, and the second silicon substrate is used. However, a SiC substrate or the like can be used instead of the second silicon substrate. It is.

The present invention is not limited to the above-described embodiment, and is within the scope not departing from the spirit of the invention.
Various modifications are possible.

1 is a cross-sectional view showing a power MISFET according to a first embodiment. It is a schematic diagram showing a power MISFET according to the first embodiment. FIG. 6 is a characteristic diagram showing on-resistance of the power MISFET according to the first embodiment. It is sectional drawing which shows power MISFET which concerns on the modification of 1st Embodiment. It is sectional drawing which shows power MISFET which concerns on the modification of 1st Embodiment. It is a top view showing power MISFET concerning a 2nd embodiment. It is a characteristic view which shows on-resistance of power MISFET which concerns on 2nd Embodiment. It is a figure which shows the circuit structure of the optical semiconductor relay apparatus which concerns on 3rd Embodiment. It is sectional drawing which shows the semiconductor device which concerns on 4th Embodiment. It is sectional drawing which shows power MISFET which concerns on 5th Embodiment. It is operation | movement explanatory drawing of power MISFET which concerns on 5th Embodiment. It is a top view which shows power MISFET concerning a 5th embodiment. It is sectional drawing which shows power MISFET concerning 6th Embodiment. It is operation | movement explanatory drawing of power MISFET which concerns on 6th Embodiment. It is a top view showing power MISFET concerning a 6th embodiment.

Explanation of symbols

1 ... 1st silicon substrate,
2 ... BOX layer (buried oxide film layer),
3 ... second silicon substrate,
4 ... SOI substrate,
5, 50 ... offset layer,
6 ... P layer,
7 ... N ⁺ source layer,
8 ... N ⁺ drain layer,
9: Gate insulating film,
10: First gate electrode,
13 ... Source electrode,
14 ... drain electrode,
15 ... second gate electrode,
16: First channel section,
17 ... second channel section,
20, 20a, 20b ... power MISFET,
21 ... P ⁺ back gate layer,
22 ... P offset layer,
23 ... N offset layer,
90 ... a third gate insulating film,
100: Third gate electrode.

Claims (5)

A semiconductor substrate;
An oxide film layer provided on the first main surface of the semiconductor substrate;
A first conductivity type semiconductor layer provided on the oxide film layer;
An offset layer having a lower impurity concentration than the first conductivity type semiconductor layer provided on the oxide film layer in contact with one end of the first conductivity type semiconductor layer;
A second conductivity type source layer having a higher impurity concentration than the first conductivity type semiconductor layer provided on the oxide film layer in contact with the other end of the first conductivity type semiconductor layer;
A second conductivity type drain layer having a higher impurity concentration than the first conductivity type semiconductor layer provided on the oxide film layer in contact with the offset layer and spaced apart from the first conductivity type semiconductor layer When,
A first gate insulating film provided on the semiconductor layer of the first conductivity type;
A first gate electrode provided on the semiconductor layer of the first conductivity type via the first gate insulating film;
A second gate electrode provided on the second main surface opposite to the first main surface of the semiconductor substrate so as to face the semiconductor layer of the first conductivity type via the oxide film layer and the semiconductor substrate. A semiconductor device comprising: A second gate insulating film provided in the oxide film layer so as to be opposed to the first gate insulating film via the first conductivity type semiconductor layer;
2. The third gate electrode provided in the oxide film layer so as to face the semiconductor layer of the first conductivity type with the second gate insulating film interposed therebetween. Semiconductor device. A semiconductor substrate;
An oxide film layer provided on the first main surface of the semiconductor substrate;
A first conductivity type semiconductor layer provided on the oxide film layer;
A first conductivity type offset layer and a second conductivity type offset layer repeatedly provided on the oxide film layer in contact with one end of the first conductivity type semiconductor layer and adjacent to each other;
A second conductivity type source layer having a higher impurity concentration than the first conductivity type semiconductor layer provided on the oxide film layer in contact with the other end of the first conductivity type semiconductor layer;
The first conductivity type semiconductor provided on the oxide film layer in contact with the first conductivity type offset layer and the second conductivity type offset layer and apart from the first conductivity type semiconductor layer. A drain layer of a second conductivity type having a higher impurity concentration than the layer;
A gate insulating film provided on the semiconductor layer of the first conductivity type;
A first gate electrode provided on the semiconductor layer of the first conductivity type via the gate insulating film;
A second gate electrode provided on the second main surface opposite to the first main surface of the semiconductor substrate so as to face the semiconductor layer of the first conductivity type via the oxide film layer and the semiconductor substrate. A semiconductor device comprising: A semiconductor substrate;
An oxide film layer provided on the first main surface of the semiconductor substrate;
A first conductivity type semiconductor layer provided on the oxide film layer;
An offset layer having a lower impurity concentration than the first conductivity type semiconductor layer provided on the oxide film layer in contact with one end of the first conductivity type semiconductor layer;
A second conductivity type source layer having a higher impurity concentration than the first conductivity type semiconductor layer provided on the oxide film layer in contact with the other end of the first conductivity type semiconductor layer;
Higher impurity concentration than the first conductivity type semiconductor layer provided on the oxide film layer adjacent to the second conductivity type source layer and in contact with the other end of the first conductivity type semiconductor layer A back gate layer of the first conductivity type,
A second conductivity type drain layer having a higher impurity concentration than the first conductivity type semiconductor layer provided on the oxide film layer in contact with the offset layer and spaced apart from the first conductivity type semiconductor layer When,
A gate insulating film provided on the semiconductor layer of the first conductivity type;
A first gate electrode provided on the semiconductor layer of the first conductivity type via the gate insulating film;
A second gate electrode provided on the second main surface opposite to the first main surface of the semiconductor substrate so as to face the semiconductor layer of the first conductivity type via the oxide film layer and the semiconductor substrate. A semiconductor device comprising: A light emitting element to which a relay control signal is input;
A photodiode array that receives light emitted from the light emitting element and generates a voltage;
A semiconductor substrate, an oxide film layer provided on the first main surface of the semiconductor substrate, a first conductivity type semiconductor layer provided on the oxide film layer, and one end of the first conductivity type semiconductor layer An offset layer having a lower impurity concentration than the semiconductor layer of the first conductivity type provided on the oxide film layer in contact with
A source layer of a second conductivity type having a higher impurity concentration than the semiconductor layer of the first conductivity type provided on the oxide film layer in contact with the other end of the semiconductor layer of the first conductivity type; and the offset layer A second conductivity type drain layer having a higher impurity concentration than the first conductivity type semiconductor layer provided on the oxide film layer in contact with the first conductivity type semiconductor layer and spaced apart from the first conductivity type semiconductor layer; A gate insulating film provided on the first conductive type semiconductor layer; a first gate electrode provided on the first conductive type semiconductor layer via the gate insulating film; and a first of the semiconductor substrate. A second gate electrode provided on the second main surface opposite to the main surface on the oxide film layer and the semiconductor layer of the first conductivity type via the semiconductor substrate; A voltage generated by a photodiode array is connected to the first gate electrode and the first gate electrode. Optical semiconductor relay device characterized by comprising a semiconductor element which is supplied to the gate electrode of.

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