JPH09246545A - Semiconductor element for power - Google Patents
Semiconductor element for powerInfo
- Publication number
- JPH09246545A JPH09246545A JP8051291A JP5129196A JPH09246545A JP H09246545 A JPH09246545 A JP H09246545A JP 8051291 A JP8051291 A JP 8051291A JP 5129196 A JP5129196 A JP 5129196A JP H09246545 A JPH09246545 A JP H09246545A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- gate electrode
- groove
- electrode
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 44
- 239000000758 substrate Substances 0.000 claims description 32
- 239000002184 metal Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 19
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical group [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 9
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 9
- 239000002344 surface layer Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 12
- 229920005591 polysilicon Polymers 0.000 abstract description 12
- 239000012535 impurity Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 23
- 238000010586 diagram Methods 0.000 description 6
- 238000005452 bending Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、低オン抵抗で、
トレンチゲート構造を有する縦型の電力用半導体素子に
関する。TECHNICAL FIELD The present invention has a low on-resistance,
The present invention relates to a vertical power semiconductor device having a trench gate structure.
【０００２】[0002]
【従来の技術】電力用半導体素子には、用途に応じて種
々の構造が適用されている。図６は従来製造されてい
る、低オン抵抗を有するトレンチ構造の縦型ＭＯＳＦＥ
Ｔである。ｎ形の半導体基板１にｎ+ ドレイン領域７、
ｎドリフト領域６ａ、ｐベース領域１４、ｎ+ ソース領
域４が形成され、ゲート溝１３上にゲート絶縁膜３を介
してｎ形の不純物原子がドーピングされたゲート電極２
ｂが形成されている。ソース電極８はｎ+ ソース領域４
とｐベース領域１４とに接触している。この構造は単位
セルの密度を向上させて、オン抵抗を小さくできる利点
がある。さらにオン抵抗を下げる目的で提案されている
のが、図７に示したｐｎ接合を一切含まない構造の絶縁
ゲート駆動の電力用半導体素子である。図７において、
ｎ形の半導体基板１の一方の主面の表面層にゲート溝１
３が形成され、このゲート溝１３の表面上にゲート絶縁
膜３を介してゲート電極２ｂが形成される。このゲート
溝１３に囲まれた半導体基板１の表面層にｎ+ ソース領
域４が形成され、ｎ+ ソース領域４上にソース電極８が
形成される。半導体基板１でゲート溝１３に囲まれた領
域はｎ形の第１ドリフト領域５となり、その下の領域は
ｎ形の第２ドリフト領域６となる。半導体基板１の他方
の主面の表面層にｎ+ ドレイン領域７が形成され、ｎ+
ドレイン領域７上にドレイン電極１０が形成される。ゲ
ート電極２ｂはｎ形のポリシリコンで形成される。2. Description of the Related Art Various structures are applied to power semiconductor devices depending on the application. FIG. 6 shows a conventional vertical MOSFET with a trench structure having a low on-resistance.
T. an n + drain region 7 on the n-type semiconductor substrate 1,
A gate electrode 2 in which an n drift region 6a, a p base region 14, and an n + source region 4 are formed, and n type impurity atoms are doped on the gate groove 13 through the gate insulating film 3
b is formed. The source electrode 8 is the n + source region 4
And the p base region 14 are in contact with each other. This structure has an advantage that the density of the unit cell can be improved and the on-resistance can be reduced. Further proposed for the purpose of lowering the on-resistance is an insulated gate drive power semiconductor device having a structure not including any pn junction shown in FIG. In FIG.
The gate groove 1 is formed in the surface layer of one main surface of the n-type semiconductor substrate 1.
3 is formed, and the gate electrode 2b is formed on the surface of the gate groove 13 via the gate insulating film 3. An n + source region 4 is formed in the surface layer of the semiconductor substrate 1 surrounded by the gate groove 13, and a source electrode 8 is formed on the n + source region 4. The region surrounded by the gate groove 13 in the semiconductor substrate 1 becomes the n-type first drift region 5, and the region thereunder becomes the n-type second drift region 6. N + drain region 7 is formed on the surface layer of the other main surface of the semiconductor substrate 1, n +
The drain electrode 10 is formed on the drain region 7. The gate electrode 2b is made of n-type polysilicon.
【０００３】図７の構造の素子は図６に示す従来構造の
素子と異なり、オン時には第１ドリフト領域５のゲート
電極２ｂと対向する面に蓄積層が形成され、この蓄積層
がチャネルとなるため、チャネル抵抗を大幅に低減する
ことができる。またｐｎ接合がないため、ｐｎ接合によ
るキャリアの蓄積がなく、スイッチング時間の短縮がで
き、また電流集中が起こらないため素子の破壊耐量を向
上できる利点を有している。Unlike the conventional structure element shown in FIG. 6, the element having the structure shown in FIG. 7 has a storage layer formed on the surface of the first drift region 5 facing the gate electrode 2b when turned on, and this storage layer serves as a channel. Therefore, the channel resistance can be significantly reduced. Further, since there is no pn junction, carriers are not accumulated due to the pn junction, the switching time can be shortened, and current concentration does not occur, so that there is an advantage that the breakdown resistance of the element can be improved.
【０００４】また図６および図７の素子は絶縁ゲート駆
動型の電力用半導体素子であるが、ゲート電極２ｂはｎ
形のポリシリコンが使われ、電気抵抗を下げるために、
高濃度ドーピングされている。またポリシリコンは高純
度にでき、さらに高温に耐え、加工が容易であり、広く
用いられる。The element shown in FIGS. 6 and 7 is an insulated gate drive type power semiconductor element, but the gate electrode 2b is n.
Shaped polysilicon is used to reduce electrical resistance,
It is heavily doped. Further, polysilicon can be highly purified, can withstand high temperatures, can be easily processed, and is widely used.
【０００５】[0005]
【発明が解決しようとする課題】つぎに、オフ時の動作
を説明すると、ゲート電極を負、ソース電極を正にバイ
アスするとゲート電圧２ｂはゲート絶縁膜３を介して第
１ドリフト領域５および第２ドリフト領域６に印加さ
れ、これらの領域に空乏層１１が拡がり、この空乏層端
１２が密着するとソース電極８とドレイン電極１０間の
電流通路は絶たれ、電流は遮断する。このことは、図７
の素子はゲート電極２ｂに電圧が印加されていないとき
には素子はオン状態になっている。これは電源投入初期
でゲート駆動回路系に電圧が確立していない時期は素子
が短絡状態になるという変換装置に適用する上で極めて
大きな不便さがある。Next, the operation at the time of turning off will be described. When the gate electrode is biased negatively and the source electrode is biased positively, the gate voltage 2b passes through the gate insulating film 3 and the first drift region 5 and the first drift region 5b. When the depletion layer 11 is applied to the two-drift region 6 and the depletion layer 11 spreads in these regions and the depletion layer end 12 adheres to it, the current path between the source electrode 8 and the drain electrode 10 is cut off and the current is cut off. This is illustrated in FIG.
The element is in the ON state when no voltage is applied to the gate electrode 2b. This is extremely inconvenient when applied to a conversion device in which elements are short-circuited when voltage is not established in the gate drive circuit system at the initial stage of power-on.
【０００６】この発明の目的は、前記の課題を解決し
て、ゲート電圧を印加しない状態で、ソース・ドレイン
間の電流通路を高抵抗とするか、この電流通路を遮断す
ることができる絶縁ゲート構造の電力用半導体装置を提
供することにある。An object of the present invention is to solve the above-mentioned problems and to make the current path between the source and the drain have a high resistance or to cut off this current path without applying a gate voltage. An object is to provide a power semiconductor device having a structure.
【０００７】[0007]
【課題を解決するための手段】前記目的を達成するため
に、第一導電形半導体基板の第一主面の表面層に選択的
に溝が形成され、該溝で囲まれた第一主面上にソース電
極が形成され、該溝の表面上に絶縁膜を介してゲート電
極が形成され、第二主面上にドレイン電極が形成される
トレンチ構造のＭＯＳＦＥＴを構成するもので、ソース
電極が前記溝を除く第一導電形半導体基板表面と接触
し、ゲート電極が第二導電形半導体膜で形成される構成
とする。To achieve the above object, a groove is selectively formed in a surface layer of a first main surface of a first conductivity type semiconductor substrate, and a first main surface surrounded by the groove. A source electrode is formed on the trench, a gate electrode is formed on the surface of the groove via an insulating film, and a drain electrode is formed on the second main surface. The gate electrode is formed of the second conductivity type semiconductor film in contact with the surface of the first conductivity type semiconductor substrate except the groove.
【０００８】また第一導電形半導体基板の第一主面の表
面層に選択的に溝が形成され、該溝で囲まれた第一主面
上にソース電極が形成され、該溝の表面上に絶縁膜を介
してゲート電極が形成され、第二主面上にドレイン電極
が形成されるトレンチ構造のＭＯＳＦＥＴを構成するも
ので、ソース電極が前記溝を除く第一導電形半導体基板
表面と接触し、ゲート電極が金属で形成され、該金属の
仕事関数をΦｍ、基板を形成する半導体の電子親和力を
χ、基板を形成する半導体の禁制帯幅をＥｇ／ｑ（Ｅ
ｇ：エネルギーギャプ、ｑ：電荷）としたとき、Φｍ≧
χ＋Ｅｇ／２ｑが満たされる金属でゲート電極を形成す
ることよい。前記の第一導電形半導体基板をシリコンと
した場合、ゲート電極をニッケル（Ｎｉ）または白金
（Ｐｔ）とするとよい。A groove is selectively formed in the surface layer of the first main surface of the first conductivity type semiconductor substrate, a source electrode is formed on the first main surface surrounded by the groove, and a source electrode is formed on the surface of the groove. A gate electrode is formed via an insulating film on the first main surface and a drain electrode is formed on the second main surface to form a MOSFET with a trench structure, in which the source electrode contacts the surface of the first conductivity type semiconductor substrate excluding the groove. The gate electrode is formed of a metal, the work function of the metal is Φm, the electron affinity of the semiconductor forming the substrate is χ, and the band gap of the semiconductor forming the substrate is Eg / q (E
g: energy gap, q: charge), Φm ≧
It is preferable to form the gate electrode with a metal that satisfies χ + Eg / 2q. When the first conductivity type semiconductor substrate is silicon, the gate electrode may be nickel (Ni) or platinum (Pt).
【０００９】この手段を講じることで、ゲートバイアス
が零の場合でもゲート絶縁膜直下に空乏層が拡がり、素
子のインピーダンスを大きくし、単位セルを微細加工す
ることで左右からの空乏層を密着させて、電流通路を遮
断することができる。By taking this measure, even when the gate bias is zero, the depletion layer spreads directly under the gate insulating film, the impedance of the element is increased, and the depletion layers from the left and right are adhered by finely processing the unit cell. The current path can be cut off.
【００１０】[0010]
【発明の実施の形態】図１はこの発明の第１実施例の素
子の要部断面図である。半導体基板１に次に述べる各領
域が形成される。ｎ+ ドレイン領域７上に、第２ドリフ
ト領域６、第１ドリフト領域５が積層され、第１ドリフ
ト領域５上にｎ+ ソース領域４が形成され、ｎ+ ソース
領域４上にソース電極８が形成される。またゲート溝１
３の表面にゲート絶縁膜３が形成され、ゲート絶縁膜３
上にゲート溝１３を埋めるようにゲート電極２が形成さ
れる。このゲート電極２はｐ形の不純物原子をドーピン
グしたポリシリコンで形成されている。そのため、後述
するように、ｎ形の第１ドリフト領域５と第２ドリフト
領域６にゲート電圧が印加されない状態でも空乏層１１
が拡がり電流通路３５が狭まり、この部分のインピーダ
ンスが増大する。単位セルをさらに微細化し、第１ドリ
フト領域５の幅Ｗを狭めれば空乏層端の伸びＬが大きく
なり、左右からの空乏層端１２は密着し、電流通路３５
は閉じられ、電流は遮断されるというノーマリオフ型の
素子となる。尚、ｎ+ ドレイン領域７表面にはドレイン
電極１０が形成されている。FIG. 1 is a sectional view of the essential parts of a device according to a first embodiment of the present invention. Each region described below is formed on the semiconductor substrate 1. The second drift region 6 and the first drift region 5 are stacked on the n + drain region 7, the n + source region 4 is formed on the first drift region 5, and the source electrode 8 is formed on the n + source region 4. It is formed. Also the gate groove 1
The gate insulating film 3 is formed on the surface of the gate insulating film 3.
Gate electrode 2 is formed so as to fill gate trench 13. The gate electrode 2 is made of polysilicon doped with p-type impurity atoms. Therefore, as will be described later, the depletion layer 11 is applied to the n-type first drift region 5 and the second drift region 6 even when the gate voltage is not applied.
And the current path 35 narrows, and the impedance of this portion increases. If the unit cell is further miniaturized and the width W of the first drift region 5 is narrowed, the extension L of the depletion layer end is increased, the depletion layer ends 12 from the left and right are closely attached, and the current passage 35 is formed.
Is closed and the current is cut off, resulting in a normally-off type element. A drain electrode 10 is formed on the surface of the n + drain region 7.
【００１１】図２はこの発明の概念を説明する図で、同
図（ａ）はゲート電極がｎ形のポリシリコンの場合のエ
ネルギーバンド図、同図（ｂ）はゲート電極がｐ形のポ
リシリコンの場合のエネルギーバンド図である。両図と
も半導体基板２３はｎ形であり、ゲートバイアスがゼロ
の場合である。同図（ａ）においては、エネルギーバン
ドの曲がりがなく、そのため半導体基板２３内には空乏
層が拡がらない。同図（ｂ）においては、ゲート電極２
をｐ形のポリシリコンで形成し、且つ高濃度とすると、
半導体基板２３のエネルギーバンドは図のように曲が
る。そのため、曲がった部分が空乏層１１となる。この
空乏層１１が拡がると素子のインピーダンスは大きくな
り、さらに拡がると電流通路を遮断することになる。こ
のエネルギーバンドの曲がりはｎ形のゲート電極２ｂに
バンドギャップである−１．２Ｖの負電圧が印加された
場合と等価になる。2A and 2B are views for explaining the concept of the present invention. FIG. 2A is an energy band diagram when the gate electrode is n-type polysilicon, and FIG. 2B is a p-type gate electrode. It is an energy band figure in the case of silicon. In both figures, the semiconductor substrate 23 is n-type and the gate bias is zero. In the same figure (a), there is no bending of the energy band, so that the depletion layer does not spread in the semiconductor substrate 23. In FIG. 2B, the gate electrode 2
Is formed of p-type polysilicon and has a high concentration,
The energy band of the semiconductor substrate 23 bends as shown. Therefore, the bent portion becomes the depletion layer 11. When the depletion layer 11 expands, the impedance of the element increases, and when it further expands, the current path is cut off. This bending of the energy band is equivalent to the case where a negative voltage of −1.2 V, which is the band gap, is applied to the n-type gate electrode 2b.
【００１２】図３はｎ形のゲート電極に負バイアスを印
加した場合のソース・ドレイン間の電流・電圧特性であ
る。試作した素子はｎ形のゲート電極を有し、第１ドリ
フト領域の幅Ｗが５μｍである。ゲート電圧を０から−
１０Ｖまで１Ｖステップで印加した場合で１象限はドレ
インが正、ソース負の順方向で、３象限が逆方向であ
る。順方向ではゲート電圧を０Ｖと−１Ｖとした場合、
ドレイン・ソース間電圧ＶDSを４Ｖで読むと、ドレイン
・ソース間電流ＩDSが１０Ａと３Ａとなり、−１Ｖの場
合、０Ｖに対してインピーダンスが３倍程度大きくな
る。ゲート電圧を−３Ｖより低くしたい場合はドレイン
・ソース間電流ＩDSはゼロとなり電流通路は遮断され
る。図１の構成のようにｐ形のゲート電極とするとゲー
ト電圧を印加しない場合でも、あたかもゲート電圧を−
１．２Ｖ印加したときと等価となる空乏層１１が第１ド
リフト領域５に形成される。これは、図３でゲート電圧
を−１．２Ｖ印加したのと等価となり、大きなインピー
ダンスを持つようになる。さらに、図１において、単位
セルを微細化し、第１ドリフト領域５の幅Ｗを狭めれ
ば、空乏層端１２が密着し、ゲート電圧を印加しなくて
も、電流通路３５が閉じてノーマリオフ型の素子にな
る。FIG. 3 shows the current-voltage characteristics between the source and drain when a negative bias is applied to the n-type gate electrode. The prototyped device has an n-type gate electrode, and the width W of the first drift region is 5 μm. Gate voltage from 0-
In the case where the voltage is applied in steps of 1 V up to 10 V, the drain is positive and the source is negative in the first quadrant, and the third quadrant is in the reverse direction. In the forward direction, when the gate voltage is 0V and -1V,
When the drain-source voltage VDS is read at 4V, the drain-source current IDS becomes 10A and 3A, and in the case of -1V, the impedance becomes about three times larger than 0V. When the gate voltage is desired to be lower than -3V, the drain-source current IDS becomes zero and the current path is cut off. Even if the gate voltage is not applied when the p-type gate electrode is used as in the configuration of FIG.
A depletion layer 11 is formed in the first drift region 5, which is equivalent to that when 1.2 V is applied. This is equivalent to applying a gate voltage of -1.2 V in FIG. 3 and has a large impedance. Further, in FIG. 1, if the unit cell is miniaturized and the width W of the first drift region 5 is narrowed, the depletion layer end 12 is in close contact, and the current passage 35 is closed even if the gate voltage is not applied. It becomes the element of.
【００１３】図４はこの発明の第２実施例の素子の要部
断面図である。図１と異なるのは、ゲート電極２ａを次
式を満たす金属で形成した点である。FIG. 4 is a sectional view of the essential parts of an element according to the second embodiment of the present invention. The difference from FIG. 1 is that the gate electrode 2a is formed of a metal satisfying the following formula.
【００１４】[0014]
【数１】Φｍ≧χ＋Ｅｇ／２ｑ・・・・（１） 〔Φｍ：金属の仕事関数、χ：半導体基板の電子親和
力、Ｅｇ：半導体基板のバンドギャップ、ｑ：電荷〕 前記の金属をゲート電極２ａに用いることで第１実施例
であるｐ形のポリシリコンを用いた場合と同様に第１ド
リフト領域５と第２ドリフト領域６にゲート電圧を印加
しない状態でも第１ドリフト領域５と第２ドリフト領域
６に空乏層１１が拡がり、第１実施例と同様に電流通路
３５のインピーダンスが増大し、さらに単位セルを微細
化することでノーマリオフ型の素子になる。[Formula 1] Φm ≧ χ + Eg / 2q (1) [Φm: work function of metal, χ: electron affinity of semiconductor substrate, Eg: band gap of semiconductor substrate, q: charge] When the gate voltage is not applied to the first drift region 5 and the second drift region 6 as in the case of using the p-type polysilicon according to the first embodiment, the first drift region 5 and the second drift region 2a are used by using the second drift region 5a. The depletion layer 11 spreads in the drift region 6, the impedance of the current passage 35 increases as in the first embodiment, and the unit cell is further miniaturized to form a normally-off type element.
【００１５】図５はゲート電極に図４で示す金属を使用
した場合のエネルギーバンド図である。図の左側がゲー
ト電極に当たる金属２１で絶縁膜２２を挟んで右側にｎ
形の半導体基板２３を示している。真空準位３１から金
属２１のフェルミ準位３２までのエネルギーが仕事関数
Φｍである。また、真空準位３１から伝導帯３３までの
エネルギが電子親和力χであり、伝導帯３３と価電子帯
３４の間のエネルギーがＥｇ／ｑである。ここではエネ
ルギーと表現したが厳密にはポテンシャルのことであ
る。（１）式が成り立つ金属２１の場合、図示されるよ
うに半導体基板２３のエネルギーは曲がり空乏層１１が
拡がる。丁度、ｐ形のポリシリコンをゲート電極２とし
た場合と同様である。この仕事関数Φｍが大きいほど半
導体基板２３側に空乏層１１は拡がるので効果は大きく
なる。半導体基板をシリコンとした場合は、シリコンの
Ｅｇ／ｑは１．２Ｖ、電子親和力が４．０５Ｖとなるの
で、ゲート電極２ａに用いる金属２１の仕事関数は４．
６５Ｖ以上とするとよい。具体的な金属としてはニッケ
ル（Ｎｉ）や白金（Ｐｔ）などがよい。これらの金属を
ゲート電極に用いるとゲートがゼロバイアス時にも半導
体基板２３に空乏層１１が拡がるようになり、素子のイ
ンピーダンスを増大できる。また単位セルを微細化した
りより大きな仕事関数Φｍの金属２１をゲート電極２ａ
に使うことで空乏層端１２を大きく拡げ、電流通路を遮
断することも可能である。つまりノーマリオフ型の素子
を製作することができる。FIG. 5 is an energy band diagram when the metal shown in FIG. 4 is used for the gate electrode. The left side of the figure is n on the right side with the insulating film 22 sandwiched by the metal 21 that corresponds to the gate electrode.
2 shows a semiconductor substrate 23 in the form of a shape. The energy from the vacuum level 31 to the Fermi level 32 of the metal 21 is the work function Φm. The energy from the vacuum level 31 to the conduction band 33 is the electron affinity χ, and the energy between the conduction band 33 and the valence band 34 is Eg / q. Although expressed as energy here, strictly speaking it is potential. In the case of the metal 21 for which the formula (1) is satisfied, the energy of the semiconductor substrate 23 bends and the depletion layer 11 spreads as shown in the figure. Exactly the same as when the gate electrode 2 is made of p-type polysilicon. The larger the work function Φm, the more the depletion layer 11 spreads to the semiconductor substrate 23 side, and the greater the effect. When the semiconductor substrate is silicon, the Eg / q of silicon is 1.2 V and the electron affinity is 4.05 V. Therefore, the work function of the metal 21 used for the gate electrode 2a is 4.
It is better to set it to 65V or more. As a specific metal, nickel (Ni), platinum (Pt), or the like is preferable. When these metals are used for the gate electrode, the depletion layer 11 spreads on the semiconductor substrate 23 even when the gate is zero biased, and the impedance of the element can be increased. Further, the unit cell is miniaturized, and the metal 21 having a larger work function Φm is used for the gate electrode 2a.
It is also possible to greatly expand the depletion layer edge 12 and cut off the current path. That is, a normally-off type element can be manufactured.
【００１６】[0016]
【発明の効果】この発明によれば、ｐｎ接合を有さない
トレンチ構造の電圧駆動型素子で、ゲート電極にｐ形の
ポリシリコンや前記（１）式が成立する金属を用いるこ
とで、ゲート零バイアス時でもドレイン・ソース間抵抗
（素子のインピーダンス）の大きい素子や、電流通路を
遮断するノーマリオフ型の素子を得ることができる。ま
た、この素子はオン状態では極めて低いオン電圧とな
る。さらに、この素子を変換装置に適用すると、電源投
入時のゲート電圧が低い状態でも回路が短絡状態に陥る
ことはなく、通常のゲート回路で安定して変換装置を運
転できる。According to the present invention, in a voltage-driven element having a trench structure having no pn junction, by using p-type polysilicon or a metal satisfying the above formula (1) for the gate electrode, It is possible to obtain an element having a large drain-source resistance (impedance of the element) even at the time of zero bias, and a normally-off type element that interrupts a current path. Further, this element has an extremely low on-voltage in the on-state. Furthermore, when this element is applied to a converter, the circuit does not fall into a short circuit state even when the gate voltage is low when the power is turned on, and the converter can be stably operated with a normal gate circuit.
【図１】この発明の第１実施例の素子の要部断面図FIG. 1 is a sectional view of an essential part of an element according to a first embodiment of the present invention.
【図２】この発明の概念を説明する図で（ａ）はゲート
電極がｎ形のポリシリコンの場合のエネルギーバンド
図、（ｂ）はゲート電極がｐ形のポリシリコンの場合の
エネルギーバンド図2A and 2B are views for explaining the concept of the present invention, wherein FIG. 2A is an energy band diagram when the gate electrode is n-type polysilicon, and FIG. 2B is an energy band diagram when the gate electrode is p-type polysilicon.
【図３】ｎ形のゲート電極に負バイアスを印加した場合
のソース・ドレイン間の電流・電圧特性図FIG. 3 is a current-voltage characteristic diagram between a source and a drain when a negative bias is applied to an n-type gate electrode.
【図４】この発明の第２実施例の素子の要部断面図FIG. 4 is a sectional view showing the principal part of an element according to a second embodiment of the present invention.
【図５】ゲート電極に図４で示す金属を使用した場合の
エネルギーバンド図FIG. 5 is an energy band diagram when the metal shown in FIG. 4 is used for the gate electrode.
【図６】従来のトレンチ構造の縦型ＭＯＳＦＥＴの要部
断面図FIG. 6 is a cross-sectional view of a main part of a conventional vertical MOSFET having a trench structure.
【図７】従来のｐｎ接合を一切含まない構造の絶縁ゲー
ト駆動の電力用半導体素子の要部断面図FIG. 7 is a cross-sectional view of a main part of a conventional power semiconductor device driven by an insulated gate, which does not include any pn junction.
１ 半導体基板 ２ ゲート電極 ２ａ ゲート電極 ２ｂ ゲート電極 ３ ゲート絶縁膜 ４ ｎ+ ソース領域 ５ 第１ドリフト領域 ６ 第２ドリフト領域 ６ａ ドリフト領域 ７ ｎ+ ドレイン領域 ８ ソース電極 ９ ゲート電極 １０ ドレイン電極 １１ 空乏層 １２ 空乏層端 １３ ゲート溝 ２１ 金属 ２２ 絶縁膜 ２３ 半導体基板 ３１ 真空準位 ３２ フェルミ準位 ３３ 伝導帯 ３４ 価電子帯 ３５ 電流通路 Ｌ 空乏層端の伸び Ｗ 第１ドリフト領域の幅1 semiconductor substrate 2 gate electrode 2a gate electrode 2b gate electrode 3 gate insulating film 4 n + source region 5 first drift region 6 second drift region 6a drift region 7 n + drain region 8 source electrode 9 gate electrode 10 drain electrode 11 depletion Layer 12 Depletion layer edge 13 Gate groove 21 Metal 22 Insulating film 23 Semiconductor substrate 31 Vacuum level 32 Fermi level 33 Conduction band 34 Valence band 35 Current path L Extension of depletion layer edge W Width of first drift region
Claims (3)
に選択的に溝が形成され、該溝で囲まれた第一主面上に
ソース電極が形成され、該溝の表面上に絶縁膜を介して
ゲート電極が形成され、第二主面上にドレイン電極が形
成されるトレンチ構造のＭＯＳＦＥＴを構成するもの
で、ソース電極が前記溝を除く第一導電形半導体基板表
面と接触し、ゲート電極が第二導電形半導体膜で形成さ
れることを特徴とする電力用半導体素子。1. A groove is selectively formed on a surface layer of a first main surface of a first conductivity type semiconductor substrate, and a source electrode is formed on the first main surface surrounded by the groove, and a surface of the groove. A MOSFET having a trench structure in which a gate electrode is formed via an insulating film and a drain electrode is formed on a second main surface, and the source electrode is the surface of the first conductivity type semiconductor substrate excluding the groove and A power semiconductor device, which is in contact with and has a gate electrode formed of a second conductivity type semiconductor film.
に選択的に溝が形成され、該溝で囲まれた第一主面上に
ソース電極が形成され、該溝の表面上に絶縁膜を介して
ゲート電極が形成され、第二主面上にドレイン電極が形
成されるトレンチ構造のＭＯＳＦＥＴを構成するもの
で、ソース電極が前記溝を除く第一導電形半導体基板表
面と接触し、ゲート電極が金属で形成され、該金属の仕
事関数をΦm 、基板を形成する半導体の電子親和力を
χ、基板を形成する半導体の禁制帯幅をＥｇ／ｑ（Ｅ
ｇ：バンドギャプ、ｑ：電荷）としたとき、Φｍ≧χ＋
Ｅｇ／２ｑが満たされる金属でゲート電極を形成するこ
とを特徴とする電力用半導体素子。2. A groove is selectively formed in a surface layer of a first main surface of a first conductivity type semiconductor substrate, a source electrode is formed on the first main surface surrounded by the groove, and a surface of the groove. A MOSFET having a trench structure in which a gate electrode is formed via an insulating film and a drain electrode is formed on a second main surface, and the source electrode is the surface of the first conductivity type semiconductor substrate excluding the groove and In contact with each other, the gate electrode is formed of a metal, the work function of the metal is Φ m, the electron affinity of the semiconductor forming the substrate is χ, and the band gap of the semiconductor forming the substrate is Eg / q (E
g: band gap, q: charge), Φm ≧ χ +
A power semiconductor element, characterized in that the gate electrode is formed of a metal satisfying Eg / 2q.
合、ゲート電極をニッケル（Ｎｉ）または白金（Ｐｔ）
とすることを特徴とする請求項２記載の電力用半導体素
子。3. When the first conductivity type semiconductor substrate is silicon, the gate electrode is nickel (Ni) or platinum (Pt).
The power semiconductor element according to claim 2, wherein
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8051291A JPH09246545A (en) | 1996-03-08 | 1996-03-08 | Semiconductor element for power |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8051291A JPH09246545A (en) | 1996-03-08 | 1996-03-08 | Semiconductor element for power |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09246545A true JPH09246545A (en) | 1997-09-19 |
Family
ID=12882830
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8051291A Pending JPH09246545A (en) | 1996-03-08 | 1996-03-08 | Semiconductor element for power |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09246545A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001156288A (en) * | 1999-11-25 | 2001-06-08 | Toyota Motor Corp | Semiconductor device |
| JP2003517725A (en) * | 1999-08-10 | 2003-05-27 | イノベイティブ・テクノロジー・ライセンシング・エルエルシー | Unipolar field-effect transistor |
| US6787848B2 (en) | 2001-06-29 | 2004-09-07 | Kabushiki Kaisha Toshiba | Vertical type power mosfet having trenched gate structure |
| US6855983B1 (en) | 1998-11-10 | 2005-02-15 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device having reduced on resistance |
| JP2006100360A (en) * | 2004-09-28 | 2006-04-13 | Nissan Motor Co Ltd | Semiconductor device and its manufacturing method |
| JP2006229181A (en) * | 2005-01-19 | 2006-08-31 | Matsushita Electric Ind Co Ltd | Semiconductor device |
-
1996
- 1996-03-08 JP JP8051291A patent/JPH09246545A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6855983B1 (en) | 1998-11-10 | 2005-02-15 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device having reduced on resistance |
| JP2003517725A (en) * | 1999-08-10 | 2003-05-27 | イノベイティブ・テクノロジー・ライセンシング・エルエルシー | Unipolar field-effect transistor |
| JP2001156288A (en) * | 1999-11-25 | 2001-06-08 | Toyota Motor Corp | Semiconductor device |
| US6787848B2 (en) | 2001-06-29 | 2004-09-07 | Kabushiki Kaisha Toshiba | Vertical type power mosfet having trenched gate structure |
| US7045426B2 (en) | 2001-06-29 | 2006-05-16 | Kabushiki Kaisha Toshiba | Vertical type power MOSFET having trenched gate structure |
| JP2006100360A (en) * | 2004-09-28 | 2006-04-13 | Nissan Motor Co Ltd | Semiconductor device and its manufacturing method |
| JP2006229181A (en) * | 2005-01-19 | 2006-08-31 | Matsushita Electric Ind Co Ltd | Semiconductor device |
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