JPH023556B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to a semiconductor device comprising an MIS type (insulated gate type) field effect semiconductor element such as a MOS type field effect transistor.

In MOSFETs, it is conceivable to increase the channel area or channel width in order to increase the current between the source and drain. However, such a configuration inevitably increases the element size, which is disadvantageous for fine patterning of the element and reduces the degree of integration as an IC.

The present invention has been made in consideration of these circumstances, and an object of the present invention is to provide a MIS type FET that can handle a large amount of current and can be patterned finely.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

The configuration of the MIS type FET in this example is shown in Figures 1 to 3.
As shown in the figure. According to this, a field SiO ₂ film 2 is grown on one principal surface of a P-type silicon substrate 1 by a well-known selective oxidation technique, and this SiO ₂
A thin gate insulating film 3 is placed in one element region separated by a film.
A polysilicon gate electrode 4 is provided through the
Furthermore, N ⁺ is applied to the substrate 1 on both sides of this gate electrode.
A type source region 5 and a drain region 6 are formed by diffusion. The gate electrode 4, the gate insulating film 3, the P-type channel portion 7 directly below this, and the N ⁺ -type region 5,
6 constitutes a conventionally known N-channel insulated gate FET.

This example is further characterized in that the same N-channel insulated gate FET is provided over the known FET, and the source and drain regions of both of these FETs are common. That is, a second gate insulating film 8 is formed by a thermal oxidation method on the upper surface of the gate electrode 4 so as to be continuous with the gate insulating film 3, and from above the gate insulating film 3 to above the N ⁺ type regions 5 and 6 is formed. A silicon film 9 is deposited. The middle portion of this silicon film is a P-type channel 10, and the gate electrode 4, gate insulating film 8, and channel portion 10 constitute a second P-channel insulated gate FET. The N ⁺ type source region 11 and drain region 12 of this second FET are formed by converting both sides of the silicon film 9 to N type, and are formed by making both sides of the silicon film 9 N type.
It integrally overlaps the source region 5 and drain region 6 of the FET. In the drawing, for convenience, the N ⁺ type regions 11-5 and 12-6 are shown separated by broken lines, but in reality, they are integrated and should be regarded as one N ⁺ type region. It is. Therefore, the above first and second
The source and drain regions of the FETs are common, and the device is represented by an equivalent circuit as shown in FIG.

As can be understood from the above configuration, the MISFET according to this example has a structure in which the same N-channel insulated gate FETs are stacked on top and bottom, so the current amount between the source and drain of one N-channel FET as a whole is equal to that of one N-channel FET. This is approximately twice as large as that of the FET.
As a result, a large amount of current can flow without increasing the channel area, and the element size is approximately halved for the same amount of current, allowing for finer patterning and greatly improving the degree of integration. I can contribute.

Next, the manufacturing process of MISFET according to this example will be explained in the fourth step.
The diagram will be explained.

First, as shown in FIG. 4A, a field is formed on one main surface of the P-type silicon substrate 1 by a well-known selective oxidation technique.
After growing the SiO ₂ film 2, the oxidation-resistant mask (silicon nitride film) is removed, and a gate oxide film 3 is further grown in one element region. Then, polysilicon is deposited on the entire surface by chemical vapor deposition (CVD) and patterned by photoetching to form a polysilicon gate electrode 4 and its wiring.

Next, as shown in FIG. 4B, after thermally oxidizing the surface of the polysilicon film 4 to grow a thin SiO ₂ film 8,
As shown in FIG. 4C, the gate oxide film at locations corresponding to the source and drain regions is removed by etching to expose the surface of the substrate 1.

Next, as shown in FIG. 4D, a P-type polysilicon film 10 containing P-type impurities (for example, boron) is formed by CVD.
to fully grow. If boron compound gas is mixed with the reaction gas during this CVD, boron can be doped into polysilicon through its thermal decomposition. This doping amount is made to be approximately the same as the impurity concentration of the substrate 1.

Next, as shown in FIG. 4E, a polysilicon film 10 is formed.
After patterning by etching, the SiO ₂ film grown by CVD is etched to form gate electrode 4.
The SiO ₂ film 13 as a mask is left only on the top. In this case, a SiO ₂ film is grown on the entire surface in the state shown in Fig. 4D, and this is first etched to form a mask for etching the polysilicon film in the shape shown in Fig. 4E, and then this mask is etched again. It may also be formed on the SiO ₂ film 13 shown in FIG. 4E. After the mask 13 is formed as shown in the figure, the entire surface is irradiated with an ion beam 14 of N-type impurity, such as phosphorus or arsenic, to form the polysilicon film 1 in the area where the mask 13 is not present.
ion implantation into N ⁺ type polysilicon regions 11 and 12 that will become source or drain regions.
selectively formed. Through this ion implantation, N type impurities may be partially implanted into the substrate 1 as shown in the figure to form N ⁺ type crystalline silicon regions 5 and 6 under the polysilicon regions 11 and 12.

Next, as shown in FIG. 4F, the SiO ₂ film 13 is removed by etching, the entire surface is further irradiated with a laser beam 15, and the entire polysilicon 10, 11, 12 is subjected to laser annealing using the thermal energy of this laser beam. . As a result, each of these polysilicon regions is made into a single crystal, of which the P-type polysilicon region becomes the P-type channel part 10 of the second MISFET, and the N ⁺ -type polysilicon region becomes the N ⁺ -type monocrystalline silicon region on the substrate 1 side. An N ⁺ type single crystal source region 11 and a drain region 12 are formed integrally with the crystal regions 5 and 6.

Next, a phosphosilicate glass film 16 (see FIG. 1) is formed on the entire surface by CVD, and predetermined portions of the film are removed by photo-etching, and then aluminum is deposited on the entire surface and patterned to form the source electrode 17 shown in FIG. A drain electrode 18 and necessary aluminum wiring are formed.

Although the present invention has been illustrated above, the embodiments described above can be further modified based on the technical idea of the present invention. For example, the pattern of the second MISFET can be varied, and the conductivity type of the semiconductor portion of each FET can also be changed. In the above example, the upper and lower MISFETs
The threshold voltages may be the same or may be made different by doping the channel portion with impurities. For example, each FET can be a depletion type or an enhancement type. Also,
In order to improve the film quality of the polysilicon film 10, after the polysilicon is deposited, this polysilicon is irradiated with a laser.
It is also possible to try to make polysilicon into a single crystal. Also,
In order to form the P-type polysilicon film shown in FIG. 4D, a polysilicon film containing no impurities may be grown first, and then ions such as boron or the like may be implanted into the entire surface. Furthermore, as a method for forming the source/drain regions, the source/drain regions may be formed by ion implantation or thermal diffusion in the state shown in FIG. 4B or 4C.
After doping the drain region with an N-type impurity such as phosphorus or arsenic, a polysilicon film 10 is grown in a vapor phase. Thereafter, a laser beam 15 is irradiated, and the entire polysilicon 10, 11, 12 is subjected to laser annealing using the thermal energy of the laser beam.
As a result, in addition to single crystallization of each of these polysilicon regions, the N-type impurity doped in the source and drain regions of the substrate diffuses into the polysilicon film, forming self-junction type source and drain regions. It becomes possible to form

As described above, in the present invention, channel portions are formed above and below the gate electrode, and the source and drain regions of the first and second MISFETs are provided in common on both sides of the channel portion.
This allows the current between the source and drain to be increased, and since this increase in current can be achieved with a stacked structure of both FETs, the element area does not increase, allowing for fine patterning and high integration. Can be done.

[Brief explanation of drawings]

The drawings show an embodiment of the present invention, and FIG. 1 is a cross-sectional view of a MOSFET, FIG. 2 is a plan view of FIG. The equivalent circuit diagrams of the MOSFET, FIGS. 4A to 4F, are cross-sectional views showing the method of manufacturing the MOSFET in the order of steps. In addition, in the symbols used in the drawings, 3
and 8 is a gate oxide film, 4 is a gate electrode, 5 and 11 are source regions, 6 and 12 are drain regions,
7 and 10 are channel parts, 17 is a source electrode, 1
8 is a drain electrode.

Claims (1)

[Claims] 1. In a semiconductor device comprising a MIS type field effect semiconductor element having a gate electrode provided on a semiconductor substrate via a gate insulating film, and having the semiconductor substrate under the gate insulating film as a channel part, A second gate insulating film that is continuous with the gate insulating film is formed on the gate electrode, and a semiconductor layer is deposited from above the second gate insulating film to the MIS type field effect semiconductor element, and is connected to the gate electrode. The second gate insulating film and the semiconductor layer forming a channel portion on the second gate insulating film
The MIS type field effect semiconductor device is composed of
A semiconductor device characterized in that source and drain regions of both MIS type field effect semiconductor elements are provided in common on both sides of the semiconductor layer.