JPS63278273A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63278273A JPS63278273A JP9873087A JP9873087A JPS63278273A JP S63278273 A JPS63278273 A JP S63278273A JP 9873087 A JP9873087 A JP 9873087A JP 9873087 A JP9873087 A JP 9873087A JP S63278273 A JPS63278273 A JP S63278273A
- Authority
- JP
- Japan
- Prior art keywords
- region
- film
- semiconductor
- substrate
- source region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052796 boron Inorganic materials 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 239000000969 carrier Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000007667 floating Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は、半導体装置に係わり、特に絶縁膜上に形成さ
れた半導体膜に電界効果型トランジスタを設けた半導体
装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a field effect transistor is provided in a semiconductor film formed on an insulating film.
（従来の技術）
近年、シリコン酸化膜等の絶縁膜上に単結晶半導体膜を
形成し、この半導体膜にＭＯＳ）ランジスタ等の素子を
形成する技術が開発されている。(Prior Art) In recent years, a technology has been developed in which a single crystal semiconductor film is formed on an insulating film such as a silicon oxide film, and an element such as a MOS transistor is formed on this semiconductor film.
絶縁膜上に形成された半導体素子は寄生容量が小積層す
ることが可能であり、高集積、多機能化の点で非常に有
利である。Semiconductor elements formed on an insulating film can be laminated with small parasitic capacitance, which is very advantageous in terms of high integration and multifunctionality.
ところで、絶縁膜上に作成されたＭＯＳ）ランジスタに
おいては、基板に相当する半導体膜はフローティングの
状態となる。半導体膜がフローテインクの状態となるこ
とは、ゲートとの容量結合によって半導体基板の電位が
変動すること、また素子の微細化に伴いドレイン近傍で
生じる余剰キャリアを効率良く収集できないこと等、素
子の特性を安定させる」二で好ましくない。By the way, in a MOS transistor formed on an insulating film, the semiconductor film corresponding to the substrate is in a floating state. The floating state of the semiconductor film is caused by the fluctuation of the potential of the semiconductor substrate due to capacitive coupling with the gate, and the inability to efficiently collect surplus carriers generated near the drain due to miniaturization of the device. "Stabilize the characteristics" 2 is unfavorable.
そこで、第３図に示す如く基板電極を追加することによ
り、半導体膜に所定の基板バイアスを与えることが考え
られるが、この場合、基板電極の追加により素子面積が
大きくなり、半導体装置の微細化及び高集積化に不利で
ある。なお、第３図（ａ）は平面図であり、第３図（ｂ
）は同図（ａ）の矢視Ｂ−Ｂ断面図である。また、図中
３１はＳｉ基板、３２は下地絶縁膜としての５ｉ０２膜
、３３はＳｏｌとしてのＳｉ膜、３４はゲート酸化膜、
３５はゲート電極、３６は基板電極、３７゜’、、３’
ｌ、８はソース・ドレイン領域、４１は５ｉ０２膜、１
、。Therefore, it is possible to apply a predetermined substrate bias to the semiconductor film by adding a substrate electrode as shown in FIG. And it is disadvantageous for high integration. Note that FIG. 3(a) is a plan view, and FIG. 3(b) is a plan view.
) is a sectional view taken along the line B-B in FIG. In the figure, 31 is a Si substrate, 32 is a 5i02 film as a base insulating film, 33 is a Si film as Sol, 34 is a gate oxide film,
35 is a gate electrode, 36 is a substrate electrode, 37°', 3'
l, 8 are source/drain regions, 41 is a 5i02 film, 1
,.
１ ＞＋
このように従来、絶縁膜」−の半導体膜に形成したＭＯ
Ｓトランジスタにおいては、半導体膜をフローティング
の状態で用いることは望ましくなく、またこれを避ける
ために基板電極を設けると素子面積が大きくなると云う
問題があった。1>+ In this way, conventionally, an MO formed on a semiconductor film of an insulating film
In an S transistor, it is not desirable to use a semiconductor film in a floating state, and if a substrate electrode is provided to avoid this, there is a problem in that the device area increases.
本発明は上記事情を考慮してなされたもので、その目的
とするところは、素子面積を大きくすることなく、半導
体膜に所定の基板電位を与えることができ、半導体膜に
形成する半導体素子の特性向上及び微細化をはかり得る
半導体装置を提供することにある。The present invention has been made in consideration of the above circumstances, and its purpose is to be able to apply a predetermined substrate potential to a semiconductor film without increasing the device area, and to improve the stability of semiconductor elements formed on the semiconductor film. An object of the present invention is to provide a semiconductor device whose characteristics can be improved and miniaturized.
［発明の構成］
（問題点を解決するだめの手段）
本発明の骨子は、半導体膜中に発生した余剰キャリアを
効率良く収集するための基板電極としての半導体領域を
設けることにあり、さらにこの半導体領域をソースの下
部や周囲等に設けることにより、素子面積の増大を抑え
ることにある。[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to provide a semiconductor region as a substrate electrode for efficiently collecting surplus carriers generated in a semiconductor film, and The purpose is to suppress an increase in the element area by providing a semiconductor region under or around the source.
即ち本発明は、絶縁膜上に形成された第１導電型半導体
膜に第２導電型のソース・ドレイン領域うにしたもので
ある。That is, in the present invention, a first conductivity type semiconductor film formed on an insulating film is provided with a second conductivity type source/drain region.
（作用）
本発明によれば、第１導電型半導体領域を形成すること
により、ソース電極の下部或いは周囲に形成された高濃
度の第１．第２導電型の接合を通して半導体膜の電位変
動を抑えて、半導体膜中に発生した余剰キャリアを効率
良く収集することが可能であり、これにより素子特性が
著しく向上する。また、この基板電極として作用する第
１導電型半導体領域をソース電極の下部或いは周囲に配
置するため、素子面積を増大させることなく」−記の効
果を発揮することが可能であり、微細化及び高集積化に
も有効である。(Function) According to the present invention, by forming the first conductivity type semiconductor region, the highly concentrated first conductivity type semiconductor region formed under or around the source electrode. Through the junction of the second conductivity type, it is possible to suppress potential fluctuations in the semiconductor film and efficiently collect surplus carriers generated in the semiconductor film, thereby significantly improving device characteristics. In addition, since the first conductivity type semiconductor region that acts as the substrate electrode is placed below or around the source electrode, it is possible to achieve the effects mentioned above without increasing the device area. It is also effective for high integration.
（実施例） 以下、本発明の詳細を図示の実施例によって説明する。(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.
第１図は本発明の一実施例に係わる半導体装置の製造工
程を示す断面図である。まず、第１図（ａ）に示す如く
、シリコン基板１１上にスパッタ或いはＣＶＤ法により
シリコン酸化膜（絶縁膜）−夕によるアニール法を用い
て、多結晶シリコン膜を単結晶化し、ｐ型車結晶シリコ
ン膜（第１導電型半導体膜）１３を形成した。ここで、
シリコン酸化膜１２及び単結晶シリコン膜１３からＳＯ
Ｉ単結晶シリコン基板が形成される。FIG. 1 is a cross-sectional view showing the manufacturing process of a semiconductor device according to an embodiment of the present invention. First, as shown in FIG. 1(a), a polycrystalline silicon film is made into a single crystal by sputtering or CVD on a silicon substrate 11 using a silicon oxide film (insulating film) and annealing method. A crystalline silicon film (first conductivity type semiconductor film) 13 was formed. here,
SO from silicon oxide film 12 and single crystal silicon film 13
A single crystal silicon substrate is formed.
次いで、第１図（、ｂ ）に示す如く、素子形成領域を
通常の写真蝕刻法を用いて島状にパターニングする。次
いで、第１図（ｃ）に示す如く、酸素雰囲気中での熱酸
化によりゲート酸化膜１４を４００人の厚さに形成して
、通常のＮチャネルＭＯ８）ランジスタの形成方法に従
い、ポリシリコン等からなるゲート電極１５を形成して
パターニングした。Next, as shown in FIG. 1(,b), the element forming region is patterned into an island shape using a conventional photolithography method. Next, as shown in FIG. 1(c), a gate oxide film 14 is formed to a thickness of 400 nm by thermal oxidation in an oxygen atmosphere, and polysilicon etc. are formed according to the usual N-channel MO transistor formation method. A gate electrode 15 was formed and patterned.
次いで、第１図（ｄ）に示す如く、ソース領域の下部の
みにホウ素（Ｂ＋）のイオン注入を行い、高濃度のｐ十
不純物層である基板電極（第１導電型半導体領域）１６
を形成する。このとき、通常のソース・ドレイン形成よ
りも加速電圧を大きくして、イオン注入のピーク濃度が
シリコン膜１３とシリコン酸化膜１２との界面付近に位
置するよイン領域１８の形成のためのイオン注入を行う
。Next, as shown in FIG. 1(d), boron (B+) ions are implanted only into the lower part of the source region to form a substrate electrode (first conductivity type semiconductor region) 16 which is a highly concentrated p-doped layer.
form. At this time, the acceleration voltage is set higher than that for normal source/drain formation, and the ion implantation for forming the in-region 18 is performed so that the peak concentration of the ion implantation is located near the interface between the silicon film 13 and the silicon oxide film 12. I do.
このとき、イオン注入のピーク濃度の位置を基板電極１
６を形成する場合に比べて浅くすることにより、容易に
ｎ＋ ｐ小接合を形成することか可能である。また、
このときの不純物としてはヒ素戚いはリン等を用いれば
よい。なお、この状態で基板電極１６はソース領域１７
及びチャネル領域の双方に接することになり、ソース領
域１６を介して所定の基板電位（この場合ソースと同電
位）が与えられるものとなる。At this time, the position of the peak concentration of ion implantation is set at the substrate electrode 1.
By making the thickness shallower than in the case of forming 6, it is possible to easily form a small n+p junction. Also,
As the impurity at this time, arsenic, phosphorus, etc. may be used. Note that in this state, the substrate electrode 16 is connected to the source region 17.
and the channel region, and a predetermined substrate potential (in this case, the same potential as the source) is applied via the source region 16.
次いで、第１図（ｆ）に示す如く、全面にＣＶＤ酸化膜
２１を堆積し、ソース、ドレイン及びゲートに達するコ
ンタクトホールを形成し、金属配線２２を用いて配線す
る。このとき、配線材料はｎ型及びｐ型半導体とオーミ
ックコンタクトがとれる材料であればよい。Next, as shown in FIG. 1(f), a CVD oxide film 21 is deposited on the entire surface, contact holes reaching the source, drain, and gate are formed, and wiring is provided using metal wiring 22. At this time, the wiring material may be any material as long as it can make ohmic contact with the n-type and p-type semiconductors.
かくして作成された本装置においては、素子形成領域を
増加させることなく、素子の基板電位をソース電位に一
致させることができ、トランジスタの特性を安定化する
ことができる。′即ち、ソーめ形成による素子面積の増
大をなくすことができる。また、従来工程に第１図（ｄ
）に示すホウ素のイオン注入工程を付加するのみのでよ
く、簡易な工程で実現し得る等の利点もある。In the device thus created, the substrate potential of the element can be made to match the source potential without increasing the element forming area, and the characteristics of the transistor can be stabilized. 'That is, it is possible to eliminate an increase in the element area due to saw formation. In addition, in the conventional process, Figure 1 (d
It is only necessary to add the boron ion implantation process shown in ), which has the advantage that it can be realized with a simple process.
なお、本発明は上述した実施例に限定されるものではな
い。例えば、前記基板電極となる半導体領域１６はソー
スの下部のみに限定されるものではなく、第２図に示す
如くソース領域１７の両側に形成してもよい。ここで、
第２図の矢視Ａ−Ａ断面は第１図（ｆ）と同じである。Note that the present invention is not limited to the embodiments described above. For example, the semiconductor region 16 serving as the substrate electrode is not limited to the lower part of the source, but may be formed on both sides of the source region 17 as shown in FIG. here,
The cross section taken along arrow AA in FIG. 2 is the same as that in FIG. 1(f).
つまり、上記半導体領域はソース領域とチャネル領域と
の双方に接するように形成すればよい。また、第１導電
型半導体膜に形成する素子としては、ＭＯＳトランジス
タに限らずＭＥＳトランジスタにも適用可能である。さ
らに、Ｎチャネルトランジスタに限らず、Ｐチャネルト
ランジスタにも適用できるのは勿論のことである。その
他、本発明の要旨を逸脱しない範囲で、種々変形して実
施することができる。That is, the semiconductor region may be formed so as to be in contact with both the source region and the channel region. Furthermore, the device formed in the first conductivity type semiconductor film is not limited to a MOS transistor, but can also be applied to an MES transistor. Furthermore, it goes without saying that the present invention is applicable not only to N-channel transistors but also to P-channel transistors. In addition, various modifications can be made without departing from the gist of the present invention.
［発明の効果］
子面積を増大することなく基板電位を抑えることができ
、半導体膜中に発生した余剰キャリアを効率良く収集す
ることか可能となる。従って、絶縁膜」二の半導体膜に
形成する半導体素子の特性向上及び高集積化をはかり得
る半導体装置を実現することが可能となる。[Effects of the Invention] The substrate potential can be suppressed without increasing the surface area, and surplus carriers generated in the semiconductor film can be efficiently collected. Therefore, it is possible to realize a semiconductor device in which the characteristics of the semiconductor element formed in the semiconductor film of the insulating film 2 can be improved and the degree of integration can be increased.
第１図は本発明の一実施例に係わる半導体装置の製造工
程を示す断面図、第２図は変形例を説明するための平面
図、第３図は従来の問題点を説明するための平面図及び
断面図である。
１１・・・単結晶シリコン基板、１２シリコン酸化膜（
絶縁膜）、１３・・・単結晶シリコン膜（第１導電型半
導体膜）、１４・・・ゲート酸化膜、１５・・・ゲート
電極、１６・・・基板電極（高濃度第１導電型半導体領
域）、１７・・・ソース領域、１８・・・ドレイン領域
、２１・・・ＣＶＤ酸化膜、２２・・・金属配線。
出願人 工業技術院長 飯塚 幸三
−１〇 −
第１図（２）
、「−−シ／′FIG. 1 is a cross-sectional view showing the manufacturing process of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view for explaining a modified example, and FIG. 3 is a plan view for explaining the conventional problems. They are a figure and a sectional view. 11... Single crystal silicon substrate, 12 Silicon oxide film (
insulating film), 13... single crystal silicon film (first conductivity type semiconductor film), 14... gate oxide film, 15... gate electrode, 16... substrate electrode (high concentration first conductivity type semiconductor) region), 17...source region, 18...drain region, 21...CVD oxide film, 22...metal wiring. Applicant Kozo Iizuka, Director General of the Agency of Industrial Science and Technology -10 - Figure 1 (2), "--shi/'
Claims (3)
導電型のソース・ドレイン領域を形成すると共に、これ
らの間のチャネル領域上にゲート電極を形成してなる半
導体装置において、前記ソース領域及びチャネル領域の
双方に接するように高濃度の第１導電型半導体領域を設
けたことを特徴とする半導体装置。(1) A second conductive type semiconductor film formed on an insulating film
In a semiconductor device in which a conductive type source/drain region is formed and a gate electrode is formed on a channel region between these, a highly doped first conductive type is formed in contact with both the source region and the channel region. A semiconductor device characterized by having a semiconductor region.
ス領域の下部或いは周囲に設けられたものであることを
特徴とする特許請求の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the high concentration first conductivity type semiconductor region is provided below or around the source region.
導電型半導体膜の基板電極として用いられることを特徴
とする特許請求の範囲第１項記載の半導体装置。(3) The high concentration first conductivity type semiconductor region
2. The semiconductor device according to claim 1, wherein the semiconductor device is used as a substrate electrode of a conductive semiconductor film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62098730A JPH0728043B2 (en) | 1987-04-23 | 1987-04-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62098730A JPH0728043B2 (en) | 1987-04-23 | 1987-04-23 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63278273A true JPS63278273A (en) | 1988-11-15 |
| JPH0728043B2 JPH0728043B2 (en) | 1995-03-29 |
Family
ID=14227636
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62098730A Expired - Lifetime JPH0728043B2 (en) | 1987-04-23 | 1987-04-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0728043B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02159767A (en) * | 1988-12-13 | 1990-06-19 | Mitsubishi Electric Corp | Mos field-effect transistor formed in semiconductor layer on insulating substrate |
| US5008723A (en) * | 1989-12-29 | 1991-04-16 | Kopin Corporation | MOS thin film transistor |
| US5264721A (en) * | 1989-04-29 | 1993-11-23 | Fujitsu Limited | Insulated-gate FET on an SOI-structure |
| US6873014B1 (en) * | 1999-01-29 | 2005-03-29 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US6940138B2 (en) * | 1999-07-16 | 2005-09-06 | Seiko Epson Corporation | Semiconductor device, semiconductor gate array, electro-optical device, and electronic equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59220961A (en) * | 1983-05-31 | 1984-12-12 | Toshiba Corp | Complementary mos semiconductor device |
| JPS61278164A (en) * | 1985-06-03 | 1986-12-09 | Hitachi Ltd | Bilateral type thin film semiconductor device |
| JPS6221557U (en) * | 1985-07-24 | 1987-02-09 |
-
1987
- 1987-04-23 JP JP62098730A patent/JPH0728043B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59220961A (en) * | 1983-05-31 | 1984-12-12 | Toshiba Corp | Complementary mos semiconductor device |
| JPS61278164A (en) * | 1985-06-03 | 1986-12-09 | Hitachi Ltd | Bilateral type thin film semiconductor device |
| JPS6221557U (en) * | 1985-07-24 | 1987-02-09 |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02159767A (en) * | 1988-12-13 | 1990-06-19 | Mitsubishi Electric Corp | Mos field-effect transistor formed in semiconductor layer on insulating substrate |
| US5264721A (en) * | 1989-04-29 | 1993-11-23 | Fujitsu Limited | Insulated-gate FET on an SOI-structure |
| US5008723A (en) * | 1989-12-29 | 1991-04-16 | Kopin Corporation | MOS thin film transistor |
| US6873014B1 (en) * | 1999-01-29 | 2005-03-29 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US7094663B2 (en) | 1999-01-29 | 2006-08-22 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US6940138B2 (en) * | 1999-07-16 | 2005-09-06 | Seiko Epson Corporation | Semiconductor device, semiconductor gate array, electro-optical device, and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0728043B2 (en) | 1995-03-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |