JPS59220961A - Complementary mos semiconductor device - Google Patents

Abstract

PURPOSE:To fix the potential of a semiconductor layer without increasing its area by a method wherein semiconductor island regions of different conductivity types are formed on an insulation substrate, which regions are then provided with the source and drain regions of the conductivity types different from that of the island regions, respectively, and a wiring is provided by covering the p-n junction exposed to the side surface of the island regions. CONSTITUTION:The p type and n type semiconductor layers 46 and 47 respectively of island form are provided on the insulation substrate 4 of sapphire, etc., and, with the center of the layer 46 unchanged, a p<+> type layer 51 is diffusion- formed on both sides thereof. Next, the n<+> type source region 521 and drain region 531 are provided thereon. Likewise, with the center of the other n type layer 47 unchanged, the p<+> type drain region 532 and source region 522 overlying an n<+> type layer 54 are provided on both sides thereof. Thereafter, gate electrodes 49 respectively via gate oxide films 501 and 502 are provided between the source and drain regions. After the whole is covered with an SiO2 film 55, windows, are opened, and Al electrodes 57 and 58 are adhered on the junction surface of the regions 51 and 52 with the regions 54 and 522. Besides, the region 531 is connected to the region 532 by means of the electrode 59.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION The present invention relates to improvements in complementary fiMO8 semiconductor devices provided on insulating substrates.

[Technical background of the invention and its problems]

Conventionally, complementary MO8 semiconductor devices on insulating substrates include:
A CMO8/SO8 structure shown in FIGS. 1 and 2 is known. That is, 1 in FIG. 7 is a sapphire substrate, and on this substrate 1, a p-type island-like silicon layer 2 and an n-type island-like silicon layer 3 are provided adjacent to each other. On the surface of the p-type island-like silicon layer 2, n+ type source and drain regions 41+51 which are electrically isolated from each other are provided, and on the semiconductor layer 2 including the channel region between these regions 41151, A dirt electrode 7 is provided with a dirt oxide film 61 interposed therebetween.

Further, on the surface of the n-type island-like silicon layer 3, p+ type source and drain regions 42.5 are electrically isolated from each other.
A dirt electrode 7 is provided on the island-shaped semiconductor layer 3 including the channel region between these regions 42 and 52 with a gate oxide film 62 interposed therebetween. Note that the dirt pole 7 has a U-shape as shown in FIG. 2, and serves as a common electrode for the n-channel and p-channel MO8) transistors. Further, the entire surface is covered with an insulating film 8, and on this insulating film 8, source lead-out interconnections 10 and 11 are provided which are connected to the layer type source region 41sp+ type source region 42 through contact holes 9, 9, respectively. There is. This wiring 10 is fixed to ground (0■), and wiring 11 is fixed to V
It is fixed at DD (+5 V). The insulating film 8
A drain lead-out wiring (Vout) 12 is provided above, which is commonly connected to the 51% P+ type drain region 52 through contact holes 9, 9. Further, on the insulating film 8, there is a dirt lead-out wiring (vi) connected to the r-) electrode 7 through a contact hole 9.
n) 13 are provided.

In the above-mentioned CMO8/SO3, when inputting a PH# level signal (usually about +5V) to Vinl 3, n
Channel MO8) Rannostacha 0 N.

p channel MO8) transistor is OFF l,, Vo
ut12 is at "L" level (near oV).

On the other hand, “in 13” has a “L# level signal (about OV)”
is input, the n-channel MO8) transistor is OF
F, p channel MO8) Turn on the transistor ■. u
At t13, the voltage becomes the VDD level, which is exactly the H# level (near +5V).

However, each MO8) Runnostar channel length (
When Leff n , Leff p in FIG. 1 becomes small, each of the island-shaped semiconductor layers 2 and 3 is in a floating state, so a change occurs in the static characteristics of the transistor, and a current called a kink current flows. This will be explained with reference to FIG.

However, although kink current appears in both n-channel and p-channel, it appears particularly prominently in n-channel, so FIG. 3 shows the case of an n-channel MOS transistor. 21 in Figure 3 is the Zaphire board;
22 is a p-type island silicon layer, 23 and 24 are i-type source and drain regions, and 25 is a dart provided on the silicon layer 22 including the area between the and ft regions 33 and 24 via a dirt oxide film 26. It is an electrode. Reference numeral 27 is a source wiring which is normally fixed to ground (Ov). 28 is a drain wiring, and the voltage applied thereto is VD. Further, 29 is a Tate wiring, and the voltage applied thereto is VG.

In the n-channel MO8) shown in FIG. 3, the VG applied to the dirt wiring 29 is the threshold voltage (V
T), a channel region 30 is formed, and electrons 31 from the source region 23 are attracted by the electric field of vD applied to the drain region 24, and the channel region 30. It travels through the silicon layer region 32 along the channel and reaches the drain region 24, thereby being viewed as a drain current. However, as the channel length becomes shorter, the moving electrons 31 are more likely to induce impact ionization in the silicon layer region 32 due to the high electric field, and as a result, electron-hole pairs are more likely to be generated. The electrons 33 generated here are attracted by the electric field of the drain wiring 28 and flow into the drain region 24, but the holes 34 flow into the silicon layer 22 which is in a floating state. When holes exceeding the forward potential barrier of the pn junction between the source region 23 and the p-type silicon layer 22 are accumulated, an npn transistor is formed by the source region 23, silicon NlI 22, and drain region 24,
A larger amount of current 35 flows.

The static characteristics in which the above-mentioned kink current appears are specifically shown in FIG. 4. The horizontal axis in Figure 4 is the drain voltage■
The vertical axis of D1 is the drain current ID, and the parameters include V
I took G.

Moreover, the solid line in the figure is the structure of Figure 1, and Le f f n
The dotted line indicates the case where the p-oxide silicon layer 2 shown in FIG. 1 is connected to the ground (OV) and its potential is fixed. From FIG. 4, the solid line clearly shows an abnormal current flowing that is similar to bipolar operation, and this is a kink current.

Further, the actual inverter characteristics are shown in FIG.

The solid line in the figure is the inverter characteristic of 0MO8/SO8 shown in FIG. 1, and the dotted line is the inverter characteristic when ground and vDp are connected to the island-like silicon layers 2 and 3 of 0MO8/SO8 shown in FIG. 1, respectively. . As is clear from Fig. 5, the solid line shows °1(
``The level is sufficiently high, and the inverter characteristics become gentle.This can be seen in the characteristics diagram of Fig. 4 mentioned above, for example, when VG21.Ov (inverter Vin=1.0V) (n channel, p channel Since all of the MOS () transistors are ON, the inverter output is determined by the conductance ratio of the n-channel and p-channel MOS () transistors, so a current of only about 10 μA flows as shown by the dotted line. In the solid line, a current of approximately 95 μA flows due to the kink current,
This is because the output level in Figure 5 does not reach a sufficiently high level.Furthermore, if the channel length (Leffn) becomes shorter, the kink current shown in Figure 4 increases, causing a change in the inverter characteristics. In the end, even if Vin is at °'L# level, the signal of "t Hs level" is not output from ■.ut, or conversely, Vin75K "H"
■Even at the level. Since the "L#" level signal is not outputted from ut, the inverter does not exhibit normal inverter characteristics and does not operate as a semiconductor device.

For this reason, as shown in Figures 6 and 7, p
A part of the mold island-like silicon layer 2 and the n-type island-like silicon layer 3 are respectively extended in the channel width direction, and the extending portions 2
Floating of each island-like silicon layer 2, 3 is prevented by creating a structure in which a wiring 14 fixed to ground and a wiring 15 fixed to VDD are connected to a, 3a through contact holes 9, 9, respectively. Prevention is being done. However, in the case of OMO8/SO8 having a single structure, as shown in FIG. 7, an extension portion 2a is provided to fix the potential of each semiconductor layer 2, 3.

3&), it is necessary to separately provide the mi 41 J s, which increases the element area and becomes an impediment to high integration.

In addition, as another improved CMO8/SO8, as shown in FIGS. 8 and 9, p-type island silicon layer 2 and n
A P+ type layer 16 and a layer type layer 17 are respectively formed on the island-like silicon layer 3 of the mold.
Source area 4. . The source region 42 and the n-type layer 1 are connected through the contact hole 9.
A structure in which the wires are connected across 7 is known.

However, in the case of such (JiOS/S O8), each island-like silicon layer 3 has a source.

Since the P+ type layer 16 and the N+ type layer 17 are provided separately from the drain region, the area of each island-shaped silicon layer 2, 3 increases, which becomes an obstacle to high integration.

[Purpose of the invention]

The present invention is an island-shaped semiconductor/? An attempt is made to provide a complementary MO8 semiconductor device in which deterioration of device characteristics due to kink current accompanying short channelization is prevented by connecting sufficient wiring to fix the potential of each semiconductor layer without causing an increase in the area of f. It is something.

[Summary of the invention]

The present invention forms at least a source region in island-shaped semiconductor layers having mutually different conductivities on an insulating substrate so that the bottom surface of the region is separated from the surface of the insulating substrate by a desired distance, and
By providing a wiring that spans both the source region exposed on the top side and the semiconductor layer, it is possible to fix the potential of the semi-solid layer without increasing the area of the semiconductor layer. Make it the gist.

[Embodiments of the invention]

Next, embodiments of the present invention will be described in detail with reference to the manufacturing method shown in FIGS. 10(a) to 11(e) and FIG.

(i) First, a single crystal silicon layer 42 with a thickness of 1 μm was epitaxially grown on a sapphire substrate 41 with a thickness of 500 to 600 μm by thermal decomposition of silane gas (SiH4). Subsequently, the silicon layer 42 is thermally oxidized to grow an Si02 film 43 with a thickness of 900×, and then carbon is applied to the entire surface.
Si 3N4 film 44 with a thickness of about 4500× by VD method
was deposited. Subsequently, a resist pattern 745.45 was formed by photolithography on the island-shaped semiconductor layer portion of the 5i5N4 film (the intended element region portion) (as shown in FIG. 1O(a)).

(ii) Next, the Si3N4 film and the 5i02 film were selectively etched away by RIE using the Lennost pattern 45.45 as a mask, and the patterned 5i02 film was removed by selective etching.
Silicon layer 4 using i5N4 film and 5io2 film as masks
2) Two island-like silicon layers 46 and 47 having a taper angle of about 55° on the sides were formed by selectively etching with an etchant of KOH+inpropyl alcohol.

Next, the resist pattern, Noya Turning Saleta 5
The i5N4 film and the 5i02 film were sequentially removed (as shown in FIG. 10(b)).

(iii') Next, thermal oxidation treatment is performed to form each island y IJ.
Oxide films 4Bl, 4B with a thickness of 500X on the exposed surface of the contact layer,
grew respectively. Next, zolon was applied to the island-like silicon layer 46 at an acceleration voltage of 180 keV and a dose of 2X.
Ion implantation was performed under the conditions of 1012/a♂, and further 7'
Accelerate Tt pressure 40 keV, l'-su amount 4.5
The island-like silicon layer 46 was converted to p-type by ion implantation under the conditions of
Ion implantation was performed under the conditions of a dose of 2×1 O12/cn12, and phosphorus was further accelerated at a voltage of 40 keV and a dose of 1.4.
Ion implantation was performed under the conditions of X 1012/an2 to convert the island-like silicon 1-47 to n-type. After that, a polycrystalline silicon layer containing a high concentration of phosphorus is deposited on the entire surface by CVD method,
This was turned by photoetching technology to form a U-shaped dart electrode 49 extending over a portion of the oxide films 481 and 482 of each island-like silicon layer 46 and 47.
(Illustrated in FIG. 10(C)).

(1v) Then, using the dirt electrode 49 as a mask, the oxide film 481*48g was selectively etched away to form dirt oxide films 501 and 50Q, respectively. Subsequently, after covering the n-type island-shaped silicon layer 47 with a resist pattern (not shown), turn the resist and use the dart electrode 49 as a mask to apply boron to the p-type island-shaped silicon layer 46 at an accelerating voltage of 180 keV and a dose of 5. ×1015/6n2
A boron ion implantation layer having a peak near the interface of the sapphire substrate 41 is formed by ion implantation under the following conditions, and arsenic is further implanted into the island-shaped silicon layer 46 using the same mask at an acceleration voltage of 40 keV and a dose of iAc 2 X 1 o15.
A phosphorus ion implantation layer having a peak near the surface of the silicon layer 46 was formed by ion implantation under the condition of /m2. Subsequently, the cyst pattern is removed and the ion-implanted p-type island-like silicon layer 46 is covered with a resist pattern (not shown).
Using 9 as a mask, phosphorus was applied to n-type island silicon Wi47 at a voltage of 26'0 keV and a dose of 5 x 1015/cI.
A phosphorus ion implantation layer having a peak near the interface of the sapphire substrate 41 is formed by ion implantation under n2 conditions, and boron is further implanted into the island-like silicon layer 47 using a similar mask at an acceleration voltage of 40 keVX and a dose of 2 x 1015/cm.
Ion implantation was performed under the conditions of 2 to form a boron ion implanted layer having a peak near the surface of the silicon layer 47. after that,
The resist pattern was removed and heat treatment was performed. At this time,
・Boron ion implantation layer of p-type silicon island 46.

The arsenic ion-implanted layer is activated and diffused to form an f-type layer 51.5 that is electrically isolated from each other and is in contact with the surface of the sapphire substrate 41.
1 and these p+ ten type fi51゜51 n type turns located in a portion extending from above 51 to the surface of the silicon layer 46 and electrically isolated from each other.

Drain regions 5.21 and 581 were formed, respectively. At the same time, phosphorus ions are implanted into the n-type island silicon layer 47 M +
yl? The ion-implanted layers are activated and diffused to be electrically isolated from each other, and the n+ type layers 54 and 54 are in contact with the surface of the sapphire substrate 41, and these n+ type layers 54. ．． p+ type source and drain regions 522 and 53 located in a portion extending from the top of 54 to the surface of the silicon layer 47 and electrically isolated from each other.
2 were formed respectively (as shown in FIG. 1O(d)).

(V) Next, after depositing a CVD-S i02 film 55 on the entire surface, p CVD-8
Contact holes 561 to 561I were opened in the 102 film 55. Note that the contact hole 561 is formed between the p-type layer 5 and the n-type layer exposed on the tapered side surface of the p-type island-like silicon layer 46.
CV corresponding to the part extending over both of the +-type insertion regions 521
It is formed at the location of the D-5i02 film 55. The contact hole 562 is formed at a location in the C■-3to2 film 55 corresponding to a portion extending over both the n-type layer 54 and the p+ type source region 522 exposed on the tapered side surface of the nff2 island-like silicon layer 47. has been done. In addition, contact hole se3. contact holes 566 are formed in the CVD-8i02 film 55 corresponding to the dirt electrode 49 portion on the sapphire substrate 41. Subsequently, an AtI layer is vapor deposited on the entire surface, and it is butter-filled and connected to both the p+ type layer 51 and the n+ type source region 521 through the contact hole 561, and the AtI wiring 57 is connected to the n+ type source region 521 through the contact hole 562. The At wiring 58 and contact holes 568..5 connected to both the n+ type layer 54 and the p+ type region 622
64, the n+ type and p+ type drain regions 531
, 532, and an At wire 60 connected to the gate electrode 49 via a contact hole 561I, 0MO8/SO8 was manufactured (as shown in FIGS. 10(e) and 11). . Note that FIG. 11 is a plan view of FIG. 10 (,).

(JiO8/SO8 of the present invention is shown in FIG. 10(e) and
As shown in Figure 1, on a sapphire substrate 4, mutually conductive silicon islands of p-type and n-type, each having a chi-shaped side surface, are provided adjacent to each other, and p-type islands are formed. An n+ type source is formed on the surface of the silicon layer 46.

Drain regions 521 and 531 are provided electrically isolated from each other, and p+ type source and drain regions 52□ and 532 are provided electrically isolated from each other on the surface of the n-type island silicon layer 47, and These sources.

Drain region 521, 531 + 52* + 53
P1 type layers 51, 51 and n+ type layers 54, 54 are provided in each island-shaped silicon layer 46, 47 between the bottom surface of 2 and the surface of the sapphire substrate 41, and the source/drain regions 52
Each island-shaped silicon layer 4 between 1.531.522 and 532
6.47 A dirt electrode 49 is provided on each surface through a dirt oxide film 501°50□, and further CVD-5to2 is applied to the entire surface.
The film 55 is covered, and the M wiring 57 is placed on the 5i02 film 55.
Source region 5 on the tapered side surface of the island-like silicon layer 46 of the mold
21 and the p+ type layer 5 under the source region 521 via a contact hole 561, and
A contact hole 5 is formed in both the source region 522 on the tapered side surface of the n-type island-like silicon layer 47 and the n+-type layer 54 below the source region 522.
The structure is connected through 62.

According to the present invention, in the p-type island-like silicon layer 46, the tapered side surface is utilized to connect both the n+-type bottom region 521 and the p+-type layer 51 thereunder via the contact hole 561. The wiring 57 is connected, and the tapered side surface of the n-type island-like silicon layer 47 is used to connect the p + type region 522 and the underlying layer 54.
By connecting the At wiring 58 to both through the contact hole 562, the p-type island silicon layer 46 can be fixed at the V88 potential, and the n-type island silicon layer 47 can be fixed at the VDD potential. Therefore, floating of each silicon island (d 46 and 47) can be prevented without causing an increase in the area of the element region as in the conventional 0MO8/SO8 shown in FIG. 7 or 9, and the channel length (Le
Highly integrated 0MO8/SO8 that prevents the generation of kink current due to shortening of ff) and has good inverter characteristics.
can be obtained.

In addition, in the above embodiment, as shown in FIG. Although the contact holes for the p+ type N51, the p+ type sonic region hJ1.522, and the layered layer 54 are provided at the tapered side surfaces of each island-like silicon layer 46, 47, the present invention is not limited thereto. .

For example, as shown in FIG. 12, a contact hole 561' is provided across the tapered side surface of the p-type island-like silicon layer 46 in which the source region 521 is formed, the surface of the source region 521 on both sides of the side surface, and the sapphire substrate 41 part. A similar contact hole 562' may also be provided on the side of the n-type island silicon layer 47. With such a configuration, the contact area of the At wiring 57 with the n+ type source region 521, the p+ type layer 51, etc. can be increased, and the contact resistance can be reduced and the speed increased.

In the above embodiment, a highly concentrated impurity layer having the same conductivity type as the silicon layer is provided in the island-shaped silicon layer under each source region, but it is not necessary to provide such an impurity layer. however,
In order to reduce the contact resistance with each island-like silicon layer, it is desirable to provide a highly concentrated impurity layer.

In the above embodiment, a high concentration impurity layer is also provided under the drain region, but this impurity layer may not be provided.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to connect wiring for fixing the potential of each semiconductor layer without causing area deterioration of the island-shaped semiconductor layer provided on an insulating substrate. It is possible to provide a complementary type 408 semiconductor device with high performance and high integration, which prevents deterioration of element characteristics due to kink current accompanying short channel length.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view showing the conventional 0MO8/SO8, Fig. 2 is a plan view of the CM'O8/S O8 shown in Fig. 1, and Fig. 3 is a cross-sectional view showing the conventional 0MO8/SO8. Top view of channel MoS/SO8, Figure 4 is MJS/S
Figure 5 is a diagram showing the inverter characteristics of 0MO8/SO8.
The figure is a sectional view showing a conventional improved CMO3/SO8,
7 is a plan view of 0MO8/SO3 shown in FIG. 6, FIG. 8 is a sectional view showing another conventional and improved 0MO8/SO8, and FIG. 9 is a plan view of CMO3/SO8 shown in FIG. Izi
Fig. 11 is a cross-sectional view showing the manufacturing process for obtaining CMO3/SO8 of the present invention, Fig. 11 is a plan view of CMOs and SO8 in Fig.
FIG. 2 is a sectional view of 0MO8/SO8 showing another embodiment of the present invention. 41... Sapphire substrate, 46... P-type island silicon layer, 47... N-type island silicon layer, 49...
Dirt electrode, 501, 5θ2...gate oxide film, 51
... p-type layer, 521, 522 ... source region, 5
31532...Train region, 54...n+ type layer, 55...cVI) -5ioz film, 561-56
5, 561', 5 f'-': 17 tact hole, 57-60...At wiring. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3rlJ Figure 6 Figure 8 Figure 9

Claims (2)

[Claims] (1) An insulating substrate and at least two tapered side surfaces provided adjacent to the substrate and having mutually different conductivities.
two island-shaped semiconductor layers, source and drain regions of opposite conductivity type to the semiconductor layers provided electrically separated from each other on the surface of these semiconductor layers, and an island-shaped semiconductor layer that includes at least the region between the source and drain regions. An insulating film is provided on the semiconductor layer via a gate oxide film and covers the entire surface including each island-like semiconductor layer, and an insulating film is provided on the insulating film and covers each of the island-like semiconductor layers. 1. A complementary MO8 semiconductor device comprising at least wiring connected to a source region on a cheek-shaped side surface and a semiconductor layer portion under the north region through contact holes. (2) A claim characterized in that a highly concentrated impurity layer of the same conductivity type as the semiconductor layer is provided under the north region of each island-shaped semiconductor layer so as to be exposed on the side surface of the semiconductor layer. 1st
Complementary 1MO8 semiconductor device as described in .