JPH0468565A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the performance of an element while reducing the occupied area and improve the integration and performance of an integrated circuit by improving the mutual conductance of a transistor for a CMOS inverter which has a stacked structure. CONSTITUTION:The semiconductor is formed by embedding a gate electrode 2 in an insulating layer (SiO2) 101 formed on the top plane of an insulating substrate 1. A gate insulating film 3 is formed on a gate electrode 2. A channel region 4 is formed on a gate insulating layer 3 and a p-type source region 5 and a drain region 6 are formed on both sides of the channel region 4. An insulating film 7 is formed on the top plane of the channel region 4, the p-type source region 5 and the drain region 6. An n-type source region 9 and a drain region 10 are formed on the insulating film 7 and a channel region 8 are formed between the regions 9 and 10. A gate insulating film 11 is formed on the channel region 8 and a gate electrode 12 is formed on the top of the gate insulating film 11.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor device having a stacked structure and a method for manufacturing the same, an object of the present invention is to provide a semiconductor device having a CMOS inverter having a stacked structure and a method for manufacturing the same in which the mutual conductance of transistors is improved. , a first insulating film formed on the upper surface of the semiconductor substrate, a first gate electrode formed embedded in the first insulating film, and a first gate formed on the first gate electrode. an insulating film, a first channel region of intrinsic or one conductivity type formed on the first gate insulating film, and first source regions of opposite conductivity type formed on both sides of the first channel region. and a drain region, a second insulating film formed on the upper surfaces of the first channel region, the source region and the drain region, and both sides of the second channel region of intrinsic or opposite conductivity type on the second insulating film. a second source region and a drain region of one conductivity type formed on the second channel region, a second gate insulating film formed on the second channel region, and a second gate insulating film formed on the second gate insulating film. 2 gate electrodes.

[Industrial Application Field] The present invention relates to a semiconductor device having a stacked structure and a method for manufacturing the same.

[Conventional technology]

A conventional CMOS inverter has an N-channel transistor and a P-channel transistor formed within the same substrate plane. For this reason, when forming an inverter circuit, an element forming area equivalent to at least two transistors is required. When these two transistors, an N-channel type and a P-channel type transistor, are brought close together, CM
Since the latch-up phenomenon peculiar to OS inverters tends to occur, there is a limit to reducing the area for forming elements.

Therefore, a so-called stacked structure has recently been proposed in which either an N-channel transistor or a P-channel transistor is stacked on top of the other transistor.

Figure 8 shows a proposed CM with a stacked structure.
An OS inverter is shown.

An n-type source region 5 and a drain region 6 are formed on the upper surface of the semiconductor substrate 201, and a channel region 4 is formed therebetween.

A common gate electrode 212 is formed above the channel region 4 with the gate insulating film 3 interposed therebetween. Common gate electrode 212
A P-type source region 9 is formed on the top of the gate insulating film 11 via a gate insulating film 11.
and a drain region 10 are formed, and a channel region 8 is formed therebetween.

In this way, according to the proposed stacked structure transistor, one of the N-channel transistor and the P-channel transistor is formed on top of the other transistor, which has the effect of improving the degree of integration.

[Problems to be Solved by the Invention] However, even with a stacked structure, as the element size decreases, the vertical electric field in the channel due to the gate electrode becomes stronger, similar to the conventional planar structure transistor, and carrier mobility decreases. descend.

As a result, there was a problem in that the mutual conductance of the transistor decreased.

An object of the present invention is to provide a semiconductor device having a stacked structure CMOS inverter with improved mutual contactance of transistors, and a method for manufacturing the same.

[Means for Solving the Problem] The above object is to provide a first insulating film formed on an upper surface of a semiconductor substrate, a first gate electrode formed embedded in the first insulating film, and a first a first gate insulating film formed on the gate electrode, a first channel region of intrinsic or one conductivity type formed on the first gate insulating film, and a first channel region on both sides of the first channel region. The formed first source region and drain region of opposite conductivity type, the second insulating film formed on the upper surface of the first channel region, the source region and the drain region, and the intrinsic region on the second insulating film. or second source and drain regions of one conductivity type formed on both sides of the second channel region of opposite conductivity type, a second gate insulating film formed on the second channel region; This is achieved by a semiconductor device characterized by having a second gate electrode formed on top of a second gate insulating film.

Further, the above object is to form a first gate IS standing almost perpendicularly to a first semiconductor layer on an insulating substrate, and to form a first gate IS on both sides of the first gate electrode with a first gate insulating film interposed therebetween. a second gate insulating film is formed on the surfaces of the first and second semiconductor layers, and a second gate insulating film is formed on the second semiconductor layer on both sides of the first gate electrode. A second gate electrode and a third gate electrode are respectively formed through a gate insulating film, and ions are implanted from an oblique direction on one side of the rising second semiconductor layer using the second gate electrode as a mask. A source region of one conductivity type is formed in the first semiconductor layer, a drain region of one conductivity type is formed on one side of the second semiconductor layer, and a drain region of one conductivity type is formed on one side of the second semiconductor layer. A source region of opposite conductivity type is formed in the first semiconductor layer, and a drain region of opposite conductivity type is formed in the other side of the second semiconductor layer by performing ion implantation from an oblique direction on the side. This is achieved by a method of manufacturing a semiconductor device.

[Operation] According to the present invention, it is possible to realize a semiconductor device having a stacked structure CMOS inverter with improved mutual conductance of transistors.

[Example J Stacked structure CMOS according to the first embodiment of the present invention
The inverter will be explained using FIG.

Insulation @ (S i O□) formed on the top surface of the insulating substrate 1
A gate electrode 2 is formed embedded within 101 . A gate insulating film 3 is formed on the gate electrode 2 . A channel region 4 is formed on the gate insulating WAB, and a p-type source region 5 and a p-type drain region 6 are formed on both sides of the channel region 4.

An insulating film 7 is formed on the upper surfaces of the channel region 4, p-type source region 5, and drain region 6. Insulation I! ! n-type source region 9 and drain region 10 are formed on 7;
A channel region 8 is formed therebetween. A gate insulating WA11 is formed on the channel region 8, and a gate electrode 12 is formed on the gate insulating film 11.

In the stacked structure CMOS inverter according to this embodiment, each gate electrode 2.12 of an N-channel transistor and a P-channel transistor is connected to a channel region 4 of both channels.
．． They are facing each other with 8 in between.

Therefore, the electric field of one gate electrode affects the potential of the other channel region, and as a result, the controllability of the amount of inverted carriers in the other channel region can be improved.

Furthermore, both gate electrodes strengthen each other's effects,
In addition, since the vertical electric field of the inversion channel is relaxed, carrier mobility does not decrease.

Stacked structure CMOS according to the first embodiment of the present invention
A method for manufacturing an inverter will be explained with reference to FIG.

An oxide film (SiO□) 101 is formed by thermally oxidizing the upper surface of the silicon substrate 100, and an insulating substrate 1 is formed (
Figure (a)).

Next, oxidation! ! ! A part of the etching layer 101 is etched to form a region 110 where a gate is to be formed for an N-channel transistor. Next, ion implantation is performed from the upper surface of the insulating substrate 1 to dope the surface of the insulating substrate 1 with arsenic (A s ).

This doping is for the purpose of later forming the source region and drain region of the N-channel transistor in a self-aligned manner by diffusion (FIG. 4(b)).

Next, the upper surface of the oxidized JIIOI and the gate formation region 11
Polycrystalline silicon 2' is deposited on the substrate 0 (FIG. 4(C)).

Next, the polycrystalline silicon 2' is polished to the surface of the oxide film 101 to form a polycrystalline silicon gate electrode i#12 buried in the gate formation region 110 (FIG. 2(d)).

Next, a gate insulation M3 is formed by thermally oxidizing the surface of the gate electrode 2 (FIG. 2(e)).

Next, polycrystalline silicon 112 is deposited on the upper surface of the insulating substrate 1 (FIG. 4(f)).

Next, an active region is defined in this polycrystalline silicon 112 using a phosphorography method. Subsequently, heat treatment is performed to grow the crystal grains of the polycrystalline silicon 112, and at the same time, the arsenic doped into the surface of the insulating substrate 1 is diffused, forming the source region 5 and drain region 6 (see (g) in the same figure). )).

Next, by ion-implanting oxygen <0> from above the insulating substrate 1, an insulating layer M7 is formed on the upper surface of the source region 5 and drain region 6 in the polycrystalline silicon 112, and the channel region 4 and the P channel semiconductor layer 8 are formed. ' is separated and formed ((h) in the same figure).

Next, a gate insulating film 11 is formed on the surface of the P-channel semiconductor layer 8' by thermal oxidation (FIG. 4(i)).

Next, polycrystalline silicon 12' is deposited on the upper surface of the insulating substrate (see (j>) in the same figure).

Next, a gate electrode 12 for a P-channel transistor is defined on the polycrystalline silicon 12' using a phosphorography method (FIG. 4(k)).

Next, by ion-implanting boron (<B) from above the insulating substrate 1, a channel region 8, a source region 9 for a P-channel transistor, and a drain region 1o are formed in the semiconductor layer 8' for a P-channel (see FIG. 1)).

Next, after performing heat treatment and depositing interlayer insulation M13, contact holes are opened, and a source electrode 14 of an N-channel transistor and a source electrode 15 of a P-channel transistor are formed in each contact hole. Common drain electrode 1 of transistors
6 is formed, and the manufacturing process of the semiconductor device according to this embodiment is completed (FIG. 6(m)).

As described above, if the method for manufacturing a semiconductor device according to this embodiment is used, a CM with a small element area and a large driving force can be used.
A semiconductor device having an OS inverter can be manufactured.

Stacked structure CMOS according to the second embodiment of the present invention
The inverter will be explained using FIG. 2.

An insulating film 7 is formed on the insulating substrate 1 almost perpendicularly to the insulating substrate 1.
is formed.

A channel region 4 is formed on one side of the insulating film 7, and a p-type source region 5 is formed on the insulating substrate 1 in contact with the channel region 4. A P-type drain region 6 is formed above the channel region 4 . Gate electrode 2 is formed on the surface of channel region 4 with gate insulating film 3 interposed therebetween.

A channel region 8 is formed on the other side of the insulation WA7. n on the insulating substrate 1 in contact with the channel region 8
A mold source region 9 is formed.

An n-type drain region 10 is formed above the channel region 8 . Gate insulating film 1 on the surface of channel region 8
A gate electrode 12 is formed through the gate electrode 1.

Also in this embodiment, in the stacked structure CMOS inverter, the gate electrodes 2.12 of the N-channel transistor and the P-channel transistor face each other with the channel regions 4.8 of both transistors in between. Therefore, as a result of the electric field of one gate electrode influencing the potential of the other channel region, the controllability of the amount of inverted carriers in the other channel region can be improved. Further, since both gate electrodes mutually enhance their effects and relax the vertical electric field of the inversion channel, carrier mobility does not decrease.

This effect is similar to the effect expected from a thin gSOI-MO3FET or an insulated gate static induction transistor (SIT).

Stacked structure CMOS according to the third embodiment of the present invention
The inverter will be explained using FIG. 4.

In this embodiment, in the semiconductor device described in the first embodiment, a glabella insulating film 17 is formed between the insulating film 7 and the channel region 8, and a third insulating film 17 is formed within the interlayer insulating film 17 and on the insulating film 7. A third gate electrode 18 is formed, and a third gate electrode 18 is formed.
It is characterized in that a gate insulating film 19 is formed on the upper part, and a channel region 8 is provided on the gate insulating film M19.

In the stacked structure CMOS inverter according to this embodiment, each channel region of an N-channel transistor and a P-channel transistor has two gate electrodes 2 and 18 in the channel region 4, and two gate electrodes I#l18 in the channel region 8. It is sandwiched between 12. Therefore, the electric field of one gate electrode affects the potential of the other interface, improving the controllability of the amount of inverted carriers. Further, since both gate electrodes mutually enhance their effects and relax the vertical electric field of the inversion channel, carrier mobility does not decrease.

Stacked structure CMOS according to the third embodiment of the present invention
A method for manufacturing an inverter will be explained using FIG. 5.

By thermally oxidizing the upper surface of the silicon substrate 100, oxidized H
(S i02 ) 101 is formed to form the insulating substrate 1 (FIG. 3(a)).

Next, a portion of the oxide #101 is etched to form a gate formation region 110 for an N-channel transistor. (Figure (b)).

Next, the upper surface of the oxide film 101 and the gate formation area 110
Polycrystalline silicon 2' is deposited on the surface ((C) of the same figure).

Next, the polycrystalline silicon 2' is polished to the surface of the oxide film 101 to form a polycrystalline silicon gate electrode 2 buried in the gate formation region 110 (FIG. 4(d)).

Next, the gate insulating film 3 is formed by thermally oxidizing the surface of the gate electrode 2 (FIG. 2(e)).

Next, polycrystalline silicon 112 is deposited on the upper surface of the insulating substrate l. Next, an active region is defined in this polycrystalline silicon 112 using a lithography method (FIG. 4(f)).

Subsequently, the surface of the polycrystalline silicon 112 is subjected to heat treatment to form a gate insulator M7 (FIG. 3(g)).

Next, polycrystalline silicon 113 is deposited on the entire surface (see figure (
h)).

Next, the polycrystalline silicon 113 is defined as a gate 5its by lithography, and using this as a mask, As ions are implanted to form a source region 5 and a drain region 6 in the polycrystalline silicon 112.

A channel region #i4 is formed directly under the gate electrode ((i) in the same figure).

Next, a silicon oxide film is deposited over the entire surface by chemical vapor deposition (CVD) to form an interlayer insulating film 17 (FIG. 6(j)).

Next, the surface of the substrate is polished and planarized to expose the polysilicon gate electrode 18 (FIG. 4(k)).

Next, the surface of the gate electrode 18 is thermally oxidized, and the gate insulating film 1 is
9 (see figure (I)) Next, polycrystalline silicon 114 is deposited on the entire surface (see figure (m)
)).

Next, from polycrystalline silicon 114 using a lithography method,
A P-channel semiconductor layer 8' is formed ((n) in the same figure).

Next, a gate insulating film 11 is formed on the surface of the P-channel semiconductor layer 8' by thermal oxidation ((O) in the same figure).

Next, polycrystalline silicon 12' is deposited on the upper surface of the insulating substrate (FIG. <p)).

Next, a gate electrode 12 for a P-channel transistor is formed on the polycrystalline silicon 12' using a phosphorography method. Next, by ion-implanting boron (B) from above the insulating substrate 1 using the gate electrode 12 as a mask, a channel region 8, a source region 9 for a P-channel transistor, and a drain region 10 are formed in the semiconductor layer 8' for a P-channel. form ((q) in the same figure).

Next, after performing heat treatment and depositing glabellar insulation WA13,
A contact hole is opened, a source electrode 14 of an N-channel transistor and a source electrode 15 of a P-channel transistor are formed in each contact hole, and a drain electrode 16 common to the P-channel transistor and the N-channel transistor is formed. The manufacturing process of the device is completed ((r) in the same figure).

In the above embodiment, the channel region 4 and the P-channel semiconductor layer 8' are made of polycrystalline silicon, and the crystal grains are expanded by thermal annealing. Melting-recrystallization may be performed using an energy beam such as a laser.

As described above, if the method for manufacturing a semiconductor device according to this embodiment is used, a CM with a small element area and a large driving force can be used.
A semiconductor device having an OS inverter can be manufactured.

Stacked structure CMOS according to the fourth embodiment of the present invention
The inverter will be explained using FIG.

In this embodiment, in the semiconductor device described in the second embodiment, a third gate electrode 18 is formed between the insulating film 7 and the channel region 8, and the third gate electrode 18 and the channel region 8 are insulated. The present invention is characterized in that an insulating film 19 is formed.

In this embodiment as well, the stacked structure CMOS inverter has channel regions of each of the N-channel transistor and P-channel transistor, or the channel region 4 has two gate electrodes 2 and 18, and the channel region 8 has two gate electrodes 18 and 12. It is sandwiched between. Therefore, the electric field of one gate electrode affects the potential of the other interface, improving the controllability of the amount of inverted carriers. Further, since both gate electrodes mutually enhance their effects and relax the vertical electric field of the inversion channel, carrier mobility does not decrease. This effect is similar to the effect expected from a thin film SOI-MOSFET or an insulated gate static induction transistor (SIT).

Stacked structure CMOS according to the fifth embodiment of the present invention
A method for manufacturing an inverter will be explained using FIG. 7.

By ion-implanting oxygen into the silicon substrate 100, an oxidized flJ (S i O□) 101 is formed, and an oxidized M
A silicon single crystal layer 102 is formed on 2O3 to form a silicon-on-insulator (Sol) substrate 1 (
Same figure (a>).

Silicon single crystal layer 1 is formed by phosphorography and etching.
02 into two separated silicon single crystal regions 115.1
16 (FIG. 1(b)).

Next, a thermal oxide film 22 having a thickness of, for example, 50 nm is formed on the surface of the silicon single crystal regions 115 and 116 (see FIG.
)).

Next, a polycrystalline silicon film 23 with a film thickness of, for example, 2 μm is formed on the upper surface of the substrate 1, and a carbon film with a film thickness of, for example, 1 μm is formed on top of the polycrystalline silicon film 23.
VD-silicon oxide WA24 is formed. A polycrystalline silicon film 25 having a thickness of, for example, 1 μm is formed on the CVD-silicon oxide WA 24, and a polycrystalline silicon film 25 having a thickness of, for example, 1 μm is formed on the top of the CVD-silicon oxide WA24.
A CVD-silicon oxide film 26 of m thickness is deposited (see (d) in the same figure).
)).

Next, by phosphorography and etching, the CVD-silicon oxide film 26, polycrystalline silicon film 25, CVD-silicon oxide film 24, and polycrystalline silicon film 23 are sequentially patterned so as to stand vertically to the substrate, and the gate electrode is 23
', CVD-silicon oxidation! l! 24', a polycrystalline silicon layer 25', and a CVD-silicon oxide film 26' are formed (FIG. 2(e)).

Next, a gate insulating film 27 having a thickness of, for example, 15 nm is formed on the surface of the patterned gate electrode 23' by thermal oxidation (FIG. 2(f)).

Next, silicon single crystal regions 115 are etched by anisotropic etching.
Remove the thermally oxidized WA22 on the top surface of 116 ((g) in the same figure)
.

Next, silicon single crystal regions 115 and 116 are epitaxially grown using a selective epitaxial growth method.

Epitaxial growth is performed until the silicon 28 to be grown reaches a position between the upper part of the gate electrode 23' and the polycrystalline silicon layer 25'.

(Figure (h)).

Next, by isotropic etching, the polycrystalline silicon that was formed at the same time as the gate insulating film 27 was formed! g! 25' and 2
The oxide film on the surface of 6' is removed ((i) in the same figure).

Thereafter, selective epitaxial growth of silicon 28 is continued. At this time, crystal growth also occurs from the polycrystalline silicon film 25' from which the surface oxide film has been removed, although it is not a single crystal, and comes into contact with the silicon 28 growing from below.

The epitaxial growth is terminated so that the top surface of the crystal growth does not exceed the top surface of the CVD-silicon oxide film 26' (FIG. 6(j)).

Next, apply CVD-silicon oxide WA29 to the entire surface, e.g.
The film is deposited to a thickness of 0 nm ((k) in the same figure).

Next, by subjecting the CVD silicon oxide film 29 to anisotropic etching, only the side walls of the polycrystalline silicon film 26' and silicon 28 are etched with CVD silicon oxide WA291.2.
92 remains ((1) in the same figure).

Of the remaining CVD-silicon oxide films 291 and 292, CVD-silicon oxide II! Only 292 is selectively removed by phosphorography (Figure <m)).

Next, the silicon 28 is anisotropically etched using the CVD silicon oxide H26' and 291 as a mask, and the insulating layer 101 is etched.
Etching is finished before reaching the target ((n) in the same figure).
).

Next, the surface of the silicon layer is thermally oxidized to form a second gate insulator W! with a thickness of 15 nm. A30 is formed ((Q) in the same figure).

Next, a polycrystalline silicon 31 having a thickness of 20 nm, for example, is deposited on the entire surface (FIG. 3(p)).

In anisotropic etching, polycrystalline silicon 31 is
The second gate electrodes 311 and 312 are left on the side walls of the gate insulating film 30 (FIG. 3(q)).

Boron (
B) at 40keV, 2×10′! By performing ion implantation under the condition of 'Cm-2, a source region 321 and a drain region 322 of a P-channel transistor are formed (FIG. 3(r)).

Next, arsenic (As) was applied to the rising silicon layer 28 at 70 keV from an oblique direction opposite to the P channel formation region.
A source region 331 and a drain region 332 of an n-channel transistor are formed by ion implantation under the condition of X 101'cm-''.

In this state, a heat treatment is performed to activate the implanted impurity and recover the crystal ((S) in the same figure). Next, a phosphorus glass (PSG) film is deposited to insulate the interlayer I! ! After forming the electrodes 34, @poles 35 to 37 are wired, and a stacked structure semiconductor device is completed (FIG. 3(t)).

[Advantageous Effect 1] As described above, according to the present invention, the CMOS inverter has a stacked structure, and it is possible to improve the performance of the element while reducing the occupied area, contributing to the improvement of the degree of integration and performance of the integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a star-act structure CMOS inverter according to a first embodiment of the present invention, FIG. 2 is a diagram showing a star-act structure CMOS inverter according to a second embodiment of the present invention, and FIG. is the stacked structure C according to the first embodiment of the present invention.
4 is a diagram showing a stacked structure CMOS inverter according to a third embodiment of the present invention. FIG. 5 is a diagram showing a stacked structure CMOS inverter according to a third embodiment of the present invention.
6 is a diagram showing a stacked structure CMOS inverter according to a fourth embodiment of the present invention, and FIG. 7 is a diagram showing a stacked structure CMOS inverter according to a fifth embodiment of the present invention. FIG. 8, which is a process diagram of an inverter manufacturing method, is a diagram showing a proposed stacked structure CMOS inverter. In the figure, 1...substrate 2...gate electrode 2'...polycrystalline silicon 3...gate insulating film 4...channel region 5...n-type source region 6...n-type Drain region 7...Insulating film 8...Channel region 8'...P channel semiconductor layer 9...P type source region 10...P type drain region 11...Gate insulating film 12... Gate electrode 12'... Polycrystalline silicon 13... Interlayer insulating film 14... Source electrode 15 of N-channel transistor.
... P-channel transistor source electrode 16 ... common drain electrode 17 ... interlayer insulating film 18 ... gate as pole 19 ... - gate insulating film 22 ... thermal oxide film 23 ... polycrystalline silicon Film 24...CVD-silicon oxide film 25...Polycrystalline silicon film 26...CVD-silicon oxide film 23'...Gate electrode 24'...CVD-silicon oxide film 25'...Polycrystalline silicon film 26...CVD-silicon oxide film 23'... Crystalline silicon layer 26'...CVD-silicon oxide film 27...gate insulating film 28...silicon 29...CVD-silicon oxide film 291...CVD-silicon oxide film 292...CVD-silicon Oxide film 30...Second gate insulating film 31...Polycrystalline silicon 311...Second gate electrode 312...Second gate electrode 321...P-type source region 322...P Type drain region 331...N type source region 332...N type drain region 34...Interlayer insulating film~37...Electrode 0...Silicon substrate 1...Oxide film (SiO2) 2...・Silicon single crystal layer 0... Gate formation region 2... Polycrystalline silicon 3... Polycrystalline silicon 4... Polycrystalline silicon 5... Silicon single crystal region 6... Silicon single crystal region 1...Semiconductor substrate 2...Common gate electrode

Claims (1)

[Claims] 1. A first insulating film formed on the upper surface of a semiconductor substrate; a first gate electrode formed embedded in the first insulating film; and on the first gate electrode. a first gate insulating film formed; a first channel region of intrinsic or one conductivity type formed on the first gate insulating film; and a first channel region of opposite conductivity type formed on both sides of the first channel region. a first source region and a drain region of the type, a second insulating film formed on the top surface of the first channel region, source region and drain region, and an intrinsic or opposite conductivity type on the second insulating film. second source and drain regions of one conductivity type formed on both sides of the second channel region; a second gate insulating film formed on the second channel region; and the second gate insulating film. A semiconductor device characterized by having a second gate electrode formed on the top of the film. 2. A first insulating film formed on an insulating substrate substantially perpendicular to the insulating substrate, and a true or one conductivity type first channel region formed on one side of the first insulating film. a first source region of opposite conductivity type formed on the insulating substrate in contact with the first channel region; and a first drain of opposite conductivity type formed above the first channel region. a first gate insulating film formed on the surface of the first channel region; a first gate electrode formed on the surface of the first gate insulating film; a second channel region of a true or opposite conductivity type formed on the other side surface; a second source region of one conductivity type formed on the insulating substrate in contact with the second channel region; a second drain region of one conductivity type formed above the second channel region; a second gate insulating film formed on the surface of the second channel region; and the second gate insulating film. A semiconductor device comprising: a second gate electrode formed on a surface of the semiconductor device; 3. The semiconductor device according to claim 1, further comprising: a third gate electrode provided on the second insulating film; and a third gate electrode provided between the third gate electrode and the second channel region. 1. A semiconductor device comprising: an insulating film. 4. The semiconductor device according to claim 2, further comprising: a third gate electrode provided on a side surface of the first insulating film; and a third gate electrode provided between the third gate electrode and the second channel region. 3. A semiconductor device characterized by having an insulating film of No. 3. 5. Forming a first gate electrode standing almost perpendicularly to the first semiconductor layer on the insulating substrate, and forming a second semiconductor layer on both sides of the first gate electrode with a first gate insulating film interposed therebetween. forming a second gate insulating film on the surfaces of the first and second semiconductor layers, and forming the second gate insulating film on the second semiconductor layer on both sides of the first gate electrode. A second gate electrode and a third gate electrode are respectively formed through the second semiconductor layer, and ions are implanted from an oblique direction on one side of the rising second semiconductor layer using the second gate electrode as a mask. a source region of one conductivity type is formed in one semiconductor layer, a drain region of one conductivity type is formed on one side of a second semiconductor layer, and an oblique direction of the other side of the second semiconductor layer is formed. A semiconductor device characterized by performing ion implantation to form a source region of a reverse conductivity type in a first semiconductor layer and a drain region of a reverse conductivity type on the other side of a second semiconductor layer. Production method.