JPH11168211A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a structure which provides the same performance as that of a complete depletion-type SOI-MOS transistor and can suppress a self heating effect, which is the issue of the SOI-MOS transistor. SOLUTION: A semiconductor device consists of a first impurity diffused layer 12a formed along the direction of film thickness of a semiconductor substrate 10 from the surface of the semiconductor substrate 10 and a second impurity diffused layer 12b, which is continued with the end part of the layer 12a and is formed along the direction parallel to the main surface of the substrate 10, and the device has a trench 16 formed along the direction of film thickness of the substrate 10 in a state that the trench 16 comes into contact with an L-shaped impurity diffused layer constituting a drain region 12, the layer 12b and the end part of a source region 14. A channel region 18 is encircled with a gate insulating film 20, the regions 14 and 12 and the trench 16. The layer 12b and the trench 16 function as a depletion layer stopper in the region 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device in which a channel region can be completely depleted.

[0002]

BACKGROUND ART FIG. 10 shows an SOI (Silicon On).
2 shows an example of the structure of an Insulator (MOS) type MOS transistor. In this SOI-MOS transistor, an insulating layer 2 made of a silicon oxide film is formed on a silicon substrate 1, and a single crystal silicon layer 8 is stacked on the insulating layer 2. The source region 3, the channel region 7, and the drain region 4 are formed in the single crystal silicon layer 8. A gate electrode 6 made of doped polysilicon is formed on the surface of the channel region 7 with a gate insulating film 5 interposed.

[0003] SOI-MOS transistors are classified into a fully depleted type in which the channel region 7 is completely depleted and a partial depletion type in which the channel region 7 is not completely depleted. An SOI-MOS transistor can have a channel region with a reduced thickness, and a fully depleted SOI-MOS transistor by optimizing its thickness and impurity concentration.
A transistor can be obtained. A fully depleted MOS transistor has excellent characteristics such as a smaller sub-threshold coefficient and a smaller temperature fluctuation of a threshold voltage than a partially depleted MOS transistor.

[0004] Due to such excellent characteristics, a fully depleted SOI-MOS transistor is a next-generation high-speed
Attention has been paid to devices that carry SI or environment-resistant LSI.

[0005]

The fully depleted SOI-MOS transistor as shown in FIG. 10 has a structure in which a channel region 7 is sandwiched between a gate insulating film 5 and an insulating layer 2, and the channel region 7 7 has a small film thickness of usually about 0.1 μm, so that there is a problem that heat generated by a current flowing through the channel region 7 is not easily dissipated. That is, the thermal conductivity of the silicon oxide film forming the insulating layer 2 and the gate insulating film 5 is 0.014 at room temperature.
(W / cm ° C.), that of the silicon constituting the channel region 7 is 1.5 (W / cm ° C.), and the thermal conductivity of the silicon oxide film is considerably smaller than that of silicon. The generated heat is not easily dissipated through the silicon oxide films (2, 5), and the temperature of the channel region becomes extremely high. This phenomenon is hereinafter referred to as “self-heating effect”. Such a self-heating effect causes the following problem.

A. Reduced mobility in the channel region, b. The desired drain current cannot be obtained; c. The occurrence of negative resistance, leading to instability of circuit operation.

An object of the present invention is to provide a fully depleted SOI-MO
An object of the present invention is to provide a semiconductor device having the same performance as an S transistor and having a structure capable of suppressing a self-heating effect, which is a problem of a fully depleted SOI-MOS transistor.

[0008]

According to the present invention, there is provided a semiconductor device comprising: a first impurity diffusion layer formed from a surface of a semiconductor substrate along a film thickness direction; and an end portion of the first impurity diffusion layer. And a second impurity diffusion layer formed along the direction parallel to the main surface of the semiconductor substrate, and an L-shaped impurity diffusion layer forming a source region or a drain region. A third impurity diffusion layer which is formed on the surface portion and is spaced apart from the first impurity diffusion layer and constitutes a drain region or a source region, an end portion of the second impurity diffusion layer and an end of the third impurity diffusion layer A trench formed along the thickness direction of the semiconductor substrate in contact with
A channel region including a region surrounded by the source region, the drain region and the trench, where a channel can be formed; and a gate electrode formed on a surface of the channel region via a gate insulating film.

In this semiconductor device, the L-shaped impurity diffusion layer and the trench forming the source region or the drain region function as a stopper for the depletion layer in the channel region. By defining the impurity concentration of the channel region and the depth of the second impurity diffusion layer forming the L-shaped impurity diffusion layer, the channel region can be completely depleted.

As a result, the same operational effects as those expected from the SOI-MOS transistor, that is, operational effects such as a small subthreshold coefficient and a small temperature fluctuation of the threshold voltage can be obtained.

Further, according to the semiconductor device of the present invention, unlike the fully depleted SOI-MOS transistor, the upper and lower surfaces of the channel region are not completely sandwiched by the silicon oxide film. The heat generated in the channel region is sufficiently dissipated through the second impurity diffusion layer. Therefore, the self-heating effect does not occur, and the problems a to c described above caused by the self-heating effect do not occur.

As described above, according to the semiconductor device of the present invention, the semiconductor device has not only the same excellent characteristics as the fully depleted SOI-MOS transistor but also the problem of the self-heating effect of the SOI-MOS transistor. it can.

In the semiconductor device of the present invention, an electrode portion can be formed by burying a conductive material in the trench via an insulating film. By using the insulating film as a gate insulating film and the electrode portion as a gate electrode, a MOS transistor having a double gate structure can be formed. With such a double gate structure, the current driving capability of the transistor can be further increased.

Further, in the semiconductor device of the present invention,
An insulating film and an electrode portion may be formed in the trench, and a conductive portion connecting the electrode portion and the channel region may be formed. Since the potential of the channel region can be controlled by the conductive portion and the electrode portion, stable operation and source-drain withstand voltage can be improved.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Main embodiments of the present invention will be described below in detail.

(First Embodiment) FIG. 1 is a plan view schematically showing an n-channel MOS transistor, and FIG.
FIG. 2 is a sectional view taken along line II-II in FIG. 1.

In the semiconductor device 100 of this embodiment, an L-shaped drain region 12, source region 14, trench 16 and channel region 18 are formed in a silicon substrate 10.

The drain region 12 is formed on the silicon substrate 1
A first impurity diffusion layer 12a having a predetermined depth L formed along the thickness direction of 0, and a main surface of the silicon substrate 10 continuous with a lower end of the first impurity diffusion layer 12a. And a second impurity diffusion layer 12b formed along a direction parallel to the second direction, and has a substantially L-shaped cross section.

The source region 14 is formed of a third impurity diffusion layer formed at a predetermined distance from the first impurity diffusion layer 12a of the drain region 12.

The trench 16 is formed in the drain region 1
The second impurity diffusion layer 12 b is formed in the thickness direction of the semiconductor substrate 10 in contact with the end of the source region 14. Then, as shown in FIG. 1, the trench 16 is continuous with a region including the first drain region 12a, the channel region 18 and the source region 14 except for a side surface outside the first impurity diffusion layer 12a. 3
It is formed in a substantially U-shaped planar shape so as to surround the two side surfaces. A gate electrode 30 made of, for example, doped polysilicon is formed on the surface of the channel region 18 with a gate insulating film 20 interposed therebetween.

In the semiconductor device 100, the channel region 18 has the gate insulating film 20 and the source region 14 on the upper surface, the trench 16 on the four side surfaces, and the first impurity on the other side surface among the four side surfaces. It has a structure in which the bottom surface is surrounded by the second impurity diffusion layer 12b by the diffusion layer 12a. In this structure, the second impurity diffusion layer 12b of the drain region 12 and the trench 16 function as a stopper for a depletion layer of the channel region 18. In the channel region 18,
Along the trench 16, a p-type impurity diffusion layer 18a having a higher concentration than the impurity concentration of the channel region is formed. By providing this impurity diffusion layer 18a, it is possible to prevent a decrease in breakdown voltage due to punch-through. However, the impurity concentration of the high-concentration p-type impurity diffusion layer 18a is set to such an extent that the impurity concentration of the impurity diffusion layer 18a is not so high that the withstand voltage is reduced by hot carriers.

In the semiconductor device 100, the channel region 18 can be sufficiently or sufficiently formed by setting the impurity concentration of the channel region 18 and the depth L of the second impurity diffusion layer 12b of the drain region 12 to appropriate values. It can be completely depleted. As a result, the semiconductor device 100
Performance equivalent to fully depleted SOI-MOS transistor,
Specifically, excellent characteristics such as a small sub-threshold coefficient and a small change in threshold voltage with temperature can be obtained. Since the channel region 18 is not covered with a silicon oxide film having a low thermal conductivity around the channel region 18, especially the lower surface thereof, heat generated by the current flowing through the channel region 18 is efficiently transferred to the outside mainly through the drain region 12. It is dissipated and therefore does not cause a self-heating effect.

Next, the results of measurements performed to confirm the operation and effect of the semiconductor device 100 according to the present embodiment will be described.

(1) Sample The conditions of the sample used for the measurement are as follows.

A. Sample of this embodiment Impurity concentration of first impurity diffusion layer of drain region 1 × 10 ²⁰ cm ⁻³ Impurity concentration of second impurity diffusion layer of drain region 1 × 10 ¹⁷ cm ⁻³ Impurity concentration of source region 1 Impurity concentration of × 10 ²⁰ cm ^-3 channel region 5 × 10 ¹⁵ cm ^-3 Impurity concentration of high concentration impurity diffusion layer of channel region 5 × 10 ¹⁶ cm ^-3 Depth L 0 of second impurity diffusion layer of drain region .75 μm Thickness of gate insulating film 10 nm Gate length 1 μm Gate width 10 μm b. Sample of SOI-MOS transistor for comparison shown in FIG. 10 Impurity concentration of source region and drain region 2 × 10 ¹⁷ cm ⁻³ Impurity concentration of channel region 1 × 10 ¹⁶ cm ⁻³ Source region, drain region and channel region are formed Thickness of single-crystal silicon layer to be formed 0.1 μm Thickness of insulating layer composed of silicon oxide film 0.3 μm Thickness of gate insulating film 10 nm Gate length 1 μm Gate width 10 μm (2) Measurement items a. VDS-ID The relationship between the drain voltage (VDS) and the drain current (ID) was determined, and the results are shown in FIG. In FIG. 3, a curve indicated by a symbol a is for the sample of the present embodiment, and a curve indicated by b is a sample for comparison.

FIG. 3 shows that in the fully-depleted SOI-MOS transistor used as a comparative sample, the drain current is reduced due to the negative drain resistance due to the self-heating effect. You can see that it can not be done.

B. VGS-ID The relationship between the gate voltage (VGS) and the drain current (ID) was determined, and the results are shown in FIG. In FIG. 4, the curve indicated by the symbol a is for the sample of the present embodiment, and the curve indicated by the symbol b is for the sample for comparison. The sub-threshold coefficient can be obtained from the slope of the straight line portion of the curves a and b in FIG.

As a result, in the sample of the present embodiment, the subthreshold coefficient S is 64 (mV-dec), and the subthreshold coefficient S of the fully depleted SOI-MOS transistor is 67 (mV-dec). Do you get it. As described above, it was confirmed that the sample of this embodiment has substantially the same subthreshold coefficient as that of the fully depleted SOI-MOS transistor.

C. Temperature fluctuation of threshold voltage The relationship between temperature and threshold voltage was determined, and the results are shown in FIG. In FIG. 5, a line indicated by a symbol a is a sample according to the present embodiment, and a line indicated by a symbol b is a sample for comparison. The temperature change rate can be obtained from the slope of each line.

In the sample of the present embodiment, the rate of change is-
It was 1.20 (mV / ° C.), and it was confirmed that the rate of change was −1.25 (mV / ° C.) in the comparative sample.
From this, it can be seen that the sample of this embodiment has a threshold voltage temperature variation about the same as that of a fully depleted SOI-MOS transistor.

From the above measurement results, it is clear that the semiconductor device of the present invention secures a small sub-threshold coefficient and a small threshold voltage temperature fluctuation similar to those of a fully depleted SOI-MOS transistor, and has a self-heating effect. Was confirmed to be able to be reliably suppressed.

Next, the semiconductor device 10 according to the present embodiment
0 will be described with reference to FIGS. 6 and 7.

(A) First, arsenic is ion-implanted into a predetermined region of the first silicon substrate 10a to form a second impurity diffusion layer 12b constituting a drain region.

(B) A second silicon substrate 10b made of single crystal silicon is formed by epitaxial growth. The thickness of second silicon substrate 10b is set to the depth of second impurity diffusion layer 12b.

(C) A trench 16 is formed in a predetermined region by reactive ion etching or the like. This trench 16
Are formed so as to be in contact with at least the end of the second impurity diffusion layer 12b and to partition three side surfaces of a region constituting a channel region, a source region and a drain region.

(D) A gate insulating film (silicon oxide film) and a doped polysilicon layer are formed by a commonly used method, and patterned by reactive ion etching or the like to form a gate insulating film 20 and a gate electrode 30. I do.

(E) Boron is ion-implanted into the channel region near the trench 16 to form the high-concentration impurity layer 1.
8a is formed.

(F) The first impurity diffusion layer 12 in the drain region 12 is implanted by ion-implanting arsenic into a predetermined region.
a and a source region (third impurity diffusion layer) 14 are formed. In the arsenic ion implantation, the first impurity diffusion layer 12a and the source region 14 have different depths.
In the formation of the impurity diffusion layer 12a, the acceleration energy is increased (for example, 500 to 600 KeV) and the source region 14 is formed.
Is formed by lowering the acceleration energy (for example, 100K
eV).

The above steps (B) and (C) are performed in the second
It is preferable that the heat treatment is performed at a temperature low enough to prevent the impurities of the impurity diffusion layer from diffusing from the predetermined region by the heat treatment, for example, at a temperature of 850 to 900 ° C. Further, the concentration of the second impurity diffusion layer formed in the step (A) may be such that the impurities in the second impurity diffusion layer diffuse to the channel region in a later step, for example, a heat treatment step for a gate insulating film or the like. In order to avoid the problem, it is desirable that the impurity concentration of the second impurity diffusion layer 12b be set lower than the impurity concentration of the first impurity diffusion region 12a.

(Second Embodiment) FIG. 8 is a sectional view schematically showing a semiconductor device 200 according to a second embodiment. The semiconductor device 200 has the basic configuration described in the first embodiment.
Therefore, members having substantially the same function are denoted by the same reference numerals,
A detailed description thereof will be omitted.

The semiconductor device 200 is the same as the semiconductor device 100
The difference is that an electrode portion 42 is formed by forming an insulating film (silicon oxide film) 40 in the trench 16 and further burying a conductive material such as doped polysilicon inside the insulating film 40. On the point. And
By configuring the insulating film 40 as a gate insulating film, a double gate structure can be formed. With this double gate structure, in addition to the functions and effects of the first embodiment, the current drive capability of the element is further increased, and the circuit operation speed can be increased.

The conductive portion 42 can be formed by depositing polysilicon and doping impurities in the step of forming the gate electrode 30.

(Third Embodiment) FIG. 9 is a sectional view schematically showing a semiconductor device 300 according to the third embodiment. The semiconductor device 300 has the basic configuration described in the first embodiment.
Therefore, members having substantially the same function are denoted by the same reference numerals, and detailed description thereof will be omitted.

The semiconductor device 300 corresponds to the semiconductor device 1
The difference from the second embodiment is that the insulating film 40 and the electrode portion 42 are formed in the trench 16 and the electrode portion 42 and the channel region 18 are electrically connected to each other, as in the second embodiment. That is, the conductive portion 44 is provided.

According to the semiconductor device 300, the first
In addition to the functions and effects of the embodiment, the electrode portion 42 can function as a control electrode for controlling the potential of the channel region 18. Thus, the potential of the channel region 18 can be controlled, so that stable operation and improvement in the source-drain withstand voltage can be achieved.

The conductive portion 42 can be formed by depositing polysilicon and doping impurities in the step of forming the gate electrode 30. The conductive portion 44 can be formed, for example, by the following method. That is, the insulating film 40 and the polysilicon layer are formed in the trench 16, and then a part of the insulating film 40 and the polysilicon layer on the channel region 18 side is made deeper than the source region 14 and the second region of the drain region 12 is formed. Is etched to a depth that does not reach the impurity diffusion layer 12b. Thereafter, polysilicon is deposited in the trench to a depth not to be shallower than the source region 14, and impurities are doped into the polysilicon layer and the polysilicon layer formed in the insulating film 40, thereby forming a conductive layer. The part 44 and the electrode part 42 can be formed.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments.
Various modifications are possible. For example, in the above-described embodiment, the L-shaped impurity diffusion layer is used as the drain region. However, this can be used as the source region, and the third impurity diffusion layer can be used as the drain region. However,
In the third embodiment, since the source region 14 and the electrode portion 42 are short-circuited, using an L-shaped impurity diffusion layer as a drain region is structurally simple. Also,
The semiconductor device of the present invention can of course be applied to a p-channel MOS transistor.

[0048]

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device 100 according to a first embodiment.

FIG. 2 is a sectional view taken along line II-II in FIG.

FIG. 3 is a diagram showing a relationship between a drain voltage and a drain current of a sample element.

FIG. 4 is a diagram showing a relationship between a gate voltage and a drain current of a sample element.

FIG. 5 is a diagram illustrating a relationship between a temperature of a sample element and a threshold voltage.

FIGS. 6A to 6C are cross-sectional views illustrating manufacturing steps of the semiconductor device according to the first embodiment.

7 (D) to 7 (F) are cross-sectional views showing manufacturing steps performed subsequent to the step shown in FIG.

FIG. 8 is a sectional view showing a semiconductor device 200 according to a second embodiment.

FIG. 9 is a sectional view showing a semiconductor device according to a third embodiment.

FIG. 10 is a cross-sectional view illustrating an SOI-MOS transistor.

[Explanation of symbols]

 Reference Signs List 10 silicon substrate 12 drain region 12a first impurity diffusion layer 12b second impurity diffusion layer 14 source region 16 trench 18 channel region 20 gate insulating film 30 gate electrode 40 insulating film 42 electrode portion 44 conductive portion

Claims (3)

[Claims] A first impurity diffusion layer formed from the surface of the semiconductor substrate along the thickness direction thereof, and continuous with an end of the first impurity diffusion layer and parallel to a main surface of the semiconductor substrate. An L-shaped impurity diffusion layer which comprises a second impurity diffusion layer formed along an arbitrary direction and constitutes a source region or a drain region, and is separated from the first impurity diffusion layer on a surface portion of the semiconductor substrate. A third impurity diffusion layer forming a drain region or a source region, and contacting an end of the second impurity diffusion layer and the third impurity diffusion layer in a thickness direction of the semiconductor substrate. A channel region including a region surrounded by the source region, the drain region, and the trench, where a channel can be formed, and a gate insulating film on a surface of the channel region. A semiconductor device including a gate electrode formed through the gate electrode. 2. A semiconductor device comprising: a first impurity diffusion layer formed from a surface of a semiconductor substrate along a film thickness direction thereof; an end portion of the first impurity diffusion layer continuous with a main surface of the semiconductor substrate; An L-shaped impurity diffusion layer which comprises a second impurity diffusion layer formed along an arbitrary direction and constitutes a source region or a drain region, and is separated from the first impurity diffusion layer on a surface portion of the semiconductor substrate. A third impurity diffusion layer forming a drain region or a source region, and contacting an end of the second impurity diffusion layer and the third impurity diffusion layer in a thickness direction of the semiconductor substrate. An electrode portion formed in a trench formed along with an insulating film, a channel region including a region in which a channel can be formed and surrounded by the source region, the drain region, and the trench; A gate electrode formed on the surface of the channel region via a gate insulating film. 3. A first impurity diffusion layer formed from the surface of the semiconductor substrate along the thickness direction thereof, and continuous with an end of the first impurity diffusion layer and parallel to a main surface of the semiconductor substrate. An L-shaped impurity diffusion layer which comprises a second impurity diffusion layer formed along an arbitrary direction and constitutes a source region or a drain region, and is separated from the first impurity diffusion layer on a surface portion of the semiconductor substrate. A third impurity diffusion layer forming a drain region or a source region, the second impurity diffusion layer and an end of the third impurity diffusion layer being in contact with an end of the semiconductor substrate in a film thickness direction. An electrode portion formed in the trench formed along with an insulating film, a channel region including a region where a channel can be formed and surrounded by the source region, the drain region, and the trench; An opening formed in a part of the insulating film in the trench is formed by embedding a conductive material, a conductive portion connecting the channel region and the electrode portion, and a surface of the channel region via a gate insulating film. A semiconductor device including the formed gate electrode.