JP3003633B2 - Field effect transistor and method for manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a method of manufacturing the same, and more particularly, to an improvement in subthreshold characteristics.
The present invention relates to a field effect transistor capable of suppressing a short channel effect and improving an on-current, and a method for manufacturing the same.

[0002]

2. Description of the Related Art By using materials having different work functions for a central portion and both end portions of a gate electrode, respectively,
A field effect transistor which forms a large potential barrier in a channel region adjacent to a source / drain region and suppresses a short channel effect is described in JP-A-6-232389. FIG. 21 shows the structure of this transistor.

Referring to FIG. 21, a silicon substrate 101 is provided.
A gate electrode 105 is formed thereon with a gate oxide film 102 interposed therebetween.
^{A +} type source / drain region 104 is formed. On the silicon substrate 101 on both sides of the gate electrode, an n ⁺ -type source / drain diffusion layer 104 is formed, a central portion of the gate electrode is made of n ⁺ -type polysilicon 105, and a tungsten silicide 107 is stacked on the upper portion thereof. , N ⁺ type polysilicon 105 and tungsten silicide 107 are in contact with p ⁺ type polysilicon 106.

In this conventional example, p ⁺ polysilicon 106 at both ends is formed above a first conductivity type diffusion layer forming a source / drain or a lightly doped first conductivity type region forming an LDD (Lightly Doped Drain). Rather, it is characterized in that it is located above the channel forming region which is located inside.

In this conventional example, the material constituting the gate is not limited to this. In the case of an n-channel transistor, a material having a larger work function than the central portion of the gate is provided on the side wall. It is stated that a material having a smaller work function than the central part of the gate should be selected.

[0006] Since the conductivity type of the channel is the same as the conductivity type of the source / drain regions, when an n-type source / drain region is provided, a material having a larger work function than the gate central portion is used for the side wall. , And p-type source / drain regions. This configuration is intended to increase a potential barrier to carriers forming a channel in a portion of the channel region near the source / drain region.

Although the purpose of the present invention is different from that of the present invention, in order to improve the breakdown voltage of a fine MOS transistor, in an n-channel transistor, the center of the gate is n ⁺ -type polysilicon, and both ends are p ⁺ -type. A structure using polysilicon is disclosed in JP-A-59-134879. This structure is shown in FIG.

In FIG. 22, a gate oxide film 102 is formed on a silicon substrate 101, and n ⁺ type source / drain diffusion layers 1 are formed on the silicon substrate on both sides of the gate electrode.
04 is formed, and the center of the gate electrode is made of n ⁺ polysilicon 105, and both ends are made of p ⁺ polysilicon 106.

In a field effect transistor, a gate voltage (threshold voltage) for conducting the transistor becomes lower than an originally set value with miniaturization. This effect is called the short channel effect. This is because the potential barrier (a barrier that hinders the flow of the charge carriers forming the channel) becomes smaller than the original state due to the effect of the electric field from the drain region becoming stronger as the element becomes finer. It is.

In the prior art shown in FIG. 21, when materials having different work functions are arranged at both ends of the gate as described above, the electric field from the side walls having different work functions firmly strengthens the channel region near the source / drain. It employs the principle that a high potential barrier is formed and, as a result, the short channel effect is suppressed.

[0011]

In the structure shown in FIG. 21, the short channel effect (decrease in threshold voltage due to miniaturization) is suppressed by strengthening the potential barrier at the source end. It has the following issues. Since these occur on the same principle for both n-channel and p-channel,
Hereinafter, it is represented by an n-channel transistor.

A first problem relates to a degree of freedom in setting a threshold voltage. In the conventional example shown in FIG. 21, the gate voltage (threshold voltage) at which the transistor starts conducting is governed by the potential barrier formed by the electric field from the side wall. Since the magnitude of the potential barrier formed by the electric field from the side wall is determined by the work function of the side wall, the threshold voltage is eventually governed by the work function of the side wall. Therefore, if the material of the side wall is determined, its work function is also determined, so that the threshold voltage cannot be set freely.

Although a p-type semiconductor, metal, or metal silicide is used for the side wall, these materials generally have a problem that the threshold voltage becomes too high. Although the threshold voltage affects the operation speed and the leakage current, if the work function of the side wall strongly controls the threshold voltage, the value of the threshold voltage is set to a value that is optimal in circuit operation. It becomes difficult.

[0014] The second problem is that the sub-threshold characteristic is degraded due to the current flowing at a position distant from the semiconductor surface. When the impurity concentration of the channel formation region is low,
In a state where a gate voltage lower than the threshold voltage is applied (sub-threshold region), the potential of the side wall portion becomes lower than that of the semiconductor layer, and as shown in FIG.
A potential barrier 110a (a barrier having a lower potential than other regions and alienating the flow of electrons) 110a formed by the gate electrode 06 extends downward from the gate side.

Then, the current flows at a position away from the surface of the semiconductor while avoiding the potential barrier (a buried channel is formed). When the current flows at a position distant from the gate electrode, the ability to control the current by the gate electrode (controllability by the gate electrode) deteriorates, and as a result, the sharpness of the sub-threshold region is lost.

The third problem is that the subthreshold characteristic is deteriorated due to the formation of the potential barrier near the source. As shown in FIG. 23, when the potential barrier 110b is formed below the side wall of the source end, the potential barrier is formed closer to the source than when there is no side wall. Then, the electrostatic coupling (indicated by 109) between the potential barrier portion and the source electrode becomes stronger, and as a result, the controllability of the current by the gate electrode deteriorates.

The effects of the second and third problems will be described more specifically. In a field-effect transistor, when the gate voltage is reduced to a value lower than the threshold voltage, the drain current decreases exponentially with a change in the gate voltage. The logarithm of the drain current is plotted on the ordinate and the gate voltage is plotted on the abscissa, and a graph of this region (sub-threshold region) is obtained. As shown in FIG. 24, a linear relationship is obtained. Called the factor. In order to reduce the leakage current in the off state, it is required that the slope of the straight line is large (the sub-threshold characteristic is steep). That is, a small S factor is required.

The magnitude of the current in the sub-threshold region is governed by the potential at the position where the potential barrier is greatest in the current path (hereinafter, referred to as a current regulation point and shown as 108 in FIG. 23). Therefore, if the potential of the current regulation point 108 is strongly controlled by the gate electrode,
The subthreshold current shows a steep characteristic (small S factor) with respect to the gate voltage.

To this end, it is effective to reduce the distance between the current regulating point 108 and the gate 105 and increase the electrostatic coupling between the two. In addition, if the potential at the current regulation point is strongly affected by the potential of the portion other than the gate, the controllability of the gate electrode is deteriorated due to a relative effect. Area) and the specified current point,
It is effective to reduce the electrostatic coupling between the two.

The second problem is that when the current is away from the surface, the electrostatic coupling between the gate and the specified current point is reduced, the controllability by the gate electrode is weakened, and the sharpness of the sub-threshold characteristic is obtained. It can be said that it disappears (the S factor increases).

The third problem is that since the current regulating point can be formed near the source electrode, the electrostatic coupling between the current regulating point and the source electrode increases, and as a result, the electrostatic coupling between the current regulating point and the gate electrode becomes relatively large. In other words, the controllability by the gate electrode deteriorates, and the S factor increases.

The fourth problem is that the diffusion layer is penetrated into the lower part of the side wall. In the conventional example of FIG. 21, a potential barrier is formed at an end of a channel formation region (a region sandwiched between source / drain diffusion layers) by an electric field of a side wall portion.
Suppress short channel effects. However, the length of the source / drain diffusion layer sunk under the side wall portion is not constant due to variations in the amount of ion implantation when forming the source / drain diffusion layers, variations in the heat treatment time, and the like. Then, a portion (source /
The length that does not overlap with the drain diffusion layer) changes. As a result, the effect of forming a barrier in the channel formation region by the sidewall, that is, the ability to suppress the short channel effect varies.

As described above, the structure shown in FIG.
There is a fourth problem, and a solution to at least one or more problems is needed. Accordingly, it is an object of the present invention to provide a field effect transistor which has a sharp sub-threshold characteristic, can suppress a short channel effect, and can improve an on-current, and a method for manufacturing the same.

[0024]

According to the present invention , a gate insulating film and a gate electrode are stacked on a semiconductor layer, and at least a part of a portion of the semiconductor layer facing the gate electrode becomes a channel formation region. A field effect transistor in which a source / drain region including two first conductivity type diffusion layers sandwiching a region is formed, wherein the gate electrode has a first region located at a central portion, a second region outside the first region, When the first conductivity type is n-type, the second region is made of a material having a larger work function than any of the first and third regions. When the conductivity type is p-type, a field effect transistor is obtained in which the second region is made of a material having a lower work function than any of the first and third regions.

Further, according to the present invention, the gate electrode is formed between the first region, the second region, and the third region between the pair of n-type diffusion layers and the center of the channel located at the midpoint between the pair of diffusion layers. The second region is a material having a larger work function than any of the first and third regions, and the arrangement structure is provided in at least one of the pair of diffusion layers. A characteristic field-effect transistor is obtained.

Further, according to the present invention, the gate electrode is formed between the first region, the second region, and the second region between the pair of p-type diffusion layers and the channel center located at the midpoint between the pair of diffusion layers. The second region is a material having a smaller work function than any of the first and third regions, and the array structure is provided on at least one of the pair of diffusion layers. Thus, a field effect transistor characterized by the above is obtained.

According to the present invention, a gate insulating film is formed on a semiconductor, a gate electrode made of a first material is formed thereon, and a second material is deposited on a side surface of the gate electrode. Selective anisotropic etch-back, followed by deposition of the first or third material, selective anisotropic etch-back to the gate insulating film, from center to edge To form a gate electrode consisting of three regions, and before or after forming the gate electrode,
A method of manufacturing a field-effect transistor, characterized in that the drain region is diffused.

Then, a resist pattern is provided from the center to one end of the gate electrode comprising the three regions,
It is characterized in that a selective removal process using this resist pattern is performed.

The operation of the present invention will be described. The gate electrode is provided with a triple structure including a first region forming a central portion thereof, a second region (first side wall) located outside the first region, and a third region (second side wall) outside the first region. The work function of the second region is larger in the n-channel transistor than in the first and third regions, and smaller in the p-channel transistor.

Taking an n-channel transistor as an example, the first side wall forming the second region is a region where the work function is small and the function of forming a barrier is weak (the second side wall forming the central portion of the gate and the third region). , The potential barrier from the first side wall is reduced by the influence of the electric field from the materials on both sides thereof. This becomes remarkable when the first side wall is thin.

Therefore, when the first side wall has a structure sandwiched between two materials having small work functions, the size of the potential barrier can be changed by changing the thickness of the first side wall.
If the magnitude of the potential barrier can be changed, the threshold voltage can be changed, so that the threshold can be freely controlled by changing the thickness of the first side wall. Further, it becomes easy to set the threshold voltage to a low value.

The present invention can solve the first problem (the problem that the threshold voltage cannot be freely controlled) in this way.

Since the second side wall has a smaller effect of forming a potential barrier than the first side wall, the potential barrier and the current defining point are formed below the first side wall. Therefore, as long as there is a second side wall,
The current regulation point can be separated from the source electrode. Then, the electrostatic coupling between the current regulation point and the source electrode is reduced,
The third problem (deterioration of the S factor due to the current specified point approaching the source) can be solved, and the S factor can be improved.
When the second side wall is not provided, when the first side wall is thinned, a potential barrier is formed at a position very close to the source, and the third problem becomes remarkable. However, in the present invention having the second side wall, the first side wall is thin. In this case, this problem does not occur.

Further, in the present invention having the second side wall, even if the source / drain diffusion layers may go under the second side wall to some extent due to process variations, they control the potential barrier and the threshold voltage. It is hard to go under the first side wall. Therefore, the effective length of the first side wall (the width of the region on the channel forming region) is not affected by process variations, and the fourth problem (characteristics such as a threshold value due to process variations). Can be solved.

In a transistor in which a side wall having a different work function is provided on a gate electrode and a large potential barrier is formed at the side wall, a thin SOI film of 50 nm or less is formed in a channel region.
Use layers. Since the bottom of the SOI layer is in contact with the insulating film,
No current flows to a position farther from the gate than the bottom surface of the SOI layer. That is, since the distance between the current path and the gate is limited by the thickness of the SOI layer, the second problem can be solved and the S factor can be improved to be small.

Between the n-type diffusion layer or the low-concentration n-type region connected to the n-type diffusion layer and the center of the channel, which is the midpoint between the two diffusion layers, the gate electrode is divided into the first region and the second region. , And a structure in which the second region is made of a material having a higher work function than any of the first and third regions is provided for at least one of the opposed source / drain regions.

Between the p-type diffusion layer or the low-concentration p-type region connected to the p-type diffusion layer and the center of the channel, which is the midpoint between the two diffusion layers, the gate electrode is composed of the first region and the second region. , And a structure in which the second region is made of a material having a lower work function than either of the first and third regions is provided for at least one of the opposed source / drain regions. Further, the semiconductor layer having no third region and having a thickness of 50 n
m or less.

A gate insulating film is provided on a semiconductor, a gate electrode made of a first material is formed on the gate insulating film, and a second material is deposited on the side surface of the gate electrode and anisotropy is selectively formed with respect to the gate insulating film. Etchback, followed by selective anisotropic etchback for the first or third material deposition and gate insulating film, forming a gate electrode consisting of three regions from the center to the end, A source / drain diffusion layer is formed before or after the formation of.

A gate electrode consisting of three regions is formed from the center to the end, a resist pattern is provided from the center to one end, and the second material formed at one end and the first and second materials at the outside are formed. Remove the third material area.

[0041]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention. In FIG. 1, a buried oxide film 2 is provided on a silicon substrate 1, and an SOI layer 3 (single-crystal silicon layer) is provided thereon. The SOI layer is an intrinsic semiconductor into which impurities are not introduced, or a p-type or n-type impurity of 10 ¹⁷ cm ^-3 or less. A thin gate oxide film 4 is provided on the SOI layer, and a gate electrode 5 is formed thereon.

The gate electrode is formed by combining a gate electrode central portion 6 (first region), first side walls 7 (second regions) on both sides thereof, and a second side wall 8 (third region) on the outside thereof. You. In the case of an n-channel transistor, the first side wall has a larger work function than any of the gate electrode central portion 6 and the second side wall 8. Function is small.

In the SOI layer that hits from just below the outer end of the second side wall 8 to the outside (FIG. 1), or on the outside (FIG. 2) at a certain interval below the interface between the first side wall and the second side wall. A source / drain diffusion layer 9 into which impurities are introduced at a high concentration is formed. The source / drain regions are n ⁺ type for an n-channel transistor and p ⁺ type for a p-channel transistor.

The material constituting the gate electrode may be such that the work function of the first side wall is selected to be larger than those of the central portion of the gate and the second side wall. In the case of an n-channel transistor, for example, the gate central portion and the second sidewall use n + polysilicon, and the first sidewall uses p ⁺ polysilicon or another p-type semiconductor. For the first side wall, a metal such as W or Mo, or a metal semiconductor compound such as tungsten silicide, molybdenum silicide, or cobalt silicide is used.

Further, one or both of the central portion of the gate and the second side wall is made of a metal such as W or Mo, tungsten silicide,
A metal semiconductor compound such as molybdenum silicide or cobalt silicide is used, and the first side wall is p ⁺ polysilicon.
In a p-channel transistor, these polarities are reversed.

The first and second side walls are provided only on the source electrode side (FIG. 3). Further, a transistor having the first and second side walls is formed on a normal bulk substrate. Also,
A low-concentration region 13 of the same conductivity type as the drain region is provided adjacent to the drain region. The low concentration region 13 is located outside the interface between the first side wall 7 and the second side wall 8. Further, the SOI layer is made thinner than 50 nm. Further, the SOI layer is made thinner than 50 nm, and the second side wall is not provided.

First, the gate electrode is changed from the double structure in the conventional example (a structure having a total of three portions because there are two side walls on the left and right) to the triple structure (including the first, second, and third regions). Structure: In a symmetrical configuration, there are two second and third regions, so a structure consisting of a total of five parts) will be described to solve the first, third, and fourth problems.

Taking an n-channel transistor as an example, the first side wall forming the second region is a region where the work function is small and the function of forming a barrier is weak (the second side wall forming the central portion of the gate and the third region). , The potential barrier from the first side wall is reduced by the influence of the electric field from the material on both sides thereof. This becomes remarkable when the first side wall is thin. Therefore, when the first side wall has a structure sandwiched between two materials having a small work function, the size of the potential barrier can be changed by changing the thickness of the first side wall.

When the magnitude of the potential barrier can be changed, the threshold voltage can be changed. Therefore, the threshold value can be freely controlled by changing the thickness of the first side wall. Further, it becomes easy to set the threshold voltage to a low value. The present invention can thus solve the first problem (the problem that the threshold voltage cannot be freely controlled).

Since the second side wall has a smaller effect of forming a potential barrier than the first side wall, the potential barrier and the current defining point are formed below the first side wall. Therefore, as long as there is a second side wall,
The current regulation point can be separated from the source electrode. Then, the electrostatic coupling between the current regulation point and the source electrode is reduced,
The third problem (deterioration of the S factor due to the current specified point approaching the source) can be solved, and the S factor can be improved.
When the second side wall is not provided, when the first side wall is thinned, a potential barrier is formed at a position very close to the source, and the third problem becomes remarkable. However, in the present invention having the second side wall, the first side wall is thin. In this case, this problem does not occur.

Further, in the present invention having the second side wall, even if the source / drain diffused layer may go under the second side wall to some extent due to process variation, it controls the potential barrier and the threshold voltage. It is hard to go under the first side wall. Therefore, the effective length of the first side wall (the width of the region on the channel forming region) is not affected by the process variation, and the fourth problem (the process variation)
Variations in characteristics such as threshold values) can be solved.

Next, the operation for solving the second problem will be described. When a thin SOI layer having a thickness of 50 nm or less is used for the channel region, the position where a current flows is not farther from the gate than the bottom surface of the SOI layer, so that the second problem can be solved and the S-factor can be reduced. This is because, since the buried oxide film exists under the SOI layer, even if the potential barrier extends from the gate electrode side, current cannot flow to a position farther than the bottom of the SOI layer.

According to the simulation, it is effective when the gate length is 0.15 μm, the film thickness is 50 nm or less, and when the gate length is 0.1 μm, the film thickness is 30 nm or less. This means that it is desirable that the thickness of the SOI layer be equal to or less than one third of the gate length.

Further, by making the SOI film thickness two to three times or less the thickness of the inversion layer (typically about 5 nm),
The effect becomes more remarkable. This can be explained as follows. The SOI layer has such a thickness, and the inversion layer thickness and S
When the difference from the OI layer thickness becomes small, the SO
Even when a potential distribution in which a current flows through the surface of the I layer or a potential distribution in which a current flows behind the SOI in the sub-threshold region, the position where the current actually flows hardly changes. Of the characteristics due to the flow away from the surface is very small. This effect is particularly significant when the thickness of the SOI layer is equal to or less than the thickness of the inversion layer.

If the position where the current flows in the sub-threshold region is far from the surface, the entire sub-threshold current becomes larger than the threshold voltage that determines the on-state current.
There is a phenomenon that the current shifts to the low gate voltage side and the leak current increases. This is an effect seen in the buried channel type transistor, in which the threshold voltage with respect to the on-state current is shifted from the gate voltage at which a channel starts to be formed on the back side. This is remarkable when the SOI layer is thick or the drain voltage is high. By making the SOI layer thin, in the ON state and the sub-threshold region,
This effect is also suppressed if the difference in the depth at which the current flows is reduced.

Next, another function of the present invention will be described by taking an n-channel transistor as an example. In a symmetric structure,
The work function at the center of the gate is smaller than its ends. With an asymmetric structure, the work function is small even in the region from the gate center to the drain end. In these portions where the work function is small, the potential barrier is low, so that an inversion layer is easily formed. Therefore, in these regions where the work function is small, the inversion layer charge in the channel region increases.

When the charge in the inversion layer increases, the drain current increases due to the following three effects. The first effect is that the charge itself, which is a carrier of the current, increases, so that the resistance decreases. The second is to reduce the pinch-off resistance. Generally, when a drain voltage higher than a certain voltage (pinch-off voltage) is applied to a field-effect transistor, a region (pinch-off region) where an inversion layer is not formed is formed on the drain side. The resistance is large in the pinch-off region. According to the present invention, an inversion layer is easily formed in the central portion of the gate (all regions from the center to the drain end in the case of the asymmetric structure). Therefore, it is difficult to form a pinch-off region in this region, and the width of the pinch-off region having high resistance is reduced. As it becomes smaller, the current increases.

Third is the increase in the lateral electric field. As the pinch-off resistance decreases, and as a result the ratio of pinch-off resistance to inversion layer resistance decreases, the voltage across the inversion region increases instead of decreasing the lateral voltage across the pinch-off region. As a result, the lateral electric field in the inversion region increases, and the speed of the inversion layer charge increases. Then, the overshoot at which the speed exceeds the saturation speed tends to occur. As the speed of the carrier increases, the current also increases.

Next, an example of the manufacturing method will be described.
A gate insulating film is provided on a semiconductor, a gate electrode made of a first material is formed thereon, and anisotropic etchback with selective control over the deposition of the second material and the gate insulating film on its side surface, Subsequently, selective anisotropic etch-back is performed on the first or third material and the gate insulating film, and a gate electrode including three regions is formed from the center to the end, and before the gate electrode is formed. Alternatively, a source / drain diffusion layer is formed later.

Further, a gate electrode consisting of three regions is formed from the center to the end, a resist pattern is provided from the center to one end, and the second material formed at one end and the outside are formed. The first and third material areas are removed. Thereby, a transistor having the above-described configuration can be manufactured.

[0062]

Next, embodiments of the present invention will be described in detail.

As shown in FIG. 1, the substrate 1 has a thickness of 80 nm.
m embedded oxide film 2 and a 10 nm thick SOI
Layer 3 (single-crystal silicon layer) is provided. The SOI layer is an intrinsic semiconductor into which impurities are not introduced, or the SOI layer 3
, A p-type or n-type impurity of 10 ¹⁷ cm ⁻³ or less is introduced. A gate oxide film 4 having a thickness of 5 nm is provided on the SOI layer, and a gate electrode 5 having a thickness of 100 nm is formed thereon.

Total length of gate electrode 5 (length in the horizontal direction in the figure)
Is 0.1 μm. The gate electrode 5 is configured by combining a gate electrode central portion 6, first side walls 7 on both sides thereof, and a second side wall 8 on the outside thereof. Gate electrode central part 6
Is n ⁺ polysilicon having a width (length in the horizontal direction in the figure) of 50 nm, the first side wall 7 is TiN having a width of 10 nm, and the second side wall 7 is n ⁺ polysilicon having a width of 15 nm. A source / drain diffusion layer 9 in which an n ⁺ -type impurity is introduced at a high concentration is formed in the SOI layer which is located from right under the outer end of the second side wall 8 to the outside. This transistor is an n-type field-effect transistor in which an n-type channel is formed in a channel forming region 10 sandwiched between source / drain diffusion layers 9. This is shown in FIG.

The material constituting the gate electrode may be such that the work function of the first side wall is selected to be larger than those of the central portion of the gate and the second side wall. For example, the first sidewall uses p ⁺ polysilicon or another p-type semiconductor. For the first side wall, a metal such as W or Mo, or a metal semiconductor compound such as tungsten silicide, molybdenum silicide, or cobalt silicide is used. Also in the center of the gate,
When one or both of the second side walls is made of a metal such as W or Mo, or a metal semiconductor compound such as tungsten silicide, molybdenum silicide, or cobalt silicide, the first side wall is made of p ⁺ polysilicon.

Further, the width of the second side wall in FIG.
FIG. 2 shows a structure in which a source / drain diffusion layer extends over a length of 35 nm under the width of m.

In FIG. 1, the gate electrode central portion 6 and the second side wall 7 are formed by p ⁺ polysilicon and source / drain diffusion layers 9.
Is ap ⁺ type, a p-channel transistor can be formed. FIG. 15 shows an example in which a bulk silicon substrate 1 having a boron concentration of 5 × 10 ¹⁷ cm ⁻³ is used instead of the SOI layer 3 in the structure of FIG.

[0068] In the structure of FIG. 1, a first side wall 7 of the second side wall 2, provided in the source region 11 side consisting of n ⁺ -type diffusion only, also not provided in the drain region 12 side consisting of n + -type diffusion layer, n FIG. 3 shows a structure in which the length of the central portion of the gate made of ⁺ type polysilicon is set to 75 nm.

FIG. 4 shows an example in which the structure of FIG. 1 is applied to a high breakdown voltage MOSFET. The thickness of the SOI layer 3 is 200 nm, the thickness of the gate oxide film 4 is 30 nm, the thickness of the buried oxide film 2 is 1 μm, and the width of the central part 6 of the gate electrode (length in the horizontal direction in the figure).
The first side wall 7 has a width of 300 nm, the second side wall 7 has a width of 300 nm, and has a 2 μm long n ⁻ region 13 adjacent to the drain region. The second side wall overlaps the source region and the n ⁻ region by 100 nm, respectively. FIG. 18 shows a structure in which the first and second side walls on the drain side are omitted.

FIG. 5 shows a structure in which the second side wall is not provided in the structure of FIG. 1 and the width of the first side wall is 25 nm.

The manufacturing method will be described below with reference to FIGS. In an SOI substrate having a buried oxide film 2 having a thickness of 80 nm on a substrate 1 and an SOI layer 3 (single-crystal silicon layer) having a thickness of 11 nm, the SOI has a width of 1 μm by ordinary lithography and etching by RIE.
m (horizontal direction in the drawing) to form an element region. Next, the surface is thermally oxidized to form a gate oxide film 4 having a thickness of 5 nm.

Subsequently, the polysilicon 21 is formed by the CVD method.
Was deposited to a thickness of 100 nm, and phosphorus was added thereto at 40 keV in 5 × 1
Implantation of 0 ¹⁵ cm ^-2 is performed, followed by a heat treatment at 850 degrees for 10 minutes to make the polysilicon 21 an n ⁺ type. After performing a normal photolithography or a normal electron beam exposure to form a resist pattern on the polysilicon, the polysilicon 21 is formed to a width of 100 nm by RIE (reactive ion etching) having a high selectivity to an oxide film using the resist as a mask. To obtain the shape shown in FIG. Since the SOI layer 3 is thinner than the polysilicon 21, the polysilicon attached to the side surface of the SOI layer is removed at the time of etching by RIE.

As shown in FIG. 7, 10 nm of TiN 22 is deposited on the entire surface by sputtering, and etched back by anisotropic etching by RIE to form a first side wall of TiN 22 (FIG. 8). Subsequently, 40 nm of n + type doped polysilicon 23 is deposited on the entire surface, and then etched back by anisotropic etching by RIE similarly to the first side wall, and the second side wall made of n + type doped polysilicon 23 is formed. (FIG. 9).

Next, a first oxide film 24 is deposited to a thickness of 30 nm by the CVD method, and this is etched back by anisotropic etching by RIE to form a side wall made of the first oxide film 24. At this time, the gate oxide film 4 located outside the second side wall is also removed by etching at the same time. Then, PSG (phosphorus glass) 2 is applied to the entire surface by spin coating.
5 is deposited, and phosphorus is diffused from the PSG 25 into the SOI layer by, for example, heat treatment by lamp annealing at 800 ° C. for 10 seconds.

At this time, the polysilicon 21, TiN22,
SO located below n + type doped polysilicon 23
Since these structures serve as a mask for the I layer, phosphorus is not diffused. Phosphorus is the SOI outside these structures
It is diffused into the layer, and further goes under the first oxide film 24 therefrom to form the n ⁺ -type source / drain region 9, and the shape shown in FIG. 10 is obtained.

At this time, the combination of the film thickness of the n ⁺ -type doped polysilicon 23 forming the second side wall, the film thickness of the first oxide film 24, and the heat treatment time after the deposition of the PSG 25 is not limited to this. Should be selected so as to satisfy the condition that the wraparound goes under the first oxide film 24 and does not reach the lower portion of the first side wall.

In the case where the heat treatment is performed at a low temperature or for a short time, or when the second side wall is thick, the n ⁺ -type region formed by sneaking in of phosphorus without providing the first oxide film 24 becomes the first region. The first oxide film may be omitted as long as it does not reach the lower part of the interface between the side wall and the second side wall.

Since PSG is an insulator, it may be left as it is. However, by utilizing the fact that the etching rate by HF is higher than that of a thermal oxide film, if etching by HF is performed for a short time, it is formed by thermal oxidation. Only the PSG can be removed while leaving the gate insulating film thus formed.

After the formation of the first side wall and the formation of the second side wall, or after the formation of the second side wall, a resist pattern is provided on the left side of the center of the gate. When removed by anisotropic chemical dry etching or anisotropic RIE, as shown in FIG.
An asymmetric structure is obtained.

A method of forming a CMOS will be described, and an example in which tungsten silicide is used as the first side wall will be described. In the step of forming the shape of FIG.
As shown in FIG. 1, after depositing polysilicon 21, a resist pattern is provided, and phosphorus is applied to a region for forming an n-channel transistor at an energy of 40 keV and a dose of 5 ×.
After ion implantation at 10 ¹⁵ cm ^-2 and removing the resist, a resist pattern is provided in the region implanted with phosphorus, and boron is ion implanted at an energy of 30 keV and a dose of 3 × 10 ¹⁵ cm ^-2 . Subsequently, these ions are activated by a heat treatment at 850 ° C. for 10 minutes.

Next, a second oxide film 26 having a thickness of 100 nm is deposited on the entire surface. Subsequently, a resist pattern 28 is provided only in a region where a p-channel transistor is formed, and the second oxide film 2 is formed only in a region where an n-channel transistor is formed.
6 is removed.

Thereafter, an n-channel transistor is formed in the same manner as in the method shown in FIGS. At this time, TiN may be used for the first side wall, or tungsten silicide may be used. Second oxide film 26
Is flat, the tungsten silicide used for forming the first side wall and the n ⁺ used for forming the second side wall are used.
The doped polysilicon and the first oxide film 24 are removed by etch back for forming the side wall, and only the PSG 25 remains on the second oxide film 26. Further, the phosphorus diffused from the PSG is masked by the second oxide film 26 and the polysilicon 21 and does not reach the SOI layer 3.

Subsequently, a third oxide film 27 having a thickness of 200 nm is deposited on the entire surface. On the other hand, a resist pattern is provided only on the region where an n-channel transistor is to be formed. Oxide film 27 of
The PSG 25 and the second oxide film 26 are removed by RIE or wet etching using an etchant containing HF.

Subsequently, in the same steps as in FIGS. 7 to 10, p
A channel transistor is formed. However, at this time, the second side wall is formed of p ⁺ -doped polysilicon 29, and the source / drain regions are of p + type by diffusing boron from BSG 31 (boron glass). The first side wall is made of tungsten silicide. SO
Channel doping for the I layer is not performed for any channel type. Thus, as shown in FIG. 12, both n-channel and p-channel transistors are formed.

At this time, the surface of the third oxide film 27 is relatively flat, so that the tungsten silicide used for forming the first side wall and the second side wall are formed as in the case of forming the n-channel transistor. The p ⁺ -doped polysilicon and the first oxide film 24 are removed by etch-back for forming a side wall, and only the BSG 31 is removed from the second oxide film 2.
Remain on 6. The boron diffused from the BSG is masked by the third oxide film 27 and the polysilicon 21, and
It does not reach the I layer 3.

Next, another manufacturing method will be described. A buried oxide film 2 having a thickness of 80 nm on a substrate 1 and a thickness of 11 n
In an SOI substrate having an SOI layer 3 (single-crystal silicon layer) of m m, the SOI is patterned to a width of 1 μm by ordinary lithography and etching by RIE to form an element region. Next, a dummy oxide film 40 is formed on the
Then, the film is deposited to a thickness of 200 nm and patterned to a width of 200 nm (FIG. 13) . After removing the resist, a silicon layer 41 containing a high concentration of phosphorus is selectively epitaxially grown. Subsequently, phosphorus is diffused from the silicon layer 41 by, for example, a heat treatment at 850 ° C. for 10 seconds to form an n ⁺ -type source / drain 42. To form

After removing the dummy oxide film 40 by wet etching , a spacer oxide film 43 is
Then, the silicon layer 41 is provided with a side wall.

The gate oxide film 4 having a thickness of 5 nm is formed by thermal oxidation.
Then, deposition and etchback of n ⁺ doped polysilicon and deposition and etchback of tungsten silicide are performed to form first and second side walls, respectively. Subsequently, 100 nm of n ⁺ doped polysilicon is buried, and this is patterned (FIG. 14) .

The source / drain diffusion layer may be formed by using PSG for the spacer 43 and also diffusing phosphorus into the SOI from the spacer by heat treatment. In this case, the spacer may have a two-layer structure in which a thin oxide film is deposited after the deposition of PSG.

At the time of CMOS formation, the dummy oxide film 40 shown in FIG. 13 is removed only in a region where one channel type transistor is to be formed, and transistors are formed one by one. Alternatively, after removing one of the dummy oxide films 40 and forming one source / drain, a first mask oxide film is deposited, and the first mask oxide film in the region where the source / drain is formed is left. The first mask oxide film and the dummy oxide film of the opposite channels are patterned to form source / drain regions of different channel type transistors.

[0091] Next, as shown in FIG. 14, the first mask oxide film and the dummy oxide film is removed, the spacer 43 is deposited after the gate oxide film formation, a spacer 43 as a mask the resist only transistors of one channel Is removed, and a gate oxide film and a gate are formed after removing the resist. continue,
Using the resist as a mask, the gate material remaining on the first mask oxide film in the transistor formation region of the opposite channel is removed by isotropic chemical dry etching, and a second spacer having a thickness of 20 nm as a whole is provided. Is masked with a resist, and the thin second spacer and the spacer 43 in the transistor region of the opposite channel are etched by RIE to provide a side wall in the diffusion layer.

After removing the resist, a gate oxide film is formed and a gate is buried. Finally, the transistor on which the gate is formed later is covered with a resist, and using the resist as a mask, the gate material remaining on the second spacer on the transistor on which the gate is first formed is removed by isotropic chemical dry etching.

Alternatively, after forming both diffusion layers, a gate oxide film is formed, and after the gate is buried, one channel type region is covered with a resist, and the gate of the other channel type region is subjected to chemical dry etching. And the gate may be embedded in the other channel type after removing the resist.

FIG. 16 shows a modification of FIG. 1, in which a part of the source / drain diffusion layer 9 which is in contact with the channel region 10 is replaced with an LDD region composed of the n ⁻ region 13.
The impurity introduced into the n ⁻ region is, for example, an n-type impurity such as phosphorus, and its concentration is, for example, 1 × 10 ¹⁸ c
m ⁻³ , and its length is, for example, 50 nm.

FIG. 17 shows that a part of the LDD region composed of the n ⁻ region 13 in FIG. 16 extends to a part of the region below the second side wall 8.

FIG. 18 omits the first and second side walls on the drain side in FIG. 4 and extends the gate central portion 6 in the region where they are located.

FIG. 19 shows that, in the structure of FIG. 1, the gate oxide film thickness is set to 3 nm (corresponding to a black circle in the figure) or 5 nm (corresponding to a white circle in the figure), and the thickness of the first side wall of the threshold voltage is set. This is the result of obtaining the dependency on the simulation. The horizontal axis represents the thickness of the first side wall, and the vertical axis represents the threshold voltage. The distance between the gate end and the center of the first side wall is 30n
m and kept constant. The edge of the gate electrode coincides with the edge of the source / drain diffusion layer region at the lateral position.
The central portion of the gate and the second side wall are made of n ⁺ polysilicon, and the work function of the first side wall is 0.56 V larger than that of n ⁺ polysilicon. A drain current was determined with a channel width of 0.1 V, and a gate voltage at which a drain current of 10 ⁻⁷ A flows was defined as a threshold voltage.

In the figure, L is the total length of the gate, TSOI is SOI
The thickness of the layer, d is the distance between the gate edge and the center of the first sidewall,
VD indicates a drain voltage.

The threshold voltage increases as the thickness of the first side wall increases. This indicates that the threshold voltage can be continuously changed by changing the thickness of the first side wall, and the first problem can be solved.

FIG. 20 shows the S-factor when the SOI film thickness is changed in the structure obtained by performing the simulation of FIG. In the figure, L = 0.1 μm indicates that the gate has a total length of 0.1 μm, and L = 0.15 μm indicates that the gate has a total length of 0.15 μm. L =
The structures of 0.15 μm and L = 0.1 μm differ only in the lengths of the gate electrode central portion 6 and the channel formation region 10. In both cases, the width of the first side wall is 20 nm and the width of the second side wall is 20 nm. is there. The gate oxide film thickness Tox is 5 nm.

When a steep sub-threshold characteristic is to be obtained by suppressing the S factor to 100 mV / dec or less, when L = 0.15 μm, the SOI film thickness is 50 μm.
nm or less, L = 0.1 μm, SOI film thickness is 30 nm
It is understood that the following should be performed.

[0102]

As described above, according to the present invention, the sub-threshold characteristic is sharpened, the S factor can be improved, the short channel effect can be suppressed, and the on-current can be increased. is there. Further, there is also an effect that a problem in the threshold voltage and other element characteristics that occurs when the spread of the diffusion layer varies due to process variations can be suppressed.

[Brief description of the drawings]

FIG. 1 is a sectional view of an embodiment of the present invention.

FIG. 2 is a sectional view of an embodiment of the present invention.

FIG. 3 is a sectional view of an embodiment of the present invention.

FIG. 4 is a sectional view of an embodiment of the present invention.

FIG. 5 is a sectional view of an embodiment of the present invention.

FIG. 6 is a diagram illustrating a manufacturing method according to an example of the present invention. It is sectional drawing.

FIG. 7 is a diagram illustrating a manufacturing method according to an example of the present invention.

FIG. 8 is a diagram illustrating a manufacturing method according to an example of the present invention.

FIG. 9 is a diagram illustrating a manufacturing method according to an example of the present invention.

FIG. 10 is a sectional view of an embodiment of the present invention.

FIG. 11 is a diagram illustrating a manufacturing method according to an example of the present invention.

FIG. 12 is a sectional view of an embodiment of the present invention.

FIG. 13 is a sectional view of an embodiment of the present invention.

FIG. 14 is a sectional view of an embodiment of the present invention.

FIG. 15 is a sectional view of an embodiment of the present invention.

FIG. 16 is a sectional view of an embodiment of the present invention.

FIG. 17 is a sectional view of an embodiment of the present invention.

FIG. 18 is a sectional view of an embodiment of the present invention.

FIG. 19 is a diagram showing a simulation result of the example of the present invention.

FIG. 20 is a diagram showing a simulation result of the example of the present invention.

FIG. 21 is a diagram showing an example of a conventional field-effect transistor.

FIG. 22 is a diagram illustrating an example of a conventional field-effect transistor.

FIG. 23 is a diagram illustrating a problem of a conventional field-effect transistor.

FIG. 24 is a diagram illustrating a characteristic example of a conventional field-effect transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Substrate 2 Buried oxide film 3 SOI layer 4 Gate oxide film 5 Gate electrode 6 Gate electrode central part 7 First side wall 8 Second side wall 9 Source / drain diffusion layer 10 Channel formation region 11 Source region 12 Drain region 13 n ^- region 21 Polysilicon 22 TiN 23 n ⁺ -type doped polysilicon 24 first oxide film 25 PSG 26 second oxide film 27 third oxide film 29 p ⁺ -type doped polysilicon 30 tungsten silicide 31 BSG 40 dummy oxide film 41 Silicon layer 42 n ⁺ type source / drain 43 spacer

Claims (10)

(57) [Claims] 1. A gate insulating film and a gate electrode are stacked on a semiconductor layer, and at least a part of a portion of the semiconductor layer facing the gate electrode becomes a channel formation region, and the semiconductor layer sandwiches the channel formation region. A source / drain region formed of two first conductivity type diffusion layers, wherein the gate electrode comprises a first region located at a central portion, a second region outside the first region, and a second region outside the first region. When the first conductivity type is n-type, the second region is made of a material having a larger work function than any of the first and third regions, and the first conductivity type is p. In the case of a mold, the field-effect transistor is characterized in that the second region is made of a material having a lower work function than any of the first and third regions. Wherein said at least a portion of the third region, the field effect transistor of claim 1 than the top of the first conductivity type diffusion layer, characterized in that located in the channel forming region side. Wherein the semiconductor layer is a field-effect transistor of claim 1, wherein in that it is formed on the insulating film. 4. The field effect transistor according to claim 3, wherein said semiconductor layer has a thickness of 50 nm or less. Wherein said semiconductor layer is a field-effect transistor of claim 1, wherein it is a bulk semiconductor. 6. A gate electrode having a first region, a second region, and a third region arranged between a pair of n-type diffusion layers and a channel center located at an intermediate point between the pair of n-type diffusion layers. An electric field effect, wherein the second region is a material having a higher work function than any of the first and third regions, and the array structure is provided on at least one of the pair of diffusion layers. Transistor. 7. A gate electrode having an arrangement structure of a first region, a second region, and a third region between a pair of p-type diffusion layers and a channel center located at an intermediate point between the pair of p-type diffusion layers. The second region is a material having a work function smaller than that of any of the first and third regions, and the array structure is provided on at least one of the pair of diffusion layers. Transistor. 8. The field effect transistor according to claim 6, wherein said diffusion layer is formed in a semiconductor layer on an insulator. 9. A gate insulating film is formed on a semiconductor, a gate electrode made of a first material is formed thereon, and a second material is deposited on a side surface of the gate electrode. A certain anisotropic etchback is performed, followed by the deposition of the first or third material, and a selective anisotropic etchback with respect to the gate insulating film, from three regions from the center to the edge. A method for manufacturing a field effect transistor, comprising: forming a gate electrode, and diffusing a source / drain region before or after forming the gate electrode. 10. The method according to claim 1, wherein said second material region is formed and said second material region is formed.
Each after the region formation of the third material or the second material
After the formation of the region, a resist pattern was provided from the center of the gate electrode to one end thereof, and the resist pattern was formed at the one end using the resist pattern as a mask.
Claim 9, characterized in that it has to form a selective removal process of the second material or the third material in its outer
A method for manufacturing the field-effect transistor according to the above.