KR100504440B1 - Method for fabricating of semiconductor device - Google Patents
Method for fabricating of semiconductor device Download PDFInfo
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- KR100504440B1 KR100504440B1 KR10-2002-0086001A KR20020086001A KR100504440B1 KR 100504440 B1 KR100504440 B1 KR 100504440B1 KR 20020086001 A KR20020086001 A KR 20020086001A KR 100504440 B1 KR100504440 B1 KR 100504440B1
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000002955 isolation Methods 0.000 claims abstract description 31
- 238000005468 ion implantation Methods 0.000 claims abstract description 24
- 238000003860 storage Methods 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 150000004767 nitrides Chemical class 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 4
- 229920005591 polysilicon Polymers 0.000 claims abstract description 4
- 238000010586 diagram Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000011982 device technology Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 ISO 갭 필 마진을 확보하고 스토리지 노드 접합 면적을 감소시킬 수 있도록한 반도체 소자의 제조 방법에 관한 것으로, 스토리지부 접합 형성부의 액티브 면적이 감소되도록 장축의 CD를 감소된 ISO 마스크를 사용하여 소자 격리층을 형성하고, 웰 이온 주입 공정 및 채널(channel) 이온 주입을 실시하여 채널 이온 주입 영역을 형성하는 단계; 게이트 전극, 나이트라이드 캡층을 적층 형성하고 이를 마스크로 하여 LDD 영역을 형성하는 단계; 게이트 사이드월 산화막을 형성하고 랜딩 플러그 마스크 식각 공정시에 스토리지 노드부에 드러난 필드 산화막을 오버 에치하여 ISO 에지부의 실리콘 측면을 노출시키는 단계; 이온 주입 공정을 진행하여 소오스/드레인 영역 및 플러그 이온 주입 영역을 형성하는 단계; 도우프드 폴리 실리콘을 증착후에 평탄화 공정을 진행하여 랜딩 플러그층을 형성하는 단계를 포함한다.The present invention relates to a method of fabricating a semiconductor device to secure an ISO gap fill margin and to reduce a storage node junction area. The present invention relates to a long axis CD using a reduced ISO mask to reduce an active area of a storage junction junction. Forming a device isolation layer, and performing a well ion implantation process and a channel ion implantation to form a channel ion implantation region; Stacking the gate electrode and the nitride cap layer to form an LDD region using the mask as a mask; Forming a gate sidewall oxide layer and over-etching the field oxide layer exposed in the storage node portion during the landing plug mask etching process to expose the silicon side of the ISO edge portion; Performing an ion implantation process to form a source / drain region and a plug ion implantation region; And depositing the doped polysilicon, followed by a planarization process to form a landing plug layer.
Description
본 발명은 반도체 소자의 제조에 관한 것으로, 구체적으로 소자격리(isolation; 이하 ISO) 갭 필 마진을 확보하고 스토리지 노드 접합 면적을 감소시킬 수 있도록한 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly, to a method of manufacturing a semiconductor device capable of securing an isolation (ISO) gap fill margin and reducing a storage node junction area.
일반적으로 MOS 트랜지스터를 형성하기 위하여 실리콘 기판상에 웰(Well)을 형성한 후 이온 주입 공정으로 소오스 및 드레인을 형성한다.In general, a well is formed on a silicon substrate to form a MOS transistor, and then a source and a drain are formed by an ion implantation process.
이때 소자 동작시 드레인에 전압을 인가하고 게이트 on 상태에 두면 드레인에서 소오스로 전류가 흐르게 된다. 반면 게이트를 off 상태에 두면 드레인에서 소오스로 흐르는 전류가 없어져야 하는데 드레인에 드레인에 전압이 증가할 경우 원하지 않는 전류가 소오스로 흐르게 된다.At this time, when a voltage is applied to the drain while the device is in operation and the gate is turned on, current flows from the drain to the source. On the other hand, when the gate is off, the current flowing from the drain to the source must be eliminated. If the voltage is increased from the drain to the drain, unwanted current flows to the source.
상기 전류를 펀치 스루(Punch through) 전류라고 한다. 펀치 스루 전류는 디플리션(Depletion)층으로 캐리어가 인가되어 디플리션층의 바이어스에 캐리어가 이끌려 전류가 흐르게 되기 때문이다. This current is referred to as punch through current. The punch-through current is because a carrier is applied to the depletion layer so that the carrier is led to the bias of the depletion layer so that the current flows.
펀치 스루 현상은 게이트의 길이가 좁아질 수록 더욱 증가하며 소자 기술에 한계를 가져온다. 또한, 반도체 소자가 고집적화 함에 따라 생기는 셀(Cell) 영역과 주변영역의 높은 단차로 인하여 평탄화를 위한 후속 공정에 문제가 발생한다.The punch-through phenomenon increases as the gate length gets narrower, limiting device technology. In addition, there is a problem in the subsequent process for planarization due to the high level difference between the cell region and the peripheral region caused by the high integration of the semiconductor device.
도 1a와 도 1b는 종래 기술의 ISO 마스크의 구성 및 트랜지스터 단면 구성도이다.1A and 1B are a configuration of a conventional ISO mask and a cross-sectional view of a transistor.
도 1a는 종래 기술의 반도체 소자의 레이 아웃 구성 및 ISO 마스크의 구성도로서 (1)은 게이트 라인이고, (2)는 하나로 구성된 ISO 마스크이다.1A is a schematic diagram of a layout configuration and an ISO mask of a semiconductor device of the prior art, in which (1) is a gate line and (2) is an ISO mask composed of one.
종래 기술의 트랜지스터는 도 1b에서와 같이, 스토리지 노드의 접합 면적이 제한된 면적에서 수평으로 이루어져 (가)부분에서와 같이 접합 면적이 충분하지 않아 콘택 저항 증가 문제가 있다.Prior art transistors have a junction area of the storage node horizontally in a limited area, as shown in FIG. 1B, and thus there is a problem of increasing contact resistance because the junction area is not sufficient as shown in (a).
그리고 소오스/드레인 영역간의 채널 길이 역시 (나)에서와 같이, 수평적인 구성으로 소자의 고집적화 및 미세화에 따른 펀치스루 특성이 좋지 않다.In addition, the channel length between the source and drain regions is also in the horizontal configuration, so the punch-through characteristics due to the high integration and miniaturization of the device are not good.
도 1b에서 (3)은 필드 산화막이고, 소오스/드레인(4a)(4b)사이의 채널 영역상에 게이트(5)가 형성되는 구조이고, (6)은 스토리지 노드 콘택이다.In Fig. 1B, reference numeral 3 denotes a field oxide film, a gate 5 is formed on a channel region between the source / drain 4a and 4b, and reference numeral 6 denotes a storage node contact.
그러나 이와 같은 종래 기술의 반도체 소자의 제조 공정은 다음과 같은 문제점이 있다.However, the manufacturing process of such a semiconductor device of the prior art has the following problems.
종래 기술에서는 DRAM MOS 셀 트랜지스터 제조 공정 시 디자인 룰 감소에 따라 ISO 갭 필 마진이 부족하며, 셀 콘택 형성시도 영역 확보가 어려워 콘택 저항(이하 Rc) 증가에 따른 셀 구동력이 부족하다.In the prior art, an ISO gap fill margin is insufficient due to a decrease in design rules in the manufacturing process of a DRAM MOS cell transistor, and a cell driving force due to an increase in contact resistance (hereinafter Rc) is insufficient due to difficulty in securing a cell contact formation area.
또한, 트랜지스터 게이트 CD(Critical Dimension) 감소에 따라 셀 펀치스루 특성 취약해지며 이를 개선하기 위해 채널 도즈의 증가시에 접합부의 전계(electric field) 증가에 따른 리플래쉬(이하 tREF) 특성의 확보가 어렵다.In addition, the cell punch-through characteristics become weak due to the decrease of the transistor gate CD (critical dimension), and in order to improve this, it is difficult to secure a refresh (hereinafter referred to as tREF) characteristic due to an increase in the electric field of the junction when the channel dose is increased. .
본 발명은 이와 같은 종래 기술의 반도체 소자의 제조 공정의 문제를 해결하기 위하여 안출한 것으로, 비트 라인과 스토리지 노드간에 비대칭적인(asymmetry) 접합 구조를 형성하여 ISO 갭 필 마진을 확보하고 스토리지 노드 접합 면적을 감소시킬 수 있도록 한 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다. The present invention has been made to solve such a problem of the manufacturing process of the semiconductor device of the prior art, to form an asymmetric junction structure between the bit line and the storage node to secure the ISO gap fill margin and storage node junction area SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device capable of reducing the number of layers.
이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조 방법은 스토리지부 접합 형성부의 액티브 면적이 감소되도록 장축의 CD를 감소된 ISO 마스크를 사용하여 소자 격리층을 형성하고, 웰 이온 주입 공정 및 채널(channel) 이온 주입을 실시하여 채널 이온 주입 영역을 형성하는 단계; 게이트 전극, 나이트라이드 캡층을 적층 형성하고 이를 마스크로 하여 LDD 영역을 형성하는 단계; 게이트 사이드월 산화막을 형성하고 랜딩 플러그 마스크 식각 공정시에 스토리지 노드부에 드러난 필드 산화막을 오버 에치하여 ISO 에지부의 실리콘 측면을 노출시키는 단계; 이온 주입 공정을 진행하여 소오스/드레인 영역 및 플러그 이온 주입 영역을 형성하는 단계; 도우프드 폴리 실리콘을 증착후에 평탄화 공정을 진행하여 랜딩 플러그층을 형성하는 단계를 포함하는 것을 특징으로 한다.The semiconductor device manufacturing method according to the present invention for achieving the above object is to form a device isolation layer using a CD of a long axis reduced ISO mask so that the active area of the storage junction forming portion is reduced, and a well ion implantation process and Performing channel ion implantation to form a channel ion implantation region; Stacking the gate electrode and the nitride cap layer to form an LDD region using the mask as a mask; Forming a gate sidewall oxide layer and over-etching the field oxide layer exposed in the storage node portion during the landing plug mask etching process to expose the silicon side of the ISO edge portion; Performing an ion implantation process to form a source / drain region and a plug ion implantation region; And depositing the doped poly silicon to form a landing plug layer by performing a planarization process.
본 발명에 따른 반도체 소자의 제조 방법의 바람직한 실시예에 관하여 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.A preferred embodiment of the method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 따른 ISO 마스크의 구성도이고, 도 3a내지 도 3d는 본 발명에 따른 트랜지스터 제조를 위한 공정 단면도이다.2 is a configuration diagram of an ISO mask according to the present invention, Figures 3a to 3d is a cross-sectional view of the process for manufacturing a transistor according to the present invention.
본 발명은 MOS 트랜지스터 제조 방법에 관한 것으로 ISO 장축 CD를 줄임으로써 ISO 갭 필(Gap fill) 마진을 확보하고, 스토리지 노드(storage node) 접합 면적 감소를 통한 접합 누설 특성을 개선 가능하도록한 것이다.The present invention relates to a method for manufacturing a MOS transistor, and to reduce the ISO long-axis CD to secure the ISO gap fill margin, and to improve the junction leakage characteristics by reducing the storage node junction area.
또한, 플러그 폴리 콘택(plug poly contact) 형성시도 ISO 측면을 따라 콘택 영역의 면적을 충분히 확보하여 콘택 저항 특성을 획기적으로 가능하도록 하면서 비트 라인과 스토리지 노드간에 비대칭적(asymmetry)인 접합 구조를 형성하여 셀 트랜지스터 펀치스루(punch through) 마진도 개선할 수 있도록한 것이다.In addition, when forming a plug poly contact, the contact area along the ISO side is sufficiently secured to enable contact resistance characteristics, and an asymmetry junction structure is formed between the bit line and the storage node. It is also intended to improve cell transistor punch-through margins.
본 발명은 도 2에서와 같이, 게이트 마스크(21)와 ISO(isolation)마스크(22)를 만들 때 ISO 장축 CD를 감소하여 ISO 간 스페이스 마진을 증가시킬 수 있도록 구성한다.As shown in FIG. 2, when the gate mask 21 and the ISO (isolation) mask 22 are made, the present invention is configured to reduce the ISO long-axis CD to increase the space margin between ISOs.
이와 같은 ISO 마스크를 이용한 제조 공정은 먼저, 도 3a에서와 같이, 소자 격리 영역에 소자 격리층(31)을 형성하고 웰(well) 영역을 형성하기 위한 웰 이온 주입 공정 및 채널(channel) 이온 주입을 실시하여 채널 이온 주입 영역(32)을 형성한다.In the manufacturing process using the ISO mask, as shown in FIG. 3A, a well ion implantation process and a channel ion implantation for forming the device isolation layer 31 in the device isolation region and forming the well region are performed. Is performed to form the channel ion implantation region 32.
이어, 도 3b에서와 같이, 게이트 전극 형성용 물질층, 나이트라이드를 차례로 증착하고 선택적으로 패터닝하여 게이트 전극(33),나이트라이드 캡층(34)을 형성한다.Subsequently, as shown in FIG. 3B, the gate electrode forming material layer and nitride are sequentially deposited and selectively patterned to form the gate electrode 33 and the nitride cap layer 34.
그리고 상기 게이트 전극(33)을 마스크로 하여 LDD(Lightly Doped Drain) 이온 주입 공정을 진행하여 LDD 영역(35)을 형성한다.The LDD region 35 is formed by performing a lightly doped drain (LDD) ion implantation process using the gate electrode 33 as a mask.
이어, 전면에 스페이서 형성용 산화막을 증착하고 에치백하여 게이트 사이드월 산화막(36)을 형성한다.Subsequently, an oxide film for spacer formation is deposited on the entire surface and etched back to form a gate sidewall oxide film 36.
그리고 도 3c에서와 같이, 랜딩 플러그 마스크 식각 공정시에 스토리지 노드부에 드러난 필드 산화막을 충분하게 오버 에치하여 ISO 에지부의 실리콘 측면이 100Å이상 드러나도록 한다.In addition, as illustrated in FIG. 3C, the field oxide layer exposed to the storage node portion is sufficiently overetched during the landing plug mask etching process so that the silicon side of the ISO edge portion is exposed to 100 μs or more.
이와 같은 오버 에치를 통하여 랜딩 플러그 콘택 접촉면을 라운딩(rounding) 지게 만들어 Rc를 개선 가능하도록 한다.This over-etching makes the landing plug contact contact surface rounding to improve Rc.
이때, 습식각 등을 이용하여 콘택 형성 영역을 충분하게 확보해준 후 50KeV 이하의 로우 에너지로 N-타입 이온 주입 공정을 진행하여 소오스/드레인 영역 및 플러그 이온 주입 영역(37)을 형성한다.At this time, the contact formation region is sufficiently secured using wet etching, and the N-type ion implantation process is performed at low energy of 50 KeV or less to form the source / drain region and the plug ion implantation region 37.
이어, 도 3d에서와 같이, 전면에 n형 도우프드 폴리 실리콘을 증착후에 평탄화 공정을 진행하여 랜딩 플러그층(38)을 형성한다.Next, as shown in FIG. 3D, the landing plug layer 38 is formed by performing a planarization process after depositing n-type doped polysilicon on the entire surface.
이와 같은 공정으로 형성된 본 발명에 따른 트랜지스터는 도 3d의 (다)에서와 같이 콘택 마진이 충분이 확보되고, (라)에서와 같이 채널 영역이 충분히 확보되도록 비대칭적인 구조를 갖는다.The transistor according to the present invention formed by such a process has an asymmetrical structure such that sufficient contact margin is secured as shown in (C) of FIG. 3D and sufficient channel region is secured as shown in (D).
그리고 도 4는 본 발명의 다른 실시예에 따른 트랜지스터의 단면 구성도이다.4 is a cross-sectional configuration diagram of a transistor according to another embodiment of the present invention.
도 4에서와 같이 ISO 장축 CD를 게이트 에지부까지 감소시키고 랜딩 플러그 폴리를 형성하기 전에 에피택셜 실리콘층을 성장시켜 스토리지 노드부에 n+ 접합 영역(41)을 형성하여 N-/N+의 계단 접합 구조를 형성하는 것도 가능하다.As shown in Fig. 4, a step junction structure of N- / N + is formed by reducing the ISO long-axis CD to the gate edge and growing an epitaxial silicon layer to form an n + junction region 41 in the storage node before forming the landing plug poly. It is also possible to form a.
이는 N+ 접합 에피택셜층의 농도를 조절함으로써 계단 접합(graded junction)을 조정하여 전계 특성을 개선할 수 있어 DRAM 셀 트랜지스터 tREF 개선을 용이하도록 할 수 있다.This may improve the electric field characteristics by adjusting the graded junction by adjusting the concentration of the N + junction epitaxial layer, thereby facilitating the improvement of the DRAM cell transistor tREF.
이상 설명한 내용을 통해 당업자라면 본 발명의 기술 사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.
따라서, 본 발명의 기술적 범위는 실시예에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의하여 정해져야 한다.Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.
이상에서 설명한 본 발명에 따른 반도체 소자의 제조 방법은 다음과 같은 효과가 있다.The method of manufacturing a semiconductor device according to the present invention described above has the following effects.
첫째, 본 발명은 DRAM 셀 트랜지스터 제조시에 ISO 장축 CD를 줄임으로써 ISO 갭 필(Gap fill) 마진을 확보할 수 있다.First, the present invention can secure the ISO gap fill margin by reducing the ISO long-axis CD in the manufacture of DRAM cell transistors.
둘째, 스토리지 노드(storage node) 접합 면적 감소를 통한 접합 누설 특성을 개선 가능하도록 하는 효과가 있다.Second, there is an effect to improve the junction leakage characteristics by reducing the storage node junction area.
셋째, 플러그 폴리 콘택(plug poly contact) 형성시도 ISO 측면을 따라 콘택 영역의 면적을 충분히 확보하여 콘택 저항 특성을 획기적으로 가능하도록 하는 효과가 있다.Third, even when forming a plug poly contact, the contact area is sufficiently secured along the ISO side, and thus, the contact resistance characteristic can be significantly improved.
넷째, 스토리지 정션의 ISO 측면을 따라 플러그 이온 주입을 하여 로우 에너지로도 접합 깊이의 증가가 가능하고, 비트 라인 접합부와 비대칭적인(asymmetry)구조를 형성하여 셀 트랜지스터 펀치 스루 누설(punch through leakage) 특성을 개선할 수 있다.Fourth, plug ion implantation along the ISO side of the storage junction allows for increased junction depth even with low energy, and cell transistor punch through leakage characteristics by forming an asymmetry structure with the bit line junction. Can be improved.
도 1a와 도 1b는 종래 기술의 ISO 마스크의 구성 및 트랜지스터 단면 구성도1A and 1B show a configuration of a conventional ISO mask and a cross-sectional view of a transistor
도 2는 본 발명에 따른 ISO 마스크의 구성도2 is a block diagram of an ISO mask according to the present invention
도 3a내지 도 3d는 본 발명에 따른 트랜지스터 제조를 위한 공정 단면도3A to 3D are cross-sectional views of a process for fabricating a transistor in accordance with the present invention.
도 4는 본 발명의 다른 실시예에 따른 트랜지스터의 단면 구성도 4 is a cross-sectional configuration diagram of a transistor according to another embodiment of the present invention.
- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-
31. 소자 격리층 32. 채널 이온 주입 영역31. Device isolation layer 32. Channel ion implantation region
33. 게이트 전극 34. 나이트라이드 캡층33. Gate electrode 34. Nitride cap layer
35. LDD 영역 36. 게이트 사이드월 스페이서35. LDD Region 36. Gate Sidewall Spacers
37. 플러그 이온 주입 영역 38. 랜딩 플러그층37. Plug ion implantation area 38. Landing plug layer
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