KR20100011801A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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Publication number
KR20100011801A
KR20100011801A KR1020080073171A KR20080073171A KR20100011801A KR 20100011801 A KR20100011801 A KR 20100011801A KR 1020080073171 A KR1020080073171 A KR 1020080073171A KR 20080073171 A KR20080073171 A KR 20080073171A KR 20100011801 A KR20100011801 A KR 20100011801A
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KR
South Korea
Prior art keywords
layer
diffusion barrier
semiconductor device
active region
film
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KR1020080073171A
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Korean (ko)
Inventor
김영훈
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주식회사 하이닉스반도체
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Priority to KR1020080073171A priority Critical patent/KR20100011801A/en
Publication of KR20100011801A publication Critical patent/KR20100011801A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: A semiconductor device and a method of manufacturing the same are provided to prevent the unevenness of a boron concentration in a channel region of an active area by using the diffusion barrier. CONSTITUTION: A semiconductor device comprises a semiconductor substrate(100), an element isolation layer(F), and an ion implantation layer(106). The semiconductor substrate has an active area(A). The active area is projected from the element isolation layer. An ion implanted layer is arranged in the active area. The semiconductor device also includes the diffusion barrier layer(108) and a gate insulating layer(100). The diffusion barrier is formed on the active area and element isolation layer. The gate insulating layer is formed on the diffusion barrier.

Description

Semiconductor device and method for manufacturing same {SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the semiconductor device capable of improving the threshold voltage by preventing the uneven phenomenon of boron due to the diffusion of the channel region when forming the projection gate. It is about.

As semiconductor devices are highly integrated, channel lengths of transistors are decreasing, and ion implantation concentrations into junction regions (source / drain regions) are increasing.

As a result, a so-called short channel effect is generated in which interference between the source / drain regions increases, control of the gate decreases, and the threshold voltage Vt is drastically lowered.

In addition, a problem arises in that the refresh characteristic is degraded due to an increase in the junction leakage current due to an increase in the electric field of the junction region. Therefore, the structure of a transistor having a conventional planar channel structure has reached its limit in overcoming the problems associated with the high integration.

As a result, it is difficult to obtain a threshold voltage value required by a highly integrated device using a conventional planar channel structure transistor, which leads to a limit in improving refresh characteristics.

Accordingly, research on the idea of the implementation of a gate having a channel having a three-dimensional structure capable of expanding a channel region and an actual process development research are being actively conducted.

One such effort has recently been proposed in the field of logic devices (Fin Gate) having a channel having a three-dimensional structure. The protruding gate has a structure in which a gate line is formed to protrude a portion of the active region and surround the protruding active region. In this case, an effective channel width is increased to improve current drive characteristics through the channel. Threshold voltage margin is improved.

On the other hand, as semiconductor devices are highly integrated, protrusions having a recessed channel structure are formed by etching the gate forming regions of the active regions while forming the protruding gates as described above to overcome the deterioration due to the short channel effect due to the decrease in the channel length. The type gate is applied.

The protruding gate having the recessed channel structure combines the advantages of the short channel dose in the recess gate and the excellent leakage current control capability of the protruding gate.

However, although not shown and described in detail, in the case of the above-described protruding gate, after the boron ion implantation process is performed to form the channel region, the protruding structure is formed by protruding the active region by etching the device isolation layer. The surface of the active region and the device isolation layer is oxidized to form a gate insulating layer. During the thermal oxidation process for oxidizing the active region and the device isolation layer, boron implanted into the channel region diffuses, The boron concentration in the active area becomes uneven.

In addition, the unevenness of the boron concentration due to the diffusion becomes deeper as the channel width becomes smaller in the semiconductor device having the protruding gate.

Therefore, if the uneven change in the boron concentration becomes severe according to the change in the channel width, the change in the threshold voltage also becomes severe, resulting in deterioration of the characteristics of the threshold voltage.

The present invention provides a semiconductor device and a method for manufacturing the same, which can prevent unevenness of boron concentration when forming a projection gate.

In addition, the present invention provides a semiconductor device and a method of manufacturing the same that can prevent the deterioration of the characteristics of the threshold voltage when forming the projection gate.

A semiconductor device according to the present invention includes a semiconductor substrate having an active region; An isolation layer formed to protrude the active region in the semiconductor substrate; An ion implantation layer formed in the active region; A diffusion barrier layer formed on the active region and the device isolation layer in which the ion implantation layer is formed; And a gate insulating film formed on the diffusion barrier film.

The ion implantation layer comprises a boron ion implantation layer.

The diffusion barrier layer includes a silicon germanium (SiGe) layer.

The diffusion barrier is characterized in that it has a thickness of 100 ~ 200Å.

The gate insulating film includes an oxide film.

In addition, the method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming a device isolation film in a semiconductor substrate, defining an active region of the semiconductor substrate; Etching the device isolation layer to protrude the active region; Forming a diffusion barrier on the semiconductor substrate including the device isolation layer and the active region; And forming a gate insulating film on the diffusion barrier.

And forming an ion implantation layer in the active region between the forming of the device isolation layer and the etching of the device isolation layer.

The ion implantation layer is formed of a boron ion implantation layer.

The forming of the diffusion barrier layer is performed in an epitaxial or deposition method.

The diffusion barrier layer is formed of a silicon germanium (SiGe) layer.

The diffusion barrier is formed to a thickness of 100 ~ 200Å.

The forming of the gate insulating film may include oxidizing the diffusion barrier film by a thermal oxidation process.

According to the present invention, a diffusion barrier layer made of silicon germanium is formed on an active region having a protrusion structure and a surface of an isolation layer to form a protrusion gate, thereby performing boron formed in the active region during a thermal oxidation process for forming a gate insulating film. Diffusion can be prevented.

Therefore, the present invention can prevent the boron concentration in the channel region of the active region from becoming uneven.

In addition, the present invention forms a diffusion barrier film made of silicon germanium on the active region having the protrusion structure and the surface of the device isolation layer, thereby preventing the diffusion of boron and the resulting unevenness of the boron concentration regardless of the channel width. .

As a result, the present invention can also prevent a change in the threshold voltage, thereby improving the characteristics of the threshold voltage.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

In detail, FIG. 1 is a plan view illustrating a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention, and FIG. 2 is a semiconductor device according to an embodiment of the present invention corresponding to a YY ′ cutting line of FIG. 1. As a cross-sectional view for explaining, it is as follows.

As shown in FIG. 2, a semiconductor device according to an exemplary embodiment of the present invention may include an isolation region F and an active region A of the semiconductor substrate 100 having an active region A defined by the isolation layer F. In FIG. In (A), the ion implantation layer 106 for adjusting the threshold voltage is formed.

In this case, the active region A is formed to protrude upward from the device isolation film F so as to have a height higher than that of the device isolation film F.

In addition, the ion implantation layer 106 is made of a boron ion implantation layer.

In addition, a diffusion barrier layer 108 is formed on the semiconductor substrate 100 including the device isolation layer F and an active region A formed to have a height higher than that of the device isolation layer F.

Here, the diffusion barrier 108 is made of a silicon germanium (SiGe) film having a thickness of 100 ~ 200Å.

In addition, a gate including a stacked layer of the gate insulating layer 110, the gate conductive layer 112, and the gate hard mask layer 114 is formed on the diffusion barrier layer 108.

The gate insulating layer 110 may be formed of an oxide film, and the gate conductive layer 112 may be formed of a tungsten film or a tungsten silicide film.

Specifically, FIGS. 3A to 3E are cross-sectional views illustrating processes for manufacturing a semiconductor device according to an exemplary embodiment of the present invention corresponding to Y-Y ′ cutting lines of FIG. 1.

Referring to FIG. 3A, a threshold is formed in the active region A of the semiconductor substrate 100 having the device isolation film F and the active region A defined by the device isolation film F. An ion implantation layer 106 for voltage regulation is formed.

Here, the ion implantation layer 116 is formed of a boron ion implantation layer.

Referring to FIG. 3B, a portion of the device isolation film F adjacent to the active region A in which the boron ion implantation layer 106 is formed by the ion implantation process is etched so that the active region A becomes the device isolation film F. Referring to FIG. It is formed to protrude upward.

Referring to FIG. 3C, the diffusion barrier 108 is formed on the upper surface of the semiconductor substrate 100 including the protruding active region A and the device isolation layer F by using an epitaxial or deposition method. Form.

At this time, the diffusion barrier 108 is preferably formed of a silicon germanium (SiGe) film having a thickness of 100 ~ 200Å.

Referring to FIG. 3D, the diffusion barrier 108 is oxidized by a thermal oxidation process 118 to form a gate insulating layer 110 formed of an oxide layer on the diffusion barrier 108.

Referring to FIG. 3E, the gate conductive layer 112 and the gate hard mask layer 114 are formed on the gate insulating layer 110 formed by the thermal oxidation process of the diffusion barrier layer 108.

Thereafter, the gate hard mask layer 114, the gate conductive layer 112, and the gate insulating layer 110 are etched to stack the gate insulating layer 110, the gate conductive layer 112, and the gate hard mask layer 114. The semiconductor device according to the embodiment of the present invention is completed by forming a gate made of a film.

The gate conductive layer 112 may be formed of tungsten or a tungsten silicide layer.

As described above, the present invention forms a protruding gate by forming a diffusion barrier film made of silicon germanium on the active region having the protruding structure and the surface of the device isolation film as described above, thereby forming a gate by the diffusion barrier film made of the silicon germanium. During the thermal oxidation process for forming the insulating layer, it is possible to prevent the diffusion of boron in the channel region formed in the active region.

Therefore, as described above, the diffusion of boron can be prevented, so that the boron concentration in the channel region of the active region can be prevented from becoming uneven.

In addition, by forming a diffusion barrier film made of silicon germanium on the active region and the surface of the device isolation layer having a projection structure as described above, it is possible to prevent the diffusion of boron and the resulting unevenness of the boron concentration regardless of the size of the channel width. .

As a result, a change in the threshold voltage can also be prevented, so that the characteristics of the threshold voltage can be improved.

In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

1 is a plan view illustrating a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention corresponding to a cutting line Y-Y ′ in FIG. 1.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, which corresponds to the Y-Y ′ cutting line of FIG. 1.

Claims (12)

A semiconductor substrate having an active region; An isolation layer formed to protrude the active region in the semiconductor substrate; An ion implantation layer formed in the active region; A diffusion barrier layer formed on the active region and the device isolation layer in which the ion implantation layer is formed; And A gate insulating film formed on the diffusion barrier film; A semiconductor device comprising a. The method of claim 1, The ion implantation layer comprises a boron ion implantation layer. The method of claim 1, The diffusion barrier layer comprises a silicon germanium (SiGe) film. The method of claim 1, The diffusion barrier is a semiconductor device, characterized in that having a thickness of 100 ~ 200Å. The method of claim 1, And the gate insulating film comprises an oxide film. Forming an isolation layer in the semiconductor substrate, the device isolation layer defining an active region of the semiconductor substrate; Etching the device isolation layer to protrude the active region; Forming a diffusion barrier on the semiconductor substrate including the device isolation layer and the active region; And Forming a gate insulating film on the diffusion barrier film; Method of manufacturing a semiconductor device comprising a. The method of claim 6, Between forming the device isolation film, and etching the device isolation film, Forming an ion implantation layer in said active region; Method of manufacturing a semiconductor device further comprising. The method of claim 7, wherein The ion implantation layer is a semiconductor device manufacturing method, characterized in that formed as a boron ion implantation layer. The method of claim 6, The forming of the diffusion barrier layer is a method of manufacturing a semiconductor device, characterized in that the epitaxial (Epitaxial) or deposition (Deposition) method. The method of claim 6, The diffusion barrier layer is a semiconductor device manufacturing method, characterized in that formed of a silicon germanium (SiGe) film. The method of claim 6, The diffusion barrier is a semiconductor device manufacturing method, characterized in that formed in a thickness of 100 ~ 200∼. The method of claim 6, Forming the gate insulating film, Oxidizing the diffusion barrier layer by a thermal oxidation process; Method for manufacturing a semiconductor device, characterized in that consisting of.
KR1020080073171A 2008-07-25 2008-07-25 Semiconductor device and method of manufacturing the same KR20100011801A (en)

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KR1020080073171A KR20100011801A (en) 2008-07-25 2008-07-25 Semiconductor device and method of manufacturing the same

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KR20100011801A true KR20100011801A (en) 2010-02-03

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