KR100605108B1 - FinFET AND METHOD OF FABRICATING THE SAME - Google Patents

Abstract

Provided are a fin field effect transistor and a method of manufacturing the same. The transistor includes a fin extending vertically on a substrate and a gate electrode surrounding the fin and crossing the top of the fin. A gate insulating film is interposed between the gate electrode and the fin, and a source region and a drain region are formed in the fin on both sides of the gate electrode. The width of the fin becomes wider under the gate electrode. That is, the fin may have a 'T' shaped plane composed of a first region having a first fin width and a second region having a second fin width wider than the first fin width. The source region is formed in the first region, and the drain region is formed in the second region. A boundary region of the first region and the second region overlaps a lower portion of the gate electrode.

Description

Fin field effect transistor and its manufacturing method {FinFET AND METHOD OF FABRICATING THE SAME}

1 is a perspective view showing a vertical double gate transistor according to the prior art.

2 is a perspective view illustrating a fin field effect transistor according to a first embodiment of the present invention.

3 is a graph illustrating the threshold voltage of the pin field effect transistor according to the present invention.

4 is a plan view illustrating a portion of a DRAM cell array including a fin field effect transistor according to a first exemplary embodiment of the present invention.

5, 6, 7A, 8A, and 9A are plan views illustrating a method of manufacturing a DRAM cell array according to a first embodiment of the present invention.

7B, 7C, 7D, 8B, and 9B are cross-sectional views illustrating a method of manufacturing a DRAM cell array according to a first embodiment of the present invention.

10A and 10B are plan views illustrating a modification of the first embodiment of the present invention.

11 is a plan view illustrating a fin field effect transistor according to a second exemplary embodiment of the present invention.

12A and 12B are graphs showing doping concentrations and energy bands according to positions along II-II ′ of FIG. 11, respectively.

13A and 13B are graphs illustrating an energy band model in operation of a fin field effect transistor according to a second exemplary embodiment of the present invention.

14A and 14B are plan views each showing a modification of the second embodiment of the present invention.

15 is a perspective view showing a modification of the second embodiment of the present invention.

16A to 16D are diagrams for describing a method of manufacturing the fin field effect transistor according to the second embodiment of the present invention.

TECHNICAL FIELD The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a fin field effect transistor having a vertical channel and a method of manufacturing the same.

Transistors having a horizontal channel, which is a general structure, have various problems as design rules are reduced, thereby limiting the scale-down of transistors. The biggest problem of the reduced horizontal channel transistors is the short channel length and short channel effect and drain induced barrier lower (DIBL) effect. In conventional transistors, when the channel length is reduced to 50 nm or less, the scattering of device characteristics is increased by process variables, and when the channel length is 30 nm or less, the short channel effect and DIBL effect become severe and it is difficult for the transistor to operate normally. Known.

In order to overcome the problems of horizontal channel transistors, one of the devices that has been studied recently is a double gate transistor. The double gate transistor has a structure having a thickness of 30 nm or less, and a gate surrounding the channel or disposed at both sides of the channel. In the conventional transistor, since the gate electrode is formed only on the upper portion of the horizontal channel, an electric field is applied asymmetrically to the channel, and the on and off of the transistor is not effectively controlled by the gate electrode. As a result, the effect of short channel effects due to the reduction of the channel is severe.

In contrast, since the double gate transistor is formed at the gate electrodes on both sides of the thin channel, all regions of the channel are affected by the gate electrode. Therefore, since the charge flow between the source and the drain can be suppressed when the transistor is off, power consumption can be reduced, and the on / off of the transistor can be effectively controlled.

US Patent Publication No. US 2002/0177263 "DAMASCENE DOUBLE-GATE MOSFET WITH VERTICAL CHANNEL", US Pat. REGIONIS ").

1 is a perspective view illustrating Hussein's damascene double gate MOS transistor. According to FIG. 1, the transistor includes a silicon layer 10 formed on the insulating film 12 and a gate electrode 28 disposed across the silicon layer 10. A hard mask pattern 18 is formed on the silicon layer 10 while overlapping the gate electrode 28, and a gate insulating layer 30 is formed between the gate electrode 28 and sidewalls of the silicon layer 10. Is interposed. Source / drain regions 22 are formed in the silicon layer 10 on both sides of the gate electrode 28.

As mentioned above, the double gate MOS transistor having a vertical channel can increase the controllability of the gate with respect to the channel because the width of the silicon layer on which the channel is formed is narrow. In general, since the silicon layer has a width of several nanometers to several tens of nanometers, it may be called a fin field effect transistor depending on its shape. The fin field effect transistor has the same advantages as described above, but has a problem in that the threshold voltage of the transistor drops sharply below a certain pin width. Therefore, the threshold voltage is not easily controlled due to a large change in the characteristics of the transistor due to process variables, and cell uniformity may be deteriorated when applied to a highly integrated memory device.

As the threshold voltage of the transistor decreases, the subthreshold leakage may increase. The leakage current of the transistor causes a deterioration of the characteristics of the semiconductor element. In particular, leakage current in DRAM devices degrades data retention characteristics, and it is very important to minimize leakage current in the source region to which the capacitor is connected. Consider increasing the channel concentration to increase the threshold voltage of the transistor. However, increasing the threshold voltage reduces the turn-on current of the transistor, and increasing the channel concentration causes increased junction leakage. Therefore, when applied to the DRAM device, the write margin may be reduced due to the decrease in turn-on current, and the data retention characteristic may be degraded due to the increase of the storage node junction leakage.

An object of the present invention is to provide a pin field effect transistor with improved threshold voltage control capability and a method of manufacturing the same.

 Another object of the present invention is to provide a fin field effect transistor having a structure capable of suppressing leakage current generation in a source region and a method of manufacturing the same.

Another object of the present invention is to provide a pin field effect transistor having a high turn-on current and suppressed sub-threshold leakage and junction leakage, and a method of manufacturing the same.

In order to achieve the above technical problem, the present invention provides a fin field effect transistor having different widths of a source region and a drain region. The transistor includes a fin extending vertically on a substrate and a gate electrode surrounding the fin and crossing the top of the fin. A gate insulating film is interposed between the gate electrode and the fin, and a source region and a drain region are formed in the fin on both sides of the gate electrode. The width of the fin becomes wider under the gate electrode. That is, the fin may have a 'T' shaped plane composed of a first region having a first fin width and a second region having a second fin width wider than the first fin width. The source region is formed in the first region, and the drain region is formed in the second region. A boundary region of the first region and the second region overlaps a lower portion of the gate electrode.

According to an embodiment of the present invention, a fin field effect transistor includes a fin vertically extended on a substrate, a gate electrode surrounding the fin and crossing the upper portion of the fin, and a gate interposed between the gate electrode and the fin. And an insulating layer, a source region and a drain region respectively formed in the fins on both sides of the gate electrode, and a channel region formed in the fin between the source region and the drain region. In this embodiment, the fin width of the drain region is wider than the fin width of the source region, and the impurity concentration of the channel region adjacent to the drain region is higher than the impurity concentration of the channel region adjacent to the source region.

The fin field effect transistor according to the present invention can be applied to cell transistor formation of DRAM devices. Specifically, the device comprises a pin extending vertically on a substrate, and a gate electrode pair surrounding the pin and crossing the top of the pin. A gate insulating film is interposed between the gate electrodes and the fin. Common drain regions are formed in the fins between the gate electrodes, and source regions are formed in the fins on both sides of the gate electrode pair. The width of the fin becomes wider under each gate electrode. That is, the fin may be composed of a pair of first regions having a first fin width and a second region having a second fin width located between the first region and wider than the first fin width. The source region is formed in the first region, and the common drain region is formed in the second region. A boundary region of the first region and the second region overlaps the gate electrode.

According to another embodiment, a cell transistor of a DRAM device may include a pin extending vertically on a substrate, a gate electrode pair surrounding the pin and crossing the upper portion of the fin, the gate electrodes and the fin. A gate insulating layer interposed therebetween, a common drain region formed in the fin between the gate electrodes, a source region formed in each of the fins on both sides of the gate electrode pair, and a fin between the common drain region and the source region, respectively. The channel region may be formed. In this embodiment, the fin width of the common drain region is wider than the fin width of the source region, and the impurity concentration of the channel region adjacent to the common drain region is higher than the impurity concentration of the channel region adjacent to the source region.

In order to achieve the above technical problem, the present invention provides a method for manufacturing a fin field effect transistor. The method includes forming a fin vertically extending on a substrate, the fin including a first region having a first fin width and a second region having a second fin width wider than the first fin width. Conformally forming a gate insulating film on at least sidewalls of the fin. A gate electrode is formed on the gate insulating layer to cross the upper portion of the fin and surround the fin. The gate electrode is formed to overlap an upper portion of a boundary between the first region and the second region.

The pin may have a first region and a second region in a shape that gradually increases or decreases in width. A source region defining a channel region under the gate electrode by implanting a first conductivity type impurity into the fin on one side of the gate electrode and implanting a second conductivity type impurity into the fin using the gate electrode as an ion implantation mask; In addition to forming a drain region, a first conductivity type diffusion layer may be formed in a channel region adjacent to the drain region. The first conductivity type diffusion layer may be formed in the channel region by extending the lateral diffusion distance of the first conductivity type impurity than the lateral diffusion distance of the second conductivity type impurity.

The fins may be formed to have different widths by a photolithography process, but may be formed to have different widths by partial thermal oxidation. Specifically, the semiconductor substrate is patterned to form vertically elongated fins having a second fin width, and a mask pattern covering a portion of the fins is formed. The sidewall of the fin is oxidized by using the mask pattern as an anti-oxidation film. The sacrificial oxide film is formed on the sidewall of the fin by the sidewall oxidation. The sacrificial oxide film is removed to form a first region having a first fin width, and the mask pattern is removed to expose a second region having the second fin width.

The fin field effect transistor according to the present invention may be formed on an SOI substrate. That is, the fin may be formed by patterning a semiconductor layer on the insulating film. When the fin is formed on a bulk silicon substrate, the fin may be formed by patterning the substrate, and after forming the fin, an isolation layer may be formed on the semiconductor substrate to isolate the fin.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween.

2 is a perspective view illustrating a fin field effect transistor according to a first embodiment of the present invention.

This transistor has a pin 200 extending vertically. The fin 200 includes a first region having a first fin width W1 and a second region having a second fin width W2 that is wider than the first fin width W1. The gate electrode 210 crosses the upper portion of the fin 200 while surrounding the fin 200. A gate insulating layer 208 is interposed between the gate electrode 210 and the fin 200. Source and drain regions 202s and 202d are formed in the fins on both sides of the gate electrode 210, respectively. The source region 202s is formed in a narrow first region, and the drain region 202d is formed in a wide second region.

A boundary region of the first region and the second region overlaps the gate electrode 210. A portion overlapping the gate electrode 210, that is, a region between the source region 202s and the drain region 202d corresponds to a channel region of the transistor. Thus, the channel region is also formed over the first region and the second region.

3 is a graph illustrating the threshold voltage of the fin field effect transistor according to the first embodiment of the present invention. In the graph, the horizontal axis represents the width of the pin and the vertical axis represents the threshold voltage. As shown, when the width of the pin is lowered below a certain width, the threshold voltage is drastically lowered. For example, when the width of the pin is W1, the threshold voltage Vth1 is located in a section where the rate of change ΔVth / ΔW is high. In this section, even if the width of the pin changes slightly due to instability of the process, the threshold voltage fluctuates greatly. On the other hand, when the width of the pin is W2, the threshold voltage Vth2 is located in a section where the threshold voltage change rate is low. In this section, even if the width of the pin changes due to instability of the process, there is little variation in the threshold voltage. Therefore, the fin field effect transistor preferably has a fin width of a predetermined width or more.

In this aspect, the fin field effect transistor according to the present invention has a structure including a narrow portion of the fin and a wide region of the fin, that is, a structure in which two channel regions having different threshold voltages are connected in series. By forming a source region in the narrow portion of the fin, the source junction leakage current can be lowered and the occurrence of soft error can be suppressed. Therefore, according to the present invention, the rate of change of the threshold voltage due to instability of the process can be lowered without increasing the pin width of the source side. The transistors could be useful in DRAM devices because of low source junction leakage currents and the suppression of soft errors. Pin-field transistors operate by completely depleting the gate and the overlapping fins. As a result, it has a significantly higher current driving efficiency than a general flat plate transistor. Therefore, a narrow fin width on the source side and a wide fin width on the drain side may have an effect to increase the drain current amount, but the drain current increase effect is not expected because the fin current effect transistor has a high drain current. Will be.

4 is a plan view illustrating a portion of a DRAM cell array including a fin field effect transistor according to a first exemplary embodiment of the present invention.

Referring to FIG. 4, the DRAM cell array according to the present invention has a structure in which an active region of a conventional DRAM cell array is replaced with a fin. Specifically, the plurality of fins 112 are formed on the substrate. The substrate may be an SOI substrate or a bulk semiconductor substrate. In the case of an SOI substrate, the fin may be formed on an insulating layer, and in the case of a bulk semiconductor substrate, the semiconductor substrate may be etched. The fin 112 is composed of a first region 112a having a first fin width and a second region 112b having a second fin width. First regions 112a are positioned at both sides of the fin, and second regions 112b are positioned between the first regions 112a. A gate electrode pair 110p crosses the top of each fin 112. Each gate electrode 110 overlaps an upper portion of a boundary between the first region 112a and the second region 112b. Source regions 112s are formed in the fins on both sides of the gate electrode pair 110p, and common drain regions 112d are formed in the fins between the gate electrodes 110. Although not shown, capacitors are connected to the source region 112s, respectively, and bit lines are connected to the common drain region 112d.

According to the present invention, a channel of a transistor is composed of two channels having different threshold voltages. In addition, the source region is formed in a narrow region and the drain region is formed in a relatively wide region. Therefore, the source junction leakage current can be lowered and the occurrence of soft errors can be suppressed. However, since the width of the fin extends under the gate electrode, the threshold voltage can be increased to improve the controllability of the threshold voltage and to prevent a decrease in the amount of drain current.

The fin field effect transistor according to the present invention can be manufactured using a commonly known process. That is, it may be formed on an SOI substrate or a bulk silicon substrate, or may be formed by applying a conventional gate process or a damascene gate process.

5, 6, 7A, 8A, and 9A are plan views illustrating a method of manufacturing a DRAM cell array according to a first embodiment of the present invention.

7B, 7C, 7D, 8B, and 9B are cross-sectional views illustrating a method of manufacturing a DRAM cell array according to a first embodiment of the present invention.

Referring to FIG. 5, a plurality of fins 52 are formed on a substrate. The substrate may be an SOI substrate or a semiconductor bulk substrate. In the SOI substrate, the fins 52 may be formed on the insulating layer, and in the semiconductor bulk substrate, the fins 52 may be connected to the substrate and extend vertically. The semiconductor layer of the SOI substrate and the semiconductor bulk substrate may be one selected from silicon, germanium, silicon germanium, and graded silicon germanium or a laminate thereof.

Referring to FIG. 6, a mask pattern 53 is formed on the substrate to cross the upper center of the fins. The fin pattern 52 is thermally oxidized using the mask pattern 53 as an anti-oxidation film to form a sacrificial oxide film 54 on the sidewalls of the fins 52. As the semiconductor layer of the fin is consumed by thermal oxidation, the width of the fin is recessed and a thermal oxide film is formed on the surface. As a result, a first region 52a having a first fin width is formed on both sides of the fin 52, and a second region having a second fin width, which is an initial fin width, between the first regions 52a. 52b).

Referring to FIG. 7A, the mask pattern 53 and the sacrificial oxide film 54 are removed. As a result, a first region 52a having a first fin width is formed on both sides of the fin from which the sacrificial oxide film has been removed, and a second region having a second fin width, which is an initial fin width, between the first regions 52a. 52b is formed.

FIG. 7B illustrates a cross-sectional view of the fin formed on the SOI substrate, in which the fin 52 extending vertically on the buried insulating film 51 on the support substrate 50 is located. In contrast, referring to FIG. 7C, the fin 52 formed on the bulk substrate is vertically connected to the substrate.

When formed on the SOI substrate, the fins are separated from each other on the insulating film 51, but in the bulk substrate, the fins are connected to each other by the substrate. Therefore, when forming a fin field effect transistor using a bulk substrate, as shown in FIG. 7D, an isolation layer 55 may be further formed between the fins to isolate the fins. Although not shown in the drawings, a conventional gate process or a damascene gate process may be applied to form a gate electrode crossing the upper portion of the fins.

Another method of isolating the fins formed on the bulk substrate is described.

8A and 8B, after forming the fin having the first region and the second region, the liner layer 56 is conformally formed on the entire surface of the substrate on which the fin 52 is formed. The liner layer 56 may be formed of a film having an etch selectivity with respect to the fin 52. For example, the liner layer 56 may be formed of a silicon nitride layer. Subsequently, an insulating film 58 is formed on the entire surface of the substrate on which the liner film 56 is formed. The insulating film 58 is a film having an etch selectivity with respect to the liner film 56 and the substrate. For example, the insulating film 58 is formed of an oxide film having excellent gap-fill efficiency such as a PECVD film, an HDPCVD film, or an O ₃ -TEOS. can do.

9A and 9B, the insulating film 58 is recessed to expose the liner film 56. The exposed liner layer 56 is recessed to expose a portion of the sidewall of the fin 52. A device isolation film made of an insulating film 58 and a liner film 56 recessed in a region between the pins 52 extending vertically on the substrate is formed to isolate each pin. Impurities may be injected into the fins 52 to form a channel diffusion layer. The impurity implantation may be implanted by a gradient ion implantation method. The channel diffusion layer may be formed at a concentration of 10 ¹⁵ atoms / cm 3 to 10 ¹⁹ atoms / cm 3 by injecting boron or boron fluoride in a dose of 10 ¹¹ atoms / cm 2 to 10 ¹⁴ atoms / cm 2. Impurities may be further injected perpendicularly to the fin by adjusting a projection depth Rp below the exposed portion of the fin. As a result, the impurity diffused from the channel diffusion layer and the impurity injected vertically may be overlapped to further form a high punch-through prevention diffusion layer. The punchthrough prevention diffusion layer prevents the occurrence of punchthrough through the channel diffusion layer that is difficult to control by the gate.

The channel diffusion layer and the punch-through prevention diffusion layer may be formed after the fin of FIG. 5 is formed, or may be formed in the step shown in FIG. 7D where a portion of the sidewall of the fin is recessed and an isolation layer is formed. In the case where the fin is formed in the SOI substrate, punch through generation is prevented by the lower insulating film, so that the punch through prevention diffusion layer may not be formed.

9A and 9B, a gate insulating film is formed on sidewalls of the exposed fins 52. The gate insulating layer 59 may be formed of a metal oxide film, a silicon oxide film, or a silicon oxy nitride film, and may be formed by a thermal oxidation method or a CVD method. A conductive film is formed on the entire surface of the substrate on which the gate insulating film 59 is formed, and the conductive film is patterned to form a gate electrode 60 crossing the upper portion of the fin 52. As shown, since the device isolation layer is positioned between the fins, the width of the gap region is narrower than that of FIG. 7D. Therefore, the conductive layer may have a flat upper surface. The gate electrode may be formed by applying a damascene process. That is, forming a mold film covering the entire surface of the fin, patterning the mold film to form an opening for exposing the fin, forming a gate insulating film on the exposed fin surface, and then filling a conductive film in the opening to form a gate electrode. It may be.

The gate electrode 60 is formed to overlap an upper portion of a boundary between the first region 52a and the second region 52b of the fin. An impurity is implanted into the fin 52 by using the gate electrode 60 as an ion implantation mask to form a source region 62s and a drain region 62d.

10A and 10B are plan views for explaining a modification of the first embodiment.

10A and 10B, even if the widths of the gate electrodes 110 are the same, the threshold voltage may be adjusted according to the overlapping form of the gate electrodes 110 and the pins 100. That is, when the gate electrode 110 overlaps the first region 112a more than the second region 112b, the threshold voltage of the transistor will be lowered, and the second region will be lower than the first region 112a. If more overlapped with 112b, the threshold voltage of the transistor will be high.

11 is a plan view illustrating a fin field effect transistor according to a second exemplary embodiment of the present invention.

This transistor has a vertically stretched fin 200, similar to the first embodiment shown in FIG. The fin 200 includes a first region having a first fin width and a second region having a second fin width wider than the first fin width. The gate electrode 210 crosses the upper portion of the fin 200 while surrounding the fin 200. A gate insulating layer 208 is interposed between the gate electrode 210 and the fin 200. Source and drain regions 202s and 202d are formed in the fins on both sides of the gate electrode 210, respectively. The source region 202s is formed in a narrow first region, and the drain region 202d is formed in a wide second region. The channel region 201 of the transistor is defined at a portion overlapping the gate electrode 210, that is, a fin between the source region 202s and the drain region 202d. Thus, the channel region 201 is also formed over the first region and the second region. In the channel region adjacent to the drain region 202d, an impurity diffusion layer 204 having a higher doping concentration than the other channel region 201 is formed. The impurity diffusion layer 204 has a different conductivity type from the source region 202s and the drain region 202d.

12A and 12B are graphs showing doping concentrations and energy bands according to positions along II-II ′ of FIG. 11, respectively.

In the figure, region ① represents a source region, region ② represents a channel region, region ③ represents a channel region adjacent to the drain region, and region ④ represents a drain region.

In the fin field effect transistor according to the present invention, as shown, the doping concentration of the source region ① and the drain region ④ is high, and the doping concentration of the channel region ② is relatively very low. When applied to a DRAM cell transistor, the channel region ② may have a general p well concentration or p substrate concentration, and the channel region ③ adjacent to the drain region may include boron or boron fluoride in the p well or p substrate. P-type impurities, such as, are further implanted and doped to higher concentrations. The source region ① and the drain region ④ are doped with n-type impurities such as phosphorus (P) or arsenic (As).

As shown in FIG. 12B, a potential barrier φ _d is formed between the channel region and the drain region because the impurity concentration of the channel region ③ adjacent to the drain region is higher than that of the channel region ② adjacent to the source region. do. This potential barrier φ _d provides a very useful property for the fin field effect transistor of the present invention.

13A and 13B are graphs illustrating an energy band model in operation of a fin field effect transistor according to a second exemplary embodiment of the present invention.

FIG. 13A illustrates a state where charge is stored in a storage capacitor in a memory cell in which a storage capacitor is connected to the source region 202s and a bit line is connected to the drain region 202d. At this time, the impurity diffusion layer 204 forms a potential barrier φ _d in the channel region ③ adjacent to the drain region 202d. Therefore, in the transistor off state, the potential barrier φ _d suppresses the flow of electrons flowing from the drain region ④ to reduce the transistor off leakage.

13B illustrates a transistor on state in which Vcc is applied to the drain region 202d through the bit line of the memory cell. In the transistor-on state, since the potential barrier φ _d is located near the drain region having a high potential, the peak of the potential barrier φ _d is located at a level lower by φ _p than the channel on the source side. It hardly affects the flow of electrons flowing from the region ① to the drain region ④. Therefore, this transistor has a low threshold voltage depending on the channel region (2) adjacent to the source region.

As described above, the fin field effect transistor according to the second embodiment shows a transistor characteristic having a high threshold voltage in an off state and thus shows low off leakage, and a transistor characteristic having a low threshold voltage in an on state and thus shows a low transistor on current. Indicates. In addition, since the doping concentration of the channel region adjacent to the source region is low, the junction leakage between the source region and the channel can be suppressed.

In FIG. 11, a boundary region of the first region and the second region is illustrated to overlap the gate electrode 210. However, the fin field effect transistor according to the present invention may be formed in a tapered fin whose width decreases from the drain region 302d to the source region 302s as shown in FIG. 14A, and is illustrated in FIG. 14B. As described above, the width of the channel portion is constant and may be formed in the fin having a structure extending in the source region 212s and the drain region 312d, respectively, and having a large area of the drain region 312d. have.

15 is a perspective view showing a modification of the second embodiment of the present invention.

Referring to FIG. 15, the width of the channel region of the fin field effect transistor according to the present invention may be extended below the gate electrode, but the width of the fin may gradually increase from the source region to the drain region.

As shown in the drawing, a fin 300 protruding vertically is formed on the substrate, and a gate electrode 310 covering the sidewalls and the upper surface of the fin 300 crosses the upper portion of the fin 300. A gate insulating layer 308 is interposed between the gate electrode 310 and the fin 300. Source and drain regions 302s and 302d are formed in the fins on both sides of the gate electrode 310, respectively. The fin 300 gradually increases in width from the source region 302s to the drain region 302d. Therefore, the area of the source region 302s is small, so that the junction leakage can be reduced and the area of the drain region 302d can be relatively increased to obtain the transistor on-current increase effect.

The channel region 301 is defined by a fin between the source region 302s and the drain region 302d, that is, a fin under the gate electrode 310. The impurity concentration of the channel region adjacent to the drain region 302d is higher than the impurity concentration of the channel region adjacent to the source region 302s. Although the impurity concentration of the channel region 301 is lowered to increase the transistor on current, the source region 302s from the drain region 302d by the high impurity concentration diffusion layer 304 adjacent to the drain region 302d. The flow of electrons toward) can be suppressed. Accordingly, the channel region 301 may maintain an initial well concentration or a substrate concentration without additionally forming a channel diffusion layer.

16A to 16D are diagrams for describing a method of manufacturing the fin field effect transistor according to the second embodiment of the present invention.

Referring to FIG. 16A, fins 300 protruding perpendicular to the semiconductor substrate are formed. As in the first embodiment, the fin 300 may be formed by etching the semiconductor bulk substrate so as to be defined by an isolation layer, or by forming a silicon layer of the SOI substrate in an isolated structure on the buried oxide layer. . The pin 300 may have a tapered shape that gradually decreases in width, or may be formed in a shape divided into a narrow first region and a wide second region as shown in FIG. 11. . In addition, as shown in FIG. 14A, an asymmetric taper shape or a center portion as shown in FIG. 14B may have a narrow width and an extended area of different width on both sides.

Referring to FIG. 16B, a gate insulating film 308 conformally covering the fin 300 is formed, and a gate electrode 310 surrounding the sidewall and the top surface of the fin 300 is formed. By forming a thick insulating layer on the upper surface of the fin 300, a thick insulating layer may be interposed between the gate electrode 310 and the upper surface of the fin 300. When the gate electrode 310 surrounds the sidewalls and the upper surface of the fin, a channel of the transistor will be formed on three sides of the fin, and a thick insulating film is formed between the gate electrode 310 and the upper surface of the fin 300. When interposed, the channel of the transistor will be formed on both sidewalls of the fin.

Referring to FIG. 16C, a first conductive type diffusion layer 303 is formed by implanting impurities of a first conductivity type into the fin 300 of one layer of the gate electrode 310. The impurity of the first conductivity type is implanted into a wide portion of a fin, that is, a region where a drain of a transistor is formed (a region where bit lines are connected in a DRAM cell array). The impurity of the first conductivity type has the same conductivity type as that of the initial impurities of the fin. For example, in a DRAM device in which an nMOS transistor is adopted, the fin may be formed in a p-type substrate or p-type well, and the first conductivity type impurity may be p-type boron or boron fluoride. The first conductivity type diffusion layer 303 may be laterally diffused below the gate electrode by a predetermined distance.

Referring to FIG. 16D, an impurity of a second conductivity type is implanted into the fin 300 using the gate electrode 310 as an ion implantation mask. As a result, source regions 302s and drain regions 302d are formed in the fins on both sides of the gate electrode 310. The source region 302s is formed in the narrow portion of the fin, and the drain region 302d is formed in the wide portion of the fin. The second conductivity type impurity may be phosphorus or arsenic. The second conductivity type impurity thresholds the conductivity type of the first conductivity type diffusion layer 303 to form the drain region 302d. Since the lateral diffusion distance of the first conductivity type impurity is longer than the lateral diffusion distance of the second conductivity type impurity, the first conductivity type diffusion layer 304 may exist in the fin adjacent to the drain region 302d. That is, in the channel region 301 defined by the source region 302s and the drain region 302d, a portion adjacent to the drain region 302d may exhibit a higher impurity concentration than other regions. The formation timing of the first conductivity type diffusion layer and the second conductivity type diffusion layer may be replaced with each other. In addition, the diffusion distance may be adjusted by exposing the first conductivity type diffusion layer to more heat treatment processes than the second conductivity type diffusion layer.

The second embodiment of the present invention may be applied to the DRAM cell array forming process as in the first embodiment described above. As described with reference to FIGS. 9A and 9B, an isolation layer is formed to isolate the fins. However, even if the channel diffusion layer is not formed or formed, it is formed by implanting at a lower dose than in the first embodiment. The punch-through preventing diffusion layer may be formed at the bottom of the fin by appropriately adjusting the projection rage. Subsequently, a pair of gate electrodes (gate electrode pairs) crossing the upper portion of the fin 300 are formed, and a first conductivity type impurity is injected into the fin between the gate electrodes 310 to form a first conductivity type. The diffusion layer is formed. Subsequently, impurities are implanted into the fin 300 using the gate electrodes 310 as an ion implantation mask to form a common drain region 302d in the fin between the gate electrodes 310, and the common The DRAM cell array may be configured by forming source regions 302s on the fins on both sides of the drain region 302d. Subsequently, a bit line is connected to the common drain region 302d in a usual manner, and a storage capacitor is connected to the source region 302s, respectively.

As described above, the fin field effect transistor according to the present invention includes a fin composed of a narrow first region and a wide second region, and forms a source region in the narrow first region of the fin to form a source region. The leakage current can be suppressed. When the width of the pin is narrow, the threshold voltage control capability according to the process variable is lowered, so that not only the first region but also the wide second region may be connected to the gate electrode, thereby increasing the threshold voltage and improving the threshold voltage control capability.

Therefore, the transistor of the present invention can be applied to transistors of memory devices such as DRAM devices because of low source leakage current and excellent threshold voltage control capability. When applied to DRAM devices, the data retention time can be extended to reduce power consumption.

In addition, by forming the impurity concentration in the channel region adjacent to the drain region higher than the impurity concentration in the channel region on the source region, the transistor characteristics having a high threshold voltage in the off state are exhibited, resulting in low off leakage and a low threshold voltage in the on state. It is possible to provide a fin field effect transistor exhibiting transistor characteristics showing low transistor on current. Furthermore, since the doping concentration of the channel region adjacent to the source region is low, the junction leakage between the source region and the channel can also be suppressed.

Claims (21)

A pin extending vertically on the substrate; A gate electrode surrounding the fin and crossing the upper portion of the fin; A gate insulating film interposed between the gate electrode and the fin; and A source region and a drain region respectively formed in the fins on both sides of the gate electrode, And a fin width widened between the source region and the drain region under the gate electrode. The method of claim 1, The fin has a 'T' shaped plane consisting of a first region having a first fin width and a second region having a second fin width wider than the first fin width, The source region is formed in the first region, And the drain region is formed in the second region. The method of claim 2, A boundary region between the first region and the second region overlaps the gate electrode. A pin extending vertically on the substrate; A gate electrode surrounding the fin and crossing the upper portion of the fin; A gate insulating layer interposed between the gate electrode and the fin; Source and drain regions respectively formed in the fins on both sides of the gate electrode; and A channel region formed in the fin between the source region and the drain region, The fin width of the drain region is wider than the fin width of the source region, and the impurity concentration of the channel region adjacent to the drain region is higher than the impurity concentration of the channel region adjacent to the source region. The method of claim 4, wherein The fin has a 'T' shaped planar shape consisting of a first region having a first fin width and a second region having a second fin width wider than the first fin width, A boundary region between the first region and the second region overlaps the lower portion of the gate electrode. The method of claim 4, wherein And the fin has a taper shape that gradually decreases in width from the drain region to the source region. The method of claim 4, wherein And the channel region has a substrate concentration, and the channel region adjacent to the drain region is doped higher than the substrate concentration. A pin extending vertically on the substrate; A gate electrode pair surrounding the fin and crossing the upper portion of the fin; A gate insulating layer interposed between the gate electrodes and the fin; A common drain region formed in the fin between the gate electrodes; and A source region formed in each of the fins on both sides of the gate electrode pair, And the width of the fin is widened between the source region and the common drain region below each gate electrode. The method of claim 8, The fin is comprised of a pair of first regions having a first fin width and a second region located between the first region and having a second fin width that is wider than the first fin width, The source region is formed in the first region, And the common drain region is formed in the second region. The method of claim 9, The boundary region between the first region and the second region overlaps the gate electrode. A pin extending vertically on the substrate; A gate electrode pair surrounding the fin and crossing the upper portion of the fin; A gate insulating layer interposed between the gate electrodes and the fin; A common drain region formed in the fin between the gate electrodes; Source regions respectively formed in the fins on both sides of the gate electrode pair; and A channel region formed in each of the fin between the common drain region and the source region, The fin width of the common drain region is wider than the fin width of the source region, and the impurity concentration of the channel region adjacent to the common drain region is higher than the impurity concentration of the channel region adjacent to the source region. The method of claim 11, The fin has a 'T' shaped planar shape consisting of a first region having a first fin width and a second region having a second fin width wider than the first fin width, A boundary region between the first region and the second region overlaps the lower portion of the gate electrode. The method of claim 12, And the fin has a taper shape that gradually decreases in width from the drain region to the source region. The method of claim 11, And the channel region has a substrate concentration, and the channel region adjacent to the drain region is doped higher than the substrate concentration. Forming a fin vertically extending over the substrate, the fin including a first region having a first fin width and a second region having a second fin width wider than the first fin width; Conformally forming a gate insulating film on at least sidewalls of the fins; and A fin electrode effect is formed on the gate insulating layer to cross the upper portion of the fin and surround the fin, wherein the gate electrode overlaps an upper portion of a boundary between the first region and the second region. Method for manufacturing a transistor. The method of claim 15, Forming the pins, Patterning the semiconductor substrate to form a vertically elongated fin having a second fin width; Forming a mask pattern covering a portion of the fin; Forming a sacrificial oxide film by oxidizing the sidewall of the fin using the mask pattern as an anti-oxidation film; Removing the sacrificial oxide layer to form a first region having a first fin width; and Removing the mask pattern to expose a second region having the second fin width. The method of claim 15, The substrate is a substrate on which a supporting substrate, a buried insulating film and a semiconductor layer are stacked. And the fins are formed by patterning the semiconductor layer. The method of claim 15, The substrate is a semiconductor substrate, Wherein the fin is formed by patterning the semiconductor substrate, and after the fin is formed, an isolation layer is formed on the semiconductor substrate to isolate the fin. The method of claim 18, Forming the device isolation film, Conformally forming a liner layer on the front surface of the fin-formed substrate; Forming an insulating film on an entire surface of the substrate on which the liner layer is formed; Recessing the insulating film to expose the liner layer; and Recessing the liner layer to expose a portion of the sidewalls of the fins. Forming a fin vertically extending over the substrate, the fin including a first region having a first fin width and a second region having a second fin width wider than the first fin width; Conformally forming a gate insulating film on at least sidewalls of the fins; and Forming a gate electrode on the gate insulating layer to cross the upper portion of the fin and surround the fin; Implanting a first conductivity type impurity into the fin on one side of the gate electrode; By using the gate electrode as an ion implantation mask, a second conductivity type impurity is implanted into the fin to form a source region and a drain region in the first region and the second region, respectively, defining a channel region under the gate electrode. And forming a first conductivity type diffusion layer in a channel region adjacent to the drain region. The method of claim 20, And injecting the second conductivity type impurity, the lateral diffusion distance of the second conductivity type impurity is shorter than the lateral diffusion distance of the second conductivity type impurity.

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