KR100511000B1 - Method for fabricating of semiconductor device - Google Patents
Method for fabricating of semiconductor device Download PDFInfo
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- KR100511000B1 KR100511000B1 KR10-2002-0086002A KR20020086002A KR100511000B1 KR 100511000 B1 KR100511000 B1 KR 100511000B1 KR 20020086002 A KR20020086002 A KR 20020086002A KR 100511000 B1 KR100511000 B1 KR 100511000B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 ISO 마스크를 이분화하여 갭필 마진을 확보하고 스토리지 노드 액티브를 에피택셜 성장시켜 소자 누설 전류 특성을 향상시킬 수 있도록한 반도체 소0자의 제조 방법에 관한 것으로, 제 1 ISO 마스크를 이용하여 ISO 필드 산화막을 형성하고 폴리 실리콘층을 필드 산화막내에 매립하는 단계;제 2 ISO 마스크를 이용하여 스토리지 노드 형성부 필드 산화막을 식각한후에 ISO 측벽에 사이드 월 스페이서를 만들고 상기 폴리 실리콘층을 노출시키는 단계;상기 폴리 실리콘층을 씨드(seed)로 이용하여 에피택셜 성장 공정을 진행하여 액티브층을 형성하는 단계;전면에 게이트 형성용 물질층을 형성하고 선택적으로 패터닝하여 게이트 전극을 형성한 후에 LDD 접합 영역을 형성하는 단계;상기 게이트 전극의 측면에 게이트 스페이서를 형성하고 소오스/드레인 이온 주입을 진행하는 단계를 포함한다.The present invention relates to a method for fabricating a semiconductor element, which is capable of dividing an ISO mask to secure a gap fill margin and to epitaxially grow a storage node active to improve device leakage current characteristics. Forming a field oxide layer and embedding the polysilicon layer in the field oxide layer; after etching the storage node forming field oxide layer using a second ISO mask, forming a sidewall spacer on an ISO sidewall and exposing the polysilicon layer; Forming an active layer by epitaxial growth using a polysilicon layer as a seed; forming a gate electrode material layer on the front surface and selectively patterning the gate electrode to form an LDD junction region Forming a gate spacer on a side of the gate electrode and source / drain Proceeding with ion implantation.
Description
본 발명은 반도체 소자의 제조에 관한 것으로, 구체적으로 ISO 마스크를 이분화하여 갭필 마진을 확보하고 스토리지 노드 액티브를 에피택셜 성장시켜 소자 누설 전류 특성을 향상시킬 수 있도록한 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the fabrication of semiconductor devices, and more particularly, to a method of fabricating semiconductor devices in which an ISO mask is divided into two parts to secure a gap fill margin and epitaxially grow storage node active to improve device leakage current characteristics. .
일반적으로 MOS 트랜지스터를 형성하기 위하여 실리콘 기판상에 웰(Well)을 형성한 후 이온 주입 공정으로 소오스 및 드레인을 형성한다.In general, a well is formed on a silicon substrate to form a MOS transistor, and then a source and a drain are formed by an ion implantation process.
이때 소자 동작시 드레인에 전압을 인가하고 게이트 on 상태에 두면 드레인에서 소오스로 전류가 흐르게 된다. 반면 게이트를 off 상태에 두면 드레인에서 소오스로 흐르는 전류가 없어져야 하는데 드레인에 전압이 증가할 경우 원하지 않는 전류가 소오스로 흐르게 된다.At this time, when a voltage is applied to the drain while the device is in operation and the gate is turned on, current flows from the drain to the source. On the other hand, when the gate is off, the current flowing from the drain to the source must be eliminated. If the voltage is increased in the drain, unwanted current flows into the source.
상기 전류를 펀치 스루(Punch through) 전류라고 한다. 펀치 스루 전류는 디플리션(Depletion)층으로 캐리어가 인가되어 디플리션층의 바이어스에 캐리어가 이끌려 전류가 흐르게 되기 때문이다. This current is referred to as punch through current. The punch-through current is because a carrier is applied to the depletion layer so that the carrier is led to the bias of the depletion layer so that the current flows.
펀치 스루 현상은 게이트의 길이가 좁아질 수록 더욱 증가하며 소자 기술에 한계를 가져온다. 또한, 반도체 소자가 고집적화 함에 따라 생기는 셀(Cell) 영역과 주변영역의 높은 단차로 인하여 평탄화를 위한 후속 공정에 문제가 발생한다.The punch-through phenomenon increases as the gate length gets narrower, limiting device technology. In addition, there is a problem in the subsequent process for planarization due to the high level difference between the cell region and the peripheral region caused by the high integration of the semiconductor device.
도 1은 종래 기술의 반도체 소자의 레이 아웃 구성 및 ISO 마스크의 구성도로서 (1)은 게이트 마스크이고, (2)는 하나로 구성된 ISO 마스크이다.1 is a schematic diagram of a layout configuration and an ISO mask of a semiconductor device of the prior art, in which (1) is a gate mask and (2) is an ISO mask composed of one.
그러나 이와 같은 종래 기술의 반도체 소자의 제조 공정은 다음과 같은 문제점이 있다.However, the manufacturing process of such a semiconductor device of the prior art has the following problems.
종래 기술에서는 DRAM MOS 셀 트랜지스터 제조 공정 시 디자인 룰 감소에 따라 ISO 갭 필 마진이 부족하며, 셀 콘택 형성시도 영역 확보가 어려워 콘택 Rc 증가에 따른 셀 구동력이 부족하다.In the prior art, an ISO gap fill margin is insufficient due to a reduction in design rules in a DRAM MOS cell transistor manufacturing process, and a cell driving force due to an increase in contact Rc is insufficient due to difficulty in securing a cell contact formation area.
또한, 트랜지스터 게이트 CD 감소에 따라 셀 펀치스루 특성 취약해지며 이를 개선하기 위해 채널 도즈의 증가시에 접합부의 전계(electric field) 증가에 따른 tREF 특성의 확보가 어렵다.In addition, the cell punch-through characteristic becomes weak as the transistor gate CD decreases, and in order to improve this, it is difficult to secure the tREF characteristic due to the increase in the electric field of the junction when the channel dose is increased.
본 발명은 이와 같은 종래 기술의 의 문제를 해결하기 위하여 안출한 것으로, ISO 마스크를 이분화하여 갭필 마진을 확보하고 스토리지 노드 액티브를 에피택셜 성장시켜 소자 누설 전류 특성을 향상시킬 수 있도록한 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art. The semiconductor device has been designed to provide a gap fill margin by dividing an ISO mask and to epitaxially grow a storage node active to improve device leakage current characteristics. It is an object to provide a manufacturing method.
이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조 방법은 제 1 ISO 마스크를 이용하여 ISO 필드 산화막을 형성하고 폴리 실리콘층을 필드 산화막내에 매립하는 단계;제 2 ISO 마스크를 이용하여 스토리지 노드 형성부 필드 산화막을 식각한후에 ISO 측벽에 사이드 월 스페이서를 만들고 상기 폴리 실리콘층을 노출시키는 단계;상기 폴리 실리콘층을 씨드(seed)로 이용하여 에피택셜 성장 공정을 진행하여 액티브층을 형성하는 단계;전면에 게이트 형성용 물질층을 형성하고 선택적으로 패터닝하여 게이트 전극을 형성한 후에 LDD 접합 영역을 형성하는 단계;상기 게이트 전극의 측면에 게이트 스페이서를 형성하고 소오스/드레인 이온 주입을 진행하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming an ISO field oxide layer using a first ISO mask and embedding a polysilicon layer in the field oxide layer; a storage node using a second ISO mask Forming a sidewall spacer on an ISO sidewall and etching the polysilicon layer after etching the formation field oxide layer; forming an active layer by performing an epitaxial growth process using the polysilicon layer as a seed; Forming an LDD junction region after forming a gate electrode material layer on the front surface and selectively patterning the gate electrode; forming a LDD junction region; and forming a gate spacer on the side of the gate electrode and performing source / drain ion implantation Characterized in that.
본 발명에 따른 반도체 소자의 제조 방법의 바람직한 실시예에 관하여 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.A preferred embodiment of the method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 따른 반도체 소자의 레이 아웃 구성 및 ISO 마스크의 구성도이고, 도 3a내지 도 3e는 본 발명에 따른 반도체 소자의 제조를 위한 공정 단면도이다.2 is a layout view of a semiconductor device and an ISO mask of the semiconductor device according to the present invention, and FIGS. 3A to 3E are cross-sectional views illustrating a process of manufacturing the semiconductor device according to the present invention.
본 발명은 DRAM 셀 제조시 ISO 마스크를 이분화하여 ISO 갭 필 마진(gap fill margin)을 확보하면서 갭 필 이후 스토리지 노드(storage node) 액티브를 에피택셜 성장시킴에 따라 스토리지 노드부 액티브를 크게 정의할 수 있도록한 것이다.The present invention can largely define the storage node active by dividing the ISO mask during DRAM cell manufacturing to secure the ISO gap fill margin and epitaxially growing the storage node active after the gap fill. To be.
또한, 스토리지 노드 접합 형성부가 필드 산화막으로 채널부와 격리 되므로써 셀 펀치 누설도 개선할 수 있도록 한다.In addition, the storage node junction forming portion is isolated from the channel portion by the field oxide layer, thereby improving cell punch leakage.
본 발명은 도 2에서와 같이, ISO 마스크를 두 개로 분리하여 구성하는 것으로, 도 2에서 (11)은 게이트 마스크이고, (12)는 제 1 ISO 마스크이고, (13)은 제 2 ISO 마스크이다.In the present invention, as shown in FIG. 2, the ISO mask is divided into two parts. In FIG. 2, (11) is a gate mask, (12) is a first ISO mask, and (13) is a second ISO mask. .
제 2 ISO 마스크(13)는 스토리지 노드 형성 부분이다.The second ISO mask 13 is a storage node forming part.
제조 공정은 먼저, 도 3a에서와 같이, 제 1 ISO 마스크(31)를 이용하여 ISO 필드 산화막(32)을 형성하고, p 타입의 폴리 실리콘층(33)을 CMP(Chemical Mechanical Polishing) 공정 및 에치백 공정으로 필드 산화막(32)내에 매립 형성한다.First, as in FIG. 3A, an ISO field oxide film 32 is formed by using the first ISO mask 31, and the p-type polysilicon layer 33 is subjected to a chemical mechanical polishing (CMP) process and a process. A buried process is formed in the field oxide film 32.
도 3b에서와 같이, 제 2 ISO 마스크(34)를 이용하여 스토리지 노드 형성부 필드 산화막을 드러낸 후 습식각(wet etch)을 이용하여 액티브가 드러나도록 한 후 건식각(dry etch)을 이용하여 ISO 측벽에 사이드 월 스페이서(35)를 만들고 p 타입 폴리 실리콘층(33)이 노출되도록 한다.As shown in FIG. 3B, the storage node forming field oxide layer is exposed using the second ISO mask 34, and the active is exposed using wet etch, and then ISO is dried. Side wall spacers 35 are formed on the sidewalls and the p-type polysilicon layer 33 is exposed.
그리고 도 3c에서와 같이, 노출된 p 타입 폴리 실리콘층(33)을 씨드(seed)로 이용하여 에피택셜 성장 공정을 진행하여 액티브층(36)을 형성하고 제 2 ISO 마스크를 제거하고 평탄화 공정을 진행한다.As shown in FIG. 3C, an epitaxial growth process is performed using the exposed p-type polysilicon layer 33 as a seed to form the active layer 36, and the second ISO mask is removed and the planarization process is performed. Proceed.
이어, 도 3d에서와 같이, 게이트 형성용 물질층을 형성하고 선택적으로 패터닝하여 게이트 전극(37)을 형성한 후에 LDD 접합 영역(38)을 형성한다.3D, the LDD junction region 38 is formed after forming the gate forming material layer and selectively patterning the gate electrode 37 as shown in FIG. 3D.
그리고 도 3e에서와 같이, 게이트 전극(37)의 측면에 게이트 스페이서(39)를 형성하고 소오스/드레인 이온 주입을 진행한다.3E, the gate spacer 39 is formed on the side of the gate electrode 37 and source / drain ion implantation is performed.
이와 같은 본 발명은 DRAM 셀 트랜지스터 제조시 ISO 마스크를 이분화하여 ISO 장축 CD를 줄임으로써 ISO 갭 필(Gap fill) 마진을 확보할 수 있다.The present invention can secure the ISO gap fill margin by dividing the ISO mask by dividing the ISO mask in the manufacture of DRAM cell transistors.
또한, ISO 필드 산화막의 하부에 p 타입 폴리 실리콘을 매립한 후 스토리지 노드 접합에만 백 바이어스를 차별화하여 인가함으로써 비트 라인 커패시터 증가없이 백 바이어스 감소를 통한 접합 전계를 감소시키는 것이 가능하도록 한다.In addition, by embedding p-type polysilicon under the ISO field oxide layer, the back bias is differentiated and applied only to the storage node junction, thereby reducing the junction electric field through reducing the back bias without increasing the bit line capacitor.
이상 설명한 내용을 통해 당업자라면 본 발명의 기술 사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.
따라서, 본 발명의 기술적 범위는 실시예에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의하여 정해져야 한다.Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.
이상에서 설명한 본 발명에 따른 반도체 소자의 제조 방법은 다음과 같은 효과가 있다.The method of manufacturing a semiconductor device according to the present invention described above has the following effects.
첫째, 셀 트랜지스터 제조시에 ISO 마스크를 이분화하여 ISO 장축 CD를 줄임으로써 ISO 캡 필 마진(gap fill margin)을 확보할 수 있는 효과가 있다.First, when manufacturing a cell transistor, it is possible to secure an ISO cap fill margin by dividing an ISO mask to reduce the ISO long-axis CD.
둘째, 갭 필 이후 스토리지 노드(storage node) 액티브를 에피택셜 성장시킴에 따라 스토리지 노드부 액티브를 크게 정의할 수 있다.Second, as the storage node active is epitaxially grown after the gap fill, the storage node unit active may be largely defined.
셋째, 스토리지 노드 접합 형성부가 필드 산화막으로 채널부와 격리되므로써 셀 펀치스루 특성을 개선할 수 있다.Third, the cell punch-through characteristics can be improved by separating the storage node junction forming portion from the channel portion by the field oxide layer.
넷째, 스토리지 노드 접합에만 백 바이어스(back bias)를 차별화하여 조절함으로써 비트라인 커패시터 증가없이 백 바이어스 감소를 통한 접합 전계의 감소가 가능하다.Fourth, by differentiating and adjusting the back bias only to the storage node junction, it is possible to reduce the junction electric field by reducing the back bias without increasing the bit line capacitor.
도 1은 종래 기술의 반도체 소자의 레이 아웃 구성 및 ISO 마스크의 구성도1 is a layout diagram and a configuration diagram of an ISO mask of a semiconductor device of the prior art
도 2는 본 발명에 따른 반도체 소자의 레이 아웃 구성 및 ISO 마스크의 구성도2 is a layout view and a configuration diagram of an ISO mask of a semiconductor device according to the present invention.
도 3a내지 도 3e는 본 발명에 따른 반도체 소자의 제조를 위한 공정 단면도3A to 3E are cross-sectional views for manufacturing a semiconductor device according to the present invention.
- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-
31. 제 1 ISO 마스크 32. 필드 산화막31. First ISO Mask 32. Field Oxide
33. 폴리 실리콘층 34. 제 2 ISO 마스크33. Polysilicon Layer 34. Second ISO Mask
35. 사이드월 스페이서 36. 액티브층35. Sidewall spacers 36. Active layer
37. 게이트 전극 38. LDD 접합 영역37.Gate electrode 38.LDD junction region
39. 게이트 스페이서39. Gate spacer
Claims (4)
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