TW202218112A - Transistor structure - Google Patents

Abstract

A transistor structure includes a gate, a spacer, a channel region, a first concave, and a first conductive region. The gate is above a silicon surface. The spacer is above the silicon surface and at least covers a sidewall of the gate. The channel region is under the silicon surface. The first conductive region is at least partially formed in the first concave, wherein a conductive region of a neighborhood transistor structure next to the transistor structure is at least partially formed in the first concave.

Description

transistor structure

The present invention relates to a transistor structure, especially a transistor structure with low leakage current.

In the prior art, one of the most commonly used transistors is a metal-oxide-semiconductor field-effect transistor (MOSFET) formed in a planar silicon wafer, wherein the transistor has A gate is formed on a silicon surface, and the gate and the silicon surface are separated by a dielectric material. In addition, the drain and source of the transistor are formed in the substrate under the silicon surface. As the size of the transistor shrinks, the transistor can utilize a fin structure transistor such as a fin field effect transistor (FinFET), a tri-gate FET, or a double-gate ) transistor, etc.) so that the size of the transistor can continue to shrink from 22 nm to 7 nm, or to a size smaller than 7 nm. However, most techniques of the fin structure transistor emphasize the current driving capability of the transistor to exhibit the high performance of the transistor by generating a high ON current, rather than emphasizing that the transistor has a low leakage current ability to exhibit the low OFF current of the transistor. But for deep nano-silicon technology, the importance of utilizing the fin-structured transistor as a low-leakage and low-power device is increasing, especially when the fin-structured transistor is used in memory circuits (eg static random access memories (SRAMs), dynamic random access memories (DRAMs), portable integrated circuits (ICs) or wearable integrated circuits when switching elements in circuits, etc.).

For example, the memory cell most commonly used in dynamic random access memory has an access transistor and a storage capacitor. However, when the prior art uses a planar transistor or the fin-structured transistor as the access transistor, the access transistor suffers from high leakage current in the OFF state (eg each memory cell exceeds 1 pA), where the signal stored in the DRAM leaks rapidly due to the high leakage current problem, resulting in the DRAM requiring a very short refresh time to restore all stored signal (otherwise the stored signal would be lost), so the problem of high leakage current is unacceptable. In addition, there are various known sources of leakage current in the off state of the access transistor, such as (a) gate-to-channel leakage, (b) gate induced drain Gate-Induced Drain Leakage (GIDL), (c) Drain-induced barrier lowering (DIBL) leakage current, (d) Sub-threshold channel leakage (Sub-threshold channel leakage) ), (e) leakage currents in source/drain sidewalls or regions caused by p-n junctions in silicon materials, etc. In order for the off current of each element to meet a level close to femto-ampere, the parameters of the transistor size of the inner part of each element must be relaxed to an unacceptable level, which violates the scaling theory of transistors, In order to realize the economy of Moore's Law, the scaling theory of the transistor requires to reduce the size of the transistor to reduce the size of the memory cell. In an exaggerated example, for a 10nm process technology, the gate length needs to be greater than 100nm to reduce the off current to meet the requirement of 1 femtoamp per memory cell, however this is not practical. Therefore, how to provide transistors with low leakage current is an important issue for designers of the DRAM.

An embodiment of the present invention discloses a transistor structure. The transistor structure includes a gate electrode, a spacer layer, a channel region, a first groove, and a first conductive region. The gate is located above a silicon surface. The spacer layer is located above the silicon surface and covers at least one sidewall of the gate electrode. The channel region is below the silicon surface. The first conductive region is formed at least partially within the first recess, wherein the conductive region of an adjacent transistor structure next to the transistor structure is formed at least partially within the first recess.

In another embodiment of the present invention, the transistor structure further includes a second groove and a second conductive region. The second conductive region is formed at least partially within the second recess. The first conductive region has a first doping concentration profile along a first extension direction, and the second conductive region has a second doping concentration profile along a second extension direction, wherein the first extension The direction and the second extending direction are parallel to the normal direction of the silicon surface, and the first doping concentration distribution and the second doping concentration distribution are asymmetric.

In another embodiment of the present invention, the transistor structure further includes a first insulating layer, wherein the first insulating layer is formed in the first groove and located below the first conductive region. The first conductive region includes a first upper portion, a second upper portion, and a lower portion, the first upper portion and the second upper portion contact the spacer layer, and the lower portion contacts the channel region and is located in the on the upper layer of the first insulating layer. In addition, the transistor structure further includes a second insulating layer. The second insulating layer covers the first conductive region. In addition, the transistor structure further includes a contact region. The contact region is formed at least partially within the first recess, wherein the second upper portion of the first conductive region contacts the contact region, and the second insulating layer contacts the first upper portion of the first conductive region and the lower portion is distinguished from the contact.

In another embodiment of the present invention, the conductive region of the adjacent transistor structure is electrically isolated from the first conductive region. In addition, in another embodiment of the present invention, at least a part of the channel region is located under the gate electrode and the spacer layer, and the length of the channel region is not less than the sum of the length of the gate electrode and the length of the spacer layer . Additionally, in another embodiment of the present invention, a highly stressed dielectric layer is formed over the first conductive region, the spacer layer, and the gate.

Another embodiment of the present invention discloses a transistor structure. The transistor structure includes a gate electrode, a spacer layer, a channel region, and a first conductive region. The gate is located above a silicon surface. The spacer layer covers a side wall of the gate electrode. At least a portion of the channel region is located under the gate and the spacer layer. The first conductive region is formed between the spacer layer and a side insulating layer, wherein a portion of a sidewall of the first conductive region is covered by the side insulating layer

In another embodiment of the present invention, the first conductive region is partially formed in a first groove, and the side insulating layer is partially formed in the first groove. A bottom insulating layer is formed in the first groove, and the first conductive region is located on the bottom insulating layer. The first conductive region includes a first upper portion, a second upper portion, and a lower portion, the first upper portion and the second upper portion contact the spacer layer, and the lower portion contacts the channel region and is located in the over the bottom insulating layer. In addition, the transistor structure further includes a contact region. The contact region is formed at least partially within the first recess, wherein the second upper portion of the first conductive region contacts the contact region, and the side insulating layer the first upper portion of the first conductive region The portion and the lower portion are distinguished from the contact. Additionally, in another embodiment of the present invention, the first conductive region includes silicon, silicon carbide, or silicon germanium.

In another embodiment of the present invention, the transistor structure further includes a second conductive region, another side insulating layer, and another contact region. The second conductive region is partially formed in a second groove. The other side insulating layer is partially formed in the second groove. The other contact region is partially formed in the second recess, wherein the second conductive region includes a first upper portion, a second upper portion, and a lower portion, the lower portion of the second conductive region contacting the channel region, the second upper portion of the second conductive region contacts the other contact region, and the other side insulating layer contacts the first upper portion and the lower portion of the second conductive region with the other Contact distinction.

In another embodiment of the present invention, the transistor structure further includes another spacer layer. The other spacer layer covers the other sidewall of the gate electrode, wherein the length of the channel region is not less than the sum of the length of the gate electrode, the length of the spacer layer, and the length of the other spacer layer. In addition, the spacer layer and the other spacer layer are regenerated spacer layers. Additionally, in another embodiment of the present invention, the transistor structure further includes a lightly doped drain region under the spacer layer.

Another embodiment of the present invention discloses a transistor structure. The transistor structure includes a gate electrode, a spacer layer, a channel region, a first conductive region, and a second conductive region. The gate is located above a silicon surface. The spacer layer is located above the silicon surface and covers a sidewall of the gate. At least a portion of the channel region is located below the gate electrode and the spacer layer. The transistor structure is an asymmetrical transistor structure.

In another embodiment of the present invention, a first doping concentration distribution of the first conductive region along a first extension direction is different from a second doping concentration distribution of the second conductive region along a second extension direction concentration distribution. The structure between the gate electrode and the first conductive region is different from the structure between the gate electrode and the second conductive region. A lightly doped drain region is formed between the gate and the first conductive region. In another embodiment of the present invention, the first conductive region includes a first lower portion under the silicon surface, the second conductive region includes a second lower portion under the silicon surface, and the first lower portion The thickness of the lower portion is different from the thickness of the second lower portion. The width of one end of the channel region adjacent to the first conductive region is different from the width of the other end of the channel region adjacent to the second conductive region. The material of the first conductive region is different from the material of the second conductive region.

Another embodiment of the present invention discloses a transistor structure. The transistor structure includes a gate electrode, a spacer layer, a channel region, a first conductive region, and a second conductive region. The gate is located above a silicon surface. The spacer layer is located above the silicon surface and covers a sidewall of the gate. The spacer layer is located above the silicon surface and covers a sidewall of the gate and at least a portion of the channel region is located below the gate and the spacer layer. The first conductive region is electrically coupled to one end of the channel region and the second conductive region is electrically coupled to the other end of the channel region. The turn-on current of the transistor structure is dependent on the parameters of the first conductive region, the parameters of the channel region, the asymmetry parameters of the transistor structure, and the presence of at least the second insulating layer covering the sidewalls of the first conductive region. one of them.

In another embodiment of the present invention, the off current of the transistor structure is dependent on parameters of the first conductive region, parameters of the channel region, asymmetry parameters of the transistor structure, and parameters present in the first conductive region at least one of the first insulating layers below the region.

The invention discloses a transistor structure. The transistor structure includes a gate electrode, a spacer layer, a channel region, a first conductive region, and a second conductive region, wherein the spacer layer connects the first conductive region and the second conductive region with the gate electrode separated, and the gate is also separated by the spacer layer. In addition, the first conductive region is formed on a sidewall of a first groove, and the second conductive region is formed on a sidewall of a second groove, wherein each of the first conductive region and the second conductive region A portion of the sidewall of a conductive region is covered by an insulating layer, and another additional insulating layer may be selectively formed on the bottom surface of the first recess, as well as the bottom surface of the second recess. Therefore, compared with the fin structure transistor provided in the prior art, the transistor structure provided by the present invention can reduce the leakage current and can adjust the on/off current of the transistor through the parameters of the transistor.

Please refer to Figure 1A. FIG. 1A is a schematic diagram of a transistor structure 100 disclosed in a first embodiment of the present invention. As shown in FIG. 1A , the transistor structure 100 includes a gate electrode 101 , a spacer layer 103 , a channel region 105 , a first conductive region 107 , and a second conductive region 109 . In addition, a shallow trench isolation (STI) structure 110 is formed beside the transistor structure 100 , and the structure of the STI structure 110 is well known to those skilled in the art of the present invention and will not be repeated here. . The gate 101 is formed on a dielectric layer 111 , wherein the dielectric layer 111 is formed on the silicon surface 113 of the substrate 112 . In addition, a capping structure 115 may be formed on the gate electrode 101 . The spacer layer 103 is formed on the silicon surface 113 and includes a first portion 1031 and a second portion 1032 , wherein the first portion 1031 covers the left sidewall of the gate 101 and the second portion 1032 covers the right sidewall of the gate 101 . In addition, in an embodiment of the present invention, the spacer layer 103 has a three-layer structure, wherein the three-layer structure is a thin oxide layer, a nitride layer, and an oxide layer, respectively. However, the present invention is not limited to the spacer layer 103 having the three-layer structure. That is, the spacer layer 103 may be a single-layer or multi-layer dielectric layer, and the multi-layer dielectric layer may include nitride, oxide, oxynitride, or other dielectric materials. The channel region 105 is formed below the gate electrode 101 and the spacer layer 103 , and the channel region 105 is aligned with the spacer layer 103 . Because of the spacer layer 103 , the length of the channel region 105 is greater than the length of the gate electrode 101 . However, in another embodiment of the present invention, the channel region 105 is not completely located under the gate electrode 101 and the spacer layer 103 . That is, at least a part of the channel region 105 is located under the gate electrode 101 and the spacer layer 103 . In addition, the length of the channel region 105 can be adjusted according to the length of the spacer layer 103 and the length of the gate electrode 101 . Additionally, a dopant may be formed in the channel region 105 . In addition, in another embodiment of the present invention, lightly doped regions may be formed between the gate electrode 101 and the first conductive region 107 and/or between the gate electrode 101 and the second conductive region 109 .

The first conductive region 107 is formed and contacts the sidewall of a first recess 117, and the first conductive region 107 includes a lower portion 1071 and an upper portion (including a first upper portion 1072 and a second upper portion 1073), The lower portion 1071 is coupled to the channel region 105 , and the first upper portion 1072 and the second upper portion 1073 are coupled to the first portion 1031 of the spacer layer 103 . In addition, the top surface of the second upper portion 1073 may be higher or lower than the top of the gate electrode 101, and as shown in FIG. 1A, the thickness of the lower portion 1071 (eg, the distance from the top to the bottom of the lower portion 1071, The top of the lower portion 1071 aligned with the silicon surface 113) is greater than the thickness of the channel region 105 (eg, the distance from the top to the bottom of the channel region 105). In addition, in another embodiment of the present invention, the height of the first conductive region 107 is greater than the length of the gate electrode 101 along the silicon surface 113 , or greater than the length of the gate electrode 101 along the silicon surface 113 and the spacer layer 103 along the silicon surface 113 . The sum of the lengths of surfaces 113 . In addition, the first conductive region 107 may include a material having silicon such as silicon (Si), silicon carbide (SiC), or silicon germanium (SiGe).

A first insulating layer 119 is formed within the first groove 117 and covers the bottom surface of the first groove 117 , wherein the first insulating layer 119 is formed under the lower portion 1071 . A second insulating layer 121 is formed beside the first conductive region 107 and covers the sidewalls of the lower portion 1071 and the sidewalls of the first upper portion 1072 . In addition, the material of the first insulating layer 119 and/or the material of the second insulating layer 121 may be oxides, nitrides, or other insulating materials. In an embodiment of the present invention, the first insulating layer 119 and/or the second insulating layer 121 may be formed by thermal oxidation. In addition, in another embodiment of the present invention, the first insulating layer 119 and the second insulating layer 121 are formed by atomic layer deposition (Atomic-Layer-Deposition, ALD) or chemical vapor deposition (chemical vapor deposition, CVD) )form.

In addition, a conductive region 133 is also partially formed in the first recess 117 , wherein the conductive region 133 is included in an adjacent transistor structure next to the transistor structure 100 , and the conductive region 133 can pass through the second insulating layer 121 or other isolation methods to isolate or electrically isolate the first conductive region 107 . In another embodiment of the present invention, the conductive region 133 and the first conductive region 107 are formed and connected together to form a "collar" shaped conductive region within the first recess 117, as well as the transistor structure The adjacent transistor structure next to 100 may be a dummy structure or other transistor.

In addition, the first conductive region 107 is coupled to a contact region 123 through the second upper portion 1073 , wherein the contact region 123 is used for future interconnection of the transistor structure 100 . Due to the second insulating layer 121 , the second insulating layer 121 separates the lower portion 1071 and the first upper portion 1072 of the first conductive region 107 from the contact region 123 . Additionally, the contact region 123 may comprise heavily doped polysilicon or a metal-containing material. In this case, the conductive region 133 is physically separated from the first conductive region 107 , and the conductive region 133 is electrically coupled to the first conductive region 107 through the contact region 123 .

The first conductive region 107 has a first doping concentration distribution along a first extending direction of the first conductive region 107 , wherein the first extending direction extends upward from the lower portion 1071 to the second upper portion 1073 . That is, the first extending direction is parallel to (or substantially parallel to) the normal direction of the silicon surface 113 . Specifically, the first doping concentration profile includes the doping concentration of the lower portion 1071 , the doping concentration of the first upper portion 1072 , and the doping concentration of the second upper portion 1073 . In an embodiment of the present invention, the doping concentration of the first upper portion 1072 and/or the doping concentration of the second upper portion 1073 is higher than the doping concentration of the lower portion 1071 . However, the present invention is not limited to the doping concentration of the first upper portion 1072 and/or the doping concentration of the second upper portion 1073 being higher than the doping concentration of the lower portion 1071, that is, the first doping concentration profile Other doping concentration profiles are possible, such as any order combination of light doping, normal doping, and heavy doping.

In addition, the resistance value of the first conductive region 107 can be controlled by adjusting the first doping concentration distribution of the first conductive region 107 . That is, for example, when the turn-on current of the transistor structure 100 flows from the first conductive region 107 to the channel region 105 , the value of the turn-on current also depends on the first doping concentration distribution of the first conductive region 107 . In addition, the voltage drop of the first conductive region 107 can be reduced or changed by controlling the resistance value of the first conductive region 107 . In addition, as shown in FIG. 1A , the length of the channel region 105 is greater than the length of the gate electrode 101 , and the first insulating layer 119 also reduces the contact area between the first conductive region 107 and the substrate 112 . For the above reasons, the leakage current of the transistor structure 100 can be reduced. In addition, in another embodiment of the present invention, the resistance value of the first conductive region 107 can be controlled by the height, width, or length of the first conductive region 107 . In addition, in another embodiment of the present invention, the first insulating layer 119 may be omitted when the leakage current of the transistor structure 100 is not critical to the operation of the transistor structure 100 .

Similar to the first conductive region 107, the second conductive region 109 of the transistor structure 100 is formed and contacts the sidewall of a second recess 125, and the second conductive region 109 includes a lower portion 1091 and an upper portion (including a first upper portion 1092, and a second upper portion 1093), wherein the second conductive region 109 has a second doping concentration distribution along a second extension of the second conductive region 109, and the second extension direction is defined by The lower portion 1091 extends upward to the second upper portion 1093 . In addition, the first doping concentration distribution of the first conductive region 107 and the second doping concentration distribution of the second conductive region 109 are symmetrical. However, in another embodiment of the present invention, the first doping concentration profile and the second doping concentration can be made intentionally asymmetric.

In addition, a first insulating layer 127 is formed under the second conductive region 109 , a second insulating layer 129 is formed beside the second conductive region 109 , and the second conductive region 109 is coupled to a contact region 131 . For the structures and features of the second conductive region 109 , the first insulating layer 127 , the second insulating layer 129 , and the contact region 131 , please refer to the above-mentioned related to the first conductive region 107 , the first insulating layer 119 , the second insulating layer 121 , and the contact region 131 The description of the structure and features of the region 123 will not be repeated here.

Please refer to Figure 1B. The embodiment of FIG. 1B is similar to the embodiment of FIG. 1A, but the difference between the embodiment of FIG. 1B and the embodiment of FIG. 1A is that the conductive region 133 of the adjacent transistor structure is through the second insulating layer 121 and an isolation material 1231 are physically and electrically isolated from the first conductive region 107 . In addition, the tops of the first conductive regions 107 and 133 can be aligned with the tops of the spacer layers 103, so the first conductive regions 107 (or the conductive regions 133) can be independently electrically coupled to other wires. Similarly, another conductive region of another adjacent transistor structure is physically and electrically isolated from the second conductive region 109 by the second insulating layer 129 and another isolation material 1311 , so the second conductive region 109 is also Can be independently electrically coupled to another conductor.

Please refer to Figure 2-11. FIG. 2 is a flowchart of a method for manufacturing a transistor structure 100 disclosed in a second embodiment of the present invention. The manufacturing method of FIG. 2 will be described using FIG. 3-11, wherein FIG. 3-11 also depicts the adjacent transistor structure (or the adjacent dummy structure) next to the transistor structure 100, but in order to simplify the first Fig. 3-11, the structure of which is not shown in Fig. 3-11. The detailed steps of the manufacturing method are as follows:

Step 200: start;

Step 201: forming a first dielectric layer 301, a polysilicon layer 303, a first oxide layer 305, and a first nitride layer 307 on the silicon surface 113;

Step 202: forming a dielectric layer 111, a gate 101, and a capping structure 115 by etching a region outside the gate pattern;

Step 204: forming a spacer layer 103 beside the dielectric layer 111, the gate electrode 101, and the capping structure 115;

Step 206: Using the spacer layer 103 as a mask for anisotropic etching technique to form the first groove 117 and the second groove 125;

Step 208: Form the first insulating layers 119 and 127 in the first groove 117 and the second groove 125, respectively;

Step 210: Etch back the first insulating layers 119, 127;

Step 212: forming a first conductive region 107 and a second conductive region 109 on the first insulating layers 119 and 127, respectively;

Step 214: forming and etching back the second insulating layers 121 and 129;

Step 216: Form the contact regions 123 and 131 by filling the first groove 117 and the second groove 125, respectively;

Step 218: End.

First, using process steps well known to those skilled in the art of the present invention, a shallow trench isolation structure 110 (as shown in FIG. 1A ) can be formed in the substrate 112 first, wherein the top of the shallow trench isolation structure 110 is lower than the silicon The surface 113 is about 25 to 30 nanometers, and the bottom surface of the shallow trench insulating structure 110 can be about 300 to 1000 nanometers deep into the substrate 112 . In addition, as shown in FIG. 3, in step 201, a first dielectric layer 301 is formed on the silicon surface 113, wherein the first dielectric layer 301 may be a thermally grown oxide, an oxide and a composite insulating material, or other High dielectric constant (high-k) material. Next, a polysilicon layer 303 (including doped polysilicon, polysilicon plus silicide material, metal, or other gate materials) is deposited on the first dielectric layer 301 , and an oxide layer 305 and a second gate material are sequentially deposited on the polysilicon layer 303 A nitride layer 307 .

In step 202, as shown in FIG. 4, the gate pattern corresponding to the dielectric layer 111, the gate 101, and the capping structure 115 is defined by a lithography masking step, and the anisotropy is utilized The etching technique etches the region outside the gate pattern, wherein the dielectric layer 111 includes a first dielectric layer 301 , the gate 101 includes a polysilicon layer 303 , and the capping structure 115 includes a first oxide layer 305 and a first nitride layer 307 .

In step 204, a thin oxide layer 401, a second nitride layer 403, and a second oxide layer 405 are sequentially formed, wherein the thin oxide layer 401 is coupled to the dielectric layer 111, the gate electrode 101, and the capping structure 115. The dinitride layer 403 is coupled to the thin oxide layer 401 , and the second oxide layer 405 is coupled to the second nitride layer 403 . Next, as shown in FIG. 5 , the spacer layer 103 (including the first portion 1031 and the second portion 1032 ) is formed using the anisotropic etching technique. In addition, the spacer layer 103 is not limited to a three-layer structure, that is, the spacer layer 103 may include a two-layer structure or other multi-layer structures.

In step 206, as shown in FIG. 6A, the spacer layer 103 is used as a mask to form the first groove 117, the second groove 125, and the first groove by an etching technique (eg, the anisotropic etching technique) 117 and the sidewalls of the second groove 125 are aligned with the spacer layer 103, wherein the depth of each groove in the first groove 117 and the second groove 125 may be 10 nm, or between 10 nm and 30 nm between. Additionally, in another embodiment of the present invention, a portion of the second oxide layer 405 and the second nitride layer 403 may be re-etched to expose a portion 501 of the silicon surface 113 (as shown in FIG. 6B ), wherein the portion 501 is Being on top of the sidewalls of the first groove 117 and the second groove 125 causes the sidewalls of the first groove 117 and the second groove 125 to be misaligned with the spacer layer 103 . In subsequent steps of the manufacturing method, Figs. 7-9, 10A, 10B, 11, 12A are described based on the structure of Fig. 6A, and Fig. 12B is described based on the structure of Fig. 6B.

In step 208 , as shown in FIG. 7 , a first insulating layer 119 is formed in the first groove 117 and covers the sidewalls and the bottom of the first groove 117 . Likewise, the first insulating layer 127 is formed in the second groove 125 and covers the sidewalls and the bottom of the second groove 125 . Additionally, the first insulating layers 119, 127 may be thermally grown oxides, deposited oxides, deposited composite insulating materials, or other high dielectric constant materials.

In step 210, as shown in FIG. 8, portions of the first insulating layers 119, 127 are etched back so that the tops of the first insulating layers 119, 127 are lower than the silicon surface 113, so that the sidewalls of the channel region 105 are exposed.

In step 212 , as shown in FIG. 9 , the first conductive region 107 is formed and contacts the sidewall of the first groove 117 and is disposed on the first insulating layer 119 . Likewise, the second conductive region 109 is formed and contacts the sidewall of the second groove 125 and is disposed on the first insulating layer 127 . In an embodiment of the present invention, the first conductive region 107 and the second conductive region 109 are formed by a deposition method (eg, the atomic layer deposition method or the chemical vapor deposition method). However, in another embodiment of the present invention, the first conductive region 107 and the second conductive region 109 are grown by a selective-epitaxy-growth (SEG) method. In particular, the selective epitaxial growth method can use the left side wall of the channel region 105 as a silicon-growth seeding to grow a single-crystalline on the part of the side wall of the first groove 117 The silicon layer is used as the lower portion 1071 of the first conductive region 107, and then based on the lower portion 1071, the remaining first conductive region 107 (eg, the first upper portion 1072 and the second upper portion 107) are further grown by the selective epitaxial growth method. section 1073). During the use of the selective epitaxial growth method, the first doping concentration profile of the first conductive region 107 can be controlled. Likewise, the selective epitaxial growth method can use the right sidewall of the channel region 105 as the silicon growth seed, and grow the single-crystal silicon layer on the sidewall of the second groove 125 as the second conductive region 109 .

In addition, each of the lower portion 1071, the first upper portion 1072, and the second upper portion 1073 may be processed by different mechanisms (eg, using different doping concentrations or using other non-silicon materials such as mixtures of germanium or carbon atoms, etc. ) deposited (or grown) so that the first conductive region 107 has the first doping concentration profile. Likewise, each of the lower portion 1091, the first upper portion 1092, and the second upper portion 1093 can also be deposited (or grown) by the different mechanism, so that the second conductive region 109 has the second dopant Impurity concentration distribution. In addition, in another embodiment of the present invention, a laser-annealing technique (or a rapid thermal annealing technique or other annealing techniques) can be used to process the first conductive region 107 and the second conductive region region 109 to increase the quality and stability of the first conductive region 107 and the second conductive region 109 . In addition, how to design the shape of the first conductive region 107 and the shape of the second conductive region 109 depends on the expected resistance value of the first conductive region 107 and the second conductive region 109 and the influence of the voltage/electric field distribution, wherein the first conductive region 107 The shape/resistance of the transistor structure 109 or the shape/resistance of the second conductive region 109 can effectively control the on/off current of the transistor structure 100 .

In addition, in another embodiment of the present invention, the first conductive region 107 and the second conductive region 109 may include a material with silicon (eg, silicon, silicon carbide, or silicon germanium) to generate stress to improve the channel region 105 mobility. Additionally, as shown in FIG. 10A, when the first conductive region 107 and the second conductive region 109 include silicon carbide, the spacer layer 103 may be removed to improve the stress. However, in another embodiment of the present invention, as shown in FIG. 10B , a second dielectric layer may be formed on the spacer layer 103 , the capping structure 115 , and/or the first conductive region 107 and the second conductive region 109 1003 (eg silicon nitride).

In step 214, as shown in FIG. 11, the second insulating layers 121 and 129 are formed and etched back so that the second insulating layer 121 covers the lower portion 1071 and the first upper portion 1072 of the first conductive region 107, and the second insulating layer 121 is The second insulating layer 129 covers the lower portion 1091 and the first upper portion 1092 of the second conductive region 109 . In addition, the second insulating layers 121, 129 may be thermally grown oxides, oxides and composite insulating materials, or other high dielectric constant materials. As shown in FIG. 11 , the second upper portion 1073 of the first conductive region 107 is not covered by the second insulating layer 121 , and the second upper portion 1093 of the second conductive region 109 is not covered by the second insulating layer 129 .

In step 216, by filling n+ polysilicon material, p+ polysilicon material, metal, or other conductive materials in the first groove 117 and the second groove 125 to form contact regions 123, 131, respectively, in an implementation of the present invention For example, the tops of the contact regions 123 , 131 are aligned with the tops of the capping structures 115 . Thus, FIG. 12A shows the final structure of the transistor structure 100 . However, in another embodiment of the present invention, the tops of the contact regions 123 , 131 may be higher than the tops of the capping structures 115 . In addition, FIG. 12B shows the final structure of the transistor structure 100 in the embodiment corresponding to FIG. 6B. As shown in FIG. 12B, because the spacer layer 103 is etched back to expose the portion 501 of the silicon surface 113, the portion 501 of the silicon surface 113 can also be used as the silicon growth seed to vertically above the portion 501 of the silicon surface 113 The first conductive region 107 and the second conductive region 109 are grown on the ground.

In another embodiment of the present invention, the formation of the first insulating layers 119 and 127 is unnecessary, that is, the step 208 may be omitted. In addition, as shown in FIG. 13, in another embodiment of the present invention, the part of the first conductive region 107 below the silicon surface 113 can be completely formed in the first groove 117 and the second conductive region 109 The portion below the silicon surface 113 may be completely formed in the second groove 125 . That is, the second insulating layers 121, 129 may be omitted. In addition, the first doping concentration profile of the first conductive region 107 and the second doping concentration profile of the second conductive region 109 may be controlled in the above-mentioned manner.

In addition, as shown in FIG. 14, in another embodiment of the present invention, the second oxide layer 405 of the spacer layer 103 may be removed to expose a gap 1303, and a third oxide layer or insulating layer 1304 (eg, 15 ) can be formed or regenerated in the gap 1303 to increase the interface quality between the first conductive region 107 and the spacer layer 103 and the interface quality between the second conductive region 109 and the spacer layer 103 . In addition, the regeneration of the spacer layer shown in Figs. 14 and 15 is not limited to the structure of the embodiment shown in Fig. 13, and the regeneration can also be used for the embodiment shown in Fig. 12A or 12B. In addition, in another embodiment of the present invention, the polysilicon layer 303 (corresponding to the gate 101 ) used for the gate-first process can be replaced with a gate-last process and Other materials or p+ doped polysilicon with appropriate work function (from 4.0 eV to 5.2 eV).

In addition, in another embodiment of the present invention, the first doping concentration distribution of the first conductive region 107 and the second doping concentration distribution of the second conductive region 109 can be deliberately made asymmetric to increase the transistor structure 100 the turn-on current. For example, please refer to FIG. 16, wherein FIG. 16 shows transistor structures 1600, 1601, 1602, and 1603 of four embodiments, and transistor structures 1600, 1601, 1602, and 1603 correspond to a reference embodiment and an implementation, respectively. Example 1, an Example 2, and an Example 3. In addition, each of the transistor structures 1600, 1601, 1602, 1603 includes a gate structure G, the transistor structure 1600 includes a source S0 and a drain D0, and the transistor structure 1601 includes a source S1 and a drain electrode D1, the transistor structure 1602 includes a source electrode S2 and a drain electrode D2, and the transistor structure 1603 includes a source electrode S3 and a drain electrode D3, wherein the source electrodes S0-S3 are the transistor structure 1600, The first conductive regions of 1601, 1602, and 1603, and the drain electrodes D0-D3 are the second conductive regions of transistor structures 1600, 1601, 1602, and 1603, respectively. In order to simplify the illustration, FIG. 16 only shows the gate structures G, the source electrodes S0-S3, and the drain electrodes D0-D3 of the transistor structures 1600, 1601, 1602, and 1603. In addition, the source electrodes S0-S3 and the drain electrodes D0-D3 are drawn with different labels to represent different doping concentrations, wherein the design of the different doping concentrations depends on the requirements of the on-current and/or the off-current (or applications). In particular, as shown in this reference embodiment and Embodiment 1-3, the doping concentration distribution of the source S0 is the same as the doping concentration distribution of the drain D0, and the doping concentration distribution of the source S3 is the same as that of the drain D3 The doping concentration distribution is the same. However, the doping concentration distribution of the source electrode S0 (drain electrode D0 ) is different from the doping concentration distribution of the source electrode S3 (drain electrode D3 ). For example, the doping concentration distribution of the source electrode S0 includes light doping, normal doping, and heavy doping from bottom to top; while the doping concentration distribution of the source electrode S3 only includes heavy doping. On the other hand, the doping concentration distribution of the source S1 (eg, from bottom to top includes light doping, normal doping, and heavy doping) and the doping concentration distribution of the drain D1 (eg, bottom-to-top) ground only includes heavy doping), and the doping concentration profile of source S2 (e.g., includes only heavy doping from bottom to top) and the doping concentration distribution of drain D2 (e.g., includes bottom-up lightly doped, normally doped, and heavily doped) are different. The turn-on currents of Examples 1 and 2 are higher than that of the reference example. In general, the embodiments with asymmetric doping concentration profiles (ie, Examples 1 and 2) have higher turn-on currents than the reference example. Additionally, the desired asymmetric doping concentration profile can be selected to produce a desired on-current and an acceptable corresponding off-current, although in some cases the asymmetric doping concentration profile may result in a slight increase in the off current.

As mentioned above, since the first conductive region 107 and/or the second conductive region 109 may comprise silicon, silicon carbide, or silicon germanium, the material of the first conductive region 107 may be different from the material of the second conductive region 109 . Therefore, a transistor having a characteristic that the material of the first conductive region 107 is different from that of the material of the second conductive region 109 is an asymmetrical transistor.

In addition, in another embodiment of the present invention, as shown in FIG. 17, before the spacer layer 103 is completed, some diffusion sources (without the hazard of ion implantation) or implants (implants, which need to be followed by A lightly doped drain is formed under the silicon surface 113 and between the first conductive region 107 (eg, the drain) and the gate 101 by thermal annealing or laser annealing to remove ion implantation hazards. Lightly-Doped-Drain (LDD) region 135. As shown in FIG. 17 , the lightly doped drain region 135 is formed under the silicon surface 113 of the substrate 112 or under a fin structure, and under the gate 101 and/or the spacer layer 103 . In this case, no lightly doped drain is formed between the gate 101 and the second conductive region 109 (eg, the source). In addition, in another embodiment of the present invention, a lightly doped drain region is formed between the gate electrode 101 and the source electrode, instead of forming the lightly doped drain region between the gate electrode 101 and the drain electrode pole. Therefore, at this time, the structure between the gate electrode 101 and the source electrode is different from the structure between the gate electrode 101 and the drain electrode, that is to say, the structure between the gate electrode 101 and the source electrode is different from that between the gate electrode 101 and the drain electrode. The transistor structure characteristic of the structure between the drains is an asymmetrical transistor structure.

In addition, the thickness of the lower portion 1071 of the first conductive region 107 (ie, the distance from the silicon surface 113 to the bottom of the lower portion 1071 ) may be different from the thickness of the lower portion 1091 of the second conductive region 109 , so one end of the channel region 105 can be different from the width of the other end of the channel region 105 , that is to say, the thickness of the lower portion 1071 including the first conductive region 107 is different from the thickness of the lower portion 1091 of the second conductive region 109 and the width of one end of the channel region 105 A transistor structure characterized by a width other than the other end of the channel region 105 is also an asymmetrical transistor structure.

Please refer to Figure 1A again. The channel region 105, the first conductive region 107 and the second conductive region 109 are formed using a self-alignment technique. Therefore, the transistor structure 100 will be more accurately controllable, have a smaller form-factor, and occupy less wafer plane area. In addition, because the steps of the fabrication method of the transistor structure 100 can avoid using an ion-implantation technique to form a p-n junction between the first conductive region 107 (or the second conductive region 109 ) and the substrate 112 , the Damage caused by ion implantation techniques in the p-n junction can be reduced. In addition, the position of the p-n junction, the thickness of the lower portion 1071 of the first conductive region 107 (or the thickness of the lower portion 1091 of the second conductive region 109 ), and the first doping concentration distribution and the second doping concentration distribution are better controlled.

In addition, in the transistor structure provided by the present invention, the on/off current depends on the parameters of the first conductive region 107 (eg, the distribution of the first doping concentration, the material, the thickness of the lower portion 1071 of the first conductive region 107, and the thickness of the second upper portion 1073 of the first conductive region 107), the parameters of the second conductive region 109, the parameters of the channel region 105 (such as the length of the channel region 105), the asymmetric parameters of the transistor structure (such as the above symmetrical structure), and/or the presence of the first insulating layer/second insulating layer, etc. Therefore, the on/off current of the transistor structure can be adjusted by at least one of the above parameters.

To sum up, the transistor structure provided by the present invention includes the gate electrode, the spacer layer, the channel region, the first conductive region, and the second conductive region, wherein the first conductive region and the gate electrode are separated by The spacer layer is separated, and the second conductive region and the gate are also separated by the spacer layer. In addition, the first conductive region is formed and contacts the sidewall of the first recess, and the second conductive region is formed and contacts the sidewall of the second recess, wherein each of the first conductive region and the second conductive region Portions of the sidewalls of the conductive region are covered by an insulating layer, and another insulating layer may be formed on the bottom surface of the first groove, as well as the bottom surface of the second groove. Therefore, compared with the fin structure transistor provided in the prior art, the transistor structure provided by the present invention can reduce leakage current and can adjust the on/off current of the transistor through the parameters of the transistor. The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100, 1600, 1601, 1602, 1603: Transistor Structure 101: Gate 103: Spacer Layer 1031: Part 1 1032: Part II 105: Passage area 107: The first conductive area 1071, 1091: The lower part 1072, 1092: First Upper Section 1073, 1093: Second upper part 109: Second conductive area 110: Shallow trench insulation structure 111: Dielectric layer 112: Base 113: Silicon Surface 115: Overlay Structure 117: First groove 119, 127: the first insulating layer 121, 129: the second insulating layer 123, 131: Contact area 125: Second groove 133: Conductive area 135: Lightly doped drain region 1231, 1311: isolation material 200-218: Steps 301: first dielectric layer 303: polysilicon layer 305: first oxide layer 307: first nitride layer 401: Thin oxide layer 403: the second nitride layer 405: Second oxide layer 501: Section 1003: Second Dielectric Layer 1303: Clearance 1304: Insulation layer G: Gate structure S0-S3: source D0-D3: drain

FIG. 1A is a schematic diagram of a transistor structure disclosed in the first embodiment of the present invention. FIG. 1B is a schematic diagram of a transistor structure disclosed in another embodiment of the present invention. FIG. 2 is a flowchart of a method for manufacturing a transistor structure disclosed in a second embodiment of the present invention. FIG. 3 is a schematic diagram illustrating the formation of a first dielectric layer, a polysilicon layer, a first oxide layer, and a first nitride layer on the silicon surface. FIG. 4 is a schematic diagram illustrating the formation of a dielectric layer, a gate electrode, and a capping structure. FIG. 5 is a schematic diagram illustrating the formation of a spacer layer next to the dielectric layer, gate electrode, and capping structure. FIG. 6A is a schematic diagram illustrating the formation of a first groove and a second groove using a spacer layer as a mask of an anisotropic etching technique. FIG. 6B is a schematic diagram illustrating a portion of the spacer layer etched back to expose the silicon surface according to another embodiment of the present invention. FIG. 7 is a schematic diagram illustrating the formation of the first insulating layer in the first groove and the second groove. FIG. 8 is a schematic diagram illustrating etching back the first insulating layer. FIG. 9 is a schematic diagram illustrating the formation of a first conductive region and a second conductive region over the first insulating layer. FIG. 10A is a schematic diagram illustrating the removal of the spacer layer according to another embodiment of the present invention. FIG. 10B is a schematic diagram illustrating forming a second dielectric layer on the spacer layer, the capping structure, the first conductive region, and the second conductive region according to another embodiment of the present invention. FIG. 11 is a schematic diagram illustrating forming and etching back a second insulating layer. FIG. 12A is a schematic diagram illustrating the final structure of the transistor structure. FIG. 12B is a schematic diagram illustrating the final structure of the transistor structure according to the embodiment shown in FIG. 6B. FIG. 13 is a schematic diagram illustrating that the first conductive region and the second conductive region are completely formed in the first groove and the second groove, respectively, according to another embodiment of the present invention. FIG. 14 is a schematic diagram illustrating the removal of the second oxide layer of the spacer layer according to another embodiment of the present invention. FIG. 15 is a schematic diagram illustrating regeneration of a third oxide layer according to another embodiment of the present invention. FIG. 16 is a schematic diagram illustrating four embodiments of transistor structures according to another embodiment of the present invention. FIG. 17 is a schematic diagram of a transistor structure disclosed in another embodiment of the present invention.

100: Transistor Structure

101: Gate

103: Spacer Layer

1031: Part 1

1032: Part II

105: Passage area

107: The first conductive area

1071, 1091: The lower part

1072, 1092: First Upper Section

1073, 1093: Second upper part

109: Second conductive area

110: Shallow trench insulation structure

111: Dielectric layer

112: Base

113: Silicon Surface

115: Overlay Structure

117: First groove

119, 127: the first insulating layer

121, 129: the second insulating layer

123, 131: Contact area

125: Second groove

133: Conductive area

Claims (29)

A transistor structure comprising: a gate located above a silicon surface; a spacer layer located above the silicon surface, wherein the spacer layer covers at least one sidewall of the gate electrode; a channel region below the silicon surface; a first groove; and a first conductive area, at least partially formed in the first groove; A conductive region of an adjacent transistor structure next to the transistor structure is formed at least partially within the first recess. The transistor structure as claimed in claim 1, further comprising: a second groove; and A second conductive area is formed at least partially in the second groove. The transistor structure of claim 2, wherein the first conductive region has a first doping concentration distribution along a first extending direction, and the second conductive region has a distribution along a second extending direction The second doping concentration distribution, wherein the first extending direction and the second extending direction are parallel to the normal direction of the silicon surface, and the first doping concentration distribution and the second doping concentration distribution are asymmetric. The transistor structure as claimed in claim 1, further comprising: A first insulating layer is formed in the first groove and below the first conductive area. The transistor structure of claim 4, wherein the first conductive region comprises a first upper portion, a second upper portion, and a lower portion, the first upper portion and the second upper portion contacting the spacer layer , and the lower portion contacts the channel region and is located above the first insulating layer. The transistor structure of claim 5, further comprising: A second insulating layer covers the first conductive area. The transistor structure of claim 6, further comprising: a contact area formed at least partially within the first recess, wherein the second upper portion of the first conductive area contacts the contact area, and the second insulating layer the first upper portion of the first conductive area The portion and the lower portion are distinguished from the contact. The transistor structure of claim 1, wherein the conductive region of the adjacent transistor structure is electrically isolated from the first conductive region. The transistor structure of claim 1, wherein at least a portion of the channel region is located below the gate electrode and the spacer layer, and the length of the channel region is not less than the sum of the length of the gate electrode and the length of the spacer layer . The transistor structure of claim 1, wherein a highly stressed dielectric layer is formed over the first conductive region, the spacer layer, and the gate. A transistor structure comprising: a gate located above a silicon surface; a spacer layer covering a side wall of the gate electrode; a channel region, wherein at least a portion of the channel region is located below the gate and the spacer layer; and A first conductive area is formed between the spacer layer and a side insulating layer, wherein a part of a side wall of the first conductive area is covered by the side insulating layer. The transistor structure of claim 11, wherein the first conductive region is partially formed in a first recess, and the side insulating layer is partially formed in the first recess. The transistor structure of claim 12, wherein a bottom insulating layer is formed in the first groove, and the first conductive region is located on the bottom insulating layer. The transistor structure of claim 13, wherein the first conductive region comprises a first upper portion, a second upper portion, and a lower portion, the first upper portion and the second upper portion contacting the spacer layer , and the lower portion contacts the channel region and is above the bottom insulating layer. The transistor structure of claim 14, further comprising: a contact area formed at least partially within the first recess, wherein the second upper portion of the first conductive area contacts the contact area, and the side insulating layer the first upper portion of the first conductive area and the lower portion is distinguished from the contact. The transistor structure of claim 11, wherein the first conductive region comprises silicon, silicon carbide, or silicon germanium. The transistor structure of claim 11, further comprising: a second conductive area partially formed in a second groove; The other side insulating layer is partially formed in the second groove; and another contact area, partially formed in the second groove; The second conductive region includes a first upper portion, a second upper portion, and a lower portion, the lower portion of the second conductive region contacts the channel region, and the second upper portion of the second conductive region contacts The other contact region, and the other side insulating layer separate the first upper portion and the lower portion of the second conductive region from the other contact region. The transistor structure of claim 11, further comprising: Another spacer layer, wherein the other spacer layer covers the other side wall of the gate electrode, and the length of the channel region is not less than the sum of the length of the gate electrode, the length of the spacer layer, and the length of the other spacer layer . The transistor structure of claim 18, wherein the spacer layer and the further spacer layer are regenerated spacer layers. The transistor structure of claim 18, further comprising: A lightly doped drain region is located below the spacer layer. A transistor structure comprising: a gate located above a silicon surface; a spacer layer over the silicon surface and covering a sidewall of the gate; a channel region, wherein at least a portion of the channel region is located below the gate and the spacer layer; and a first conductive area and a second conductive area; Wherein the transistor structure is an asymmetric transistor structure. The transistor structure of claim 21, wherein a first doping concentration distribution of the first conductive region along a first extending direction is different from a second doping concentration distribution of the second conductive region along a second extending direction Doping concentration profile. The transistor structure of claim 21, wherein the structure between the gate electrode and the first conductive region is different from the structure between the gate electrode and the second conductive region. The transistor structure of claim 23, wherein a lightly doped drain region is formed between the gate and the first conductive region. The transistor structure of claim 23, wherein the first conductive region comprises a first lower portion below the silicon surface, the second conductive region comprises a second lower portion below the silicon surface, and The thickness of the first lower portion is different from the thickness of the second lower portion. The transistor structure of claim 23, wherein the width of one end of the channel region adjacent to the first conductive region is different from the width of the other end of the channel region adjacent to the second conductive region. The transistor structure of claim 21, wherein the material of the first conductive region is different from the material of the second conductive region. A transistor structure comprising: a gate located above a silicon surface; a spacer layer over the silicon surface and covering a sidewall of the gate; a channel region, wherein at least a portion of the channel region is located below the gate and the spacer layer; and a first conductive region and a second conductive region, wherein the first conductive region is electrically coupled to one end of the channel region and the second conductive region is electrically coupled to the other end of the channel region; The turn-on current of the transistor structure depends on the parameters of the first conductive region, the parameters of the channel region, the asymmetric parameters of the transistor structure, and the presence of the second insulating layer covering the sidewalls of the first conductive region. at least one of them. The transistor structure of claim 28, wherein the off current of the transistor structure is dependent on parameters of the first conductive region, parameters of the channel region, asymmetric parameters of the transistor structure, and parameters present in the first conductive region at least one of the first insulating layers below a conductive region.

Images