JPH02202032A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH02202032A JPH02202032A JP2168489A JP2168489A JPH02202032A JP H02202032 A JPH02202032 A JP H02202032A JP 2168489 A JP2168489 A JP 2168489A JP 2168489 A JP2168489 A JP 2168489A JP H02202032 A JPH02202032 A JP H02202032A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- high concentration
- diffusion
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 238000009792 diffusion process Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000012535 impurity Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 36
- 229920005591 polysilicon Polymers 0.000 abstract description 36
- 239000010408 film Substances 0.000 description 25
- 230000005669 field effect Effects 0.000 description 10
- 239000002131 composite material Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野）
この発明は高濃度な電極領域を有する半導体装置及びそ
の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a highly concentrated electrode region and a method for manufacturing the same.
第３図は従来の素子分離型複合素子構造の半導体装置を
示す断面図である。同図に示すように、ｎ−ポリシリコ
ン基体１上層部に絶縁ゲート型電界効果トランジスタ１
０Ａ、接合型バイポーラトランジスタＩＯＢがそれぞれ
絶縁Ｉ！１２により絶縁分離され形成されている。この
絶縁膜２上に所定の膜厚のｎ＋層３が形成され、このｎ
層３上にｎ−層４が形成されている。FIG. 3 is a sectional view showing a conventional semiconductor device having an element isolation type composite element structure. As shown in the figure, an insulated gate field effect transistor 1 is provided on the upper layer of an n-polysilicon substrate 1.
0A, junction bipolar transistor IOB is insulated I! 12 and is insulated and isolated. An n+ layer 3 having a predetermined thickness is formed on this insulating film 2.
An n-layer 4 is formed on layer 3.
電界効果トランジスタ１０Ａが形成されている素子形成
領Ｗｔ＜以下「島」という。）では、０層４の上層部に
ｐウェル領域５が形成されており、このｐウェル領域５
の表面部にｎ＋ソース領域６が選択的に形成されている
。The element formation region Wt in which the field effect transistor 10A is formed is hereinafter referred to as an "island". ), a p-well region 5 is formed in the upper layer part of the 0 layer 4, and this p-well region 5
An n+ source region 6 is selectively formed on the surface.
ｎ−層４の表面とｎ＋ソース領域６の表面とで挟まれた
ｐウェル領域５の表面上には、ゲート酸化膜７を介して
ポリシリコンゲート８が形成されている。また、ｎ 層
３表面にはドレイン電極９が形成され、ｎ＋ソース領域
６の表面の一部からｎ４ン一ス領域６間のｐウェル領域
５上にかけてソース電極１１が形成され、ポリシリコン
ゲート８上にはゲート電極１２が形成されている。これ
らの電極９．１１．．１２はそれぞれパッシベーション
１＄１８により絶縁されている。A polysilicon gate 8 is formed on the surface of the p-well region 5 sandwiched between the surface of the n- layer 4 and the surface of the n+ source region 6 with a gate oxide film 7 interposed therebetween. Further, a drain electrode 9 is formed on the surface of the n layer 3, a source electrode 11 is formed from a part of the surface of the n+ source region 6 to the p well region 5 between the n4 source regions 6, and a polysilicon gate 8 is formed. A gate electrode 12 is formed thereon. These electrodes9.11. ．． 12 are each insulated by passivation 1$18.
一方、バイポーラトランジスタ１０Ｂの島では、ｎ−１
１４の上層部にｐベース領域１３が形成されている。こ
のｐベース領域１３の表面部の一部にｎ＋エミッタ領域
１４が形成されている。そして、ｎ＋エミッタ領域１４
上にエミッタ電極１５が、ｐベース領域１３上にベース
電極１６が、ｎｌＳ上にコレクタ電極１７が形成されて
いる。これらのｆｆｍ１５〜１７はそれぞれパッシベー
ション膜１８により絶縁されている。On the other hand, in the island of bipolar transistor 10B, n-1
A p base region 13 is formed in the upper layer portion of the p-base region 14 . An n+ emitter region 14 is formed in a part of the surface of this p base region 13. And n+ emitter region 14
An emitter electrode 15 is formed on top, a base electrode 16 is formed on p base region 13, and a collector electrode 17 is formed on nlS. These ffm15-17 are each insulated by a passivation film 18.
第４図（ａ）〜（（１）は各々第３図で示した半導体装
置における島の形成方法を示す断面図である。FIGS. 4(a) to 4(1) are cross-sectional views showing a method of forming islands in the semiconductor device shown in FIG. 3, respectively.
以下、同図を参照しつつその形成方法の説明をする。Hereinafter, a method for forming the same will be explained with reference to the same figure.
第４図（ａ）で示すような単結晶のｎ 基板２１表面に
レジスト２２を形成し、同図（ｂ）に示すようにバター
ニングする。そして、バターニングされたレジスト２２
をマスクとして、ｎ−基板２１エツチングし、同図（Ｃ
）に示すようにＶ字型のくぼみ２３を形成する。各くぼ
み２３間の距離ｌが各島間の幅となる。A resist 22 is formed on the surface of a single-crystal n-type substrate 21 as shown in FIG. 4(a), and patterned as shown in FIG. 4(b). Then, the patterned resist 22
Using this as a mask, the n-substrate 21 was etched as shown in the same figure (C
), a V-shaped depression 23 is formed. The distance l between each depression 23 is the width between each island.
次に、くぼみ２３を含むｎ−基板２１の表面上にリン等
のｎ型の不純物を拡散しｎ＋層３を形成する。その模、
弗酸系の薬品で前処理（ｎ＋層３上に形成されたリンガ
ラス層等の除去）を施した模、ｎ＋層３上に熱酸化膜等
の絶縁膜２を同図（ｄ）に示すように形成する。Next, an n-type impurity such as phosphorus is diffused onto the surface of the n- substrate 21 including the depression 23 to form an n+ layer 3. That model,
Figure (d) shows an insulating film 2 such as a thermal oxide film on the n+ layer 3 after pre-treatment with a hydrofluoric acid-based chemical (removal of the phosphorus glass layer etc. formed on the n+ layer 3). Form it like this.
そして、絶縁１１２上にエピタキシャル成長技術により
ｎ−ポリシリコン層２４を同図（ｅ）に示すように形成
する。次に、ｎ−ｌ板２１の裏面より研磨し、同図（ｆ
）に示すように、絶縁膜２及びｎ”１１３をｎ−基板２
１裏面に露出させる。Then, an n-polysilicon layer 24 is formed on the insulator 112 by epitaxial growth technique, as shown in FIG. 4(e). Next, the back side of the n-l plate 21 is polished, and the
), the insulating film 2 and n''113 are connected to the n-substrate 2.
1 Expose on the back side.
その結果、このｎ−基板２１を裏返すと、同図（０）に
示すように、ｎ−ポリシリコン層２４を第３図のｎ ポ
リシリコン基体１とし、残ったｎ基板２１を第３図のｎ
”層４とし、絶縁膜２により各々が絶縁された複数の島
２５が完成する。そして、このようにして得られた島２
５の各々の中に、電界効果トランジスタ１０Ａ、バイポ
ーラトランジスタ１０８等が製造される。As a result, when this n-substrate 21 is turned over, the n-polysilicon layer 24 becomes the n-polysilicon base 1 of FIG. n
A plurality of islands 25, each insulated by the insulating film 2, are completed.
In each of the transistors 5, a field effect transistor 10A, a bipolar transistor 108, etc. are manufactured.
（発明が解決しようとする課題）
ところで、電界効果トランジスタ１０Ａにおいては、オ
ン抵抗、ドレイン−ソース間の順方向電圧を極力小さく
するため、バイポーラトランジスタ１０Ｂにおいては、
コレクターエミッタ間飽和電圧を極力小さくするため、
ドレイン電極９．コレクタ電極１７にそれぞれオーミッ
ク接続されるｎ＋層３を厚く、高濃度に形成する必要が
ある。(Problem to be Solved by the Invention) By the way, in the field effect transistor 10A, in order to minimize the on-resistance and the forward voltage between the drain and source, in the bipolar transistor 10B,
In order to minimize the collector-emitter saturation voltage,
Drain electrode9. It is necessary to form the n+ layer 3, which is ohmically connected to the collector electrode 17, thick and highly concentrated.
しかしながら、不純物拡散法によって、膜厚が厚く、高
濃度なｎ” Ｊｉ１３を形成することは、１つは処理に
時間がかかり過ぎて作業性が悪いという理由、他の１つ
は拡散によって実現できる濃度値に限界がある（およそ
１０〜１０”０ｚ−３）という理由により、極めて困難
であるという問題点があった。However, it is difficult to form a thick, highly concentrated n'' Ji13 film using the impurity diffusion method, because one reason is that the process takes too much time and has poor workability, and the other is that it can be achieved by diffusion. The problem is that it is extremely difficult due to the limited density value (approximately 10-10''0z-3).
この発明は上記のような問題点を解決するためになされ
たもので、所望の膜厚で高濃度な電極領域を有する半導
体装置及びその製造方法を得ることを目的とする。The present invention has been made to solve the above-mentioned problems, and aims to provide a semiconductor device having a high concentration electrode region with a desired film thickness, and a method for manufacturing the same.
この発明にかかる半導体装置は、半導体基板と、前記半
導体基板上に形成された少なくとも１つの能動領域と、
前記能動領域内に形成された、所定の導電型の不純物を
高濃度に含む多結晶半導体層および該多結晶半導体層の
周囲に形成された前記所定の導電型の拡ｉｌ！！層より
成る電極領域とを備えている。A semiconductor device according to the present invention includes a semiconductor substrate, at least one active region formed on the semiconductor substrate,
A polycrystalline semiconductor layer containing a high concentration of impurities of a predetermined conductivity type formed in the active region and an enlarged polycrystalline semiconductor layer of the predetermined conductivity type formed around the polycrystalline semiconductor layer! ! and an electrode region consisting of layers.
一方、この発明にかかる半導体装置の製造方法は、半導
体基板を準備する工程と、前記半導体基板上に能動領域
を形成する工程と、前記能動領域内に所定の導電型の不
純物を高濃度に含む多結晶半導体層を形成する工程と、
前記多結晶半導体層を拡散源として前記所定の導電型の
不純物を拡散し、前記多結晶半導体層の周囲に拡散層を
形成する工程とを備え、前記拡散層は前記多結晶半導体
層とともに電極領域を形成している。Meanwhile, a method for manufacturing a semiconductor device according to the present invention includes the steps of preparing a semiconductor substrate, forming an active region on the semiconductor substrate, and including impurities of a predetermined conductivity type in the active region at a high concentration. forming a polycrystalline semiconductor layer;
diffusing the impurity of the predetermined conductivity type using the polycrystalline semiconductor layer as a diffusion source to form a diffusion layer around the polycrystalline semiconductor layer, the diffusion layer forming an electrode region together with the polycrystalline semiconductor layer. is formed.
この発明における電極領域は、能動領域に形成された、
所定の導電型の不純物を高濃度に含む多結晶半導体層と
、この多結晶半導体層を拡散源とした拡散により形成可
能な拡散層とからなるため、作業性良く、高濃度にかつ
膜厚を厚く形成することができる。The electrode region in this invention is formed in the active region.
Consisting of a polycrystalline semiconductor layer containing a high concentration of impurities of a predetermined conductivity type and a diffusion layer that can be formed by diffusion using this polycrystalline semiconductor layer as a diffusion source, it is easy to work with, and it is possible to achieve a high concentration and a thin film. It can be formed thickly.
第１図はこの発明の一実施例である素子分離型複合素子
構造の半導体装置を示す断面図である。FIG. 1 is a sectional view showing a semiconductor device having an element-separated composite element structure, which is an embodiment of the present invention.
同図に示すように、この実施例では、第３図の従来装置
において絶縁ＩＩ！１２の上に所定の膜厚で形成される
ｎ＋ｌＩｌ！１３に代えて、ｎ型不純物を高濃度に含ん
だポリシリコンＪＩ１３０ａと、このポリシリコン層３
０ａを拡散源とした不純物拡散により得られるｎ＋拡散
層３０ｂとを設けている。なお、他の構成は従来と同じ
であるので説明を省略する。As shown in the figure, in this embodiment, insulation II! n+lIl! formed on 12 with a predetermined thickness. 13, polysilicon JI130a containing a high concentration of n-type impurities and this polysilicon layer 3
An n+ diffusion layer 30b obtained by impurity diffusion using Oa as a diffusion source is provided. Note that the other configurations are the same as the conventional one, so explanations will be omitted.
第２図（ａ）〜（ａ）は各々第１図で示した半導体装置
における島の形成方法を示す断面図である。FIGS. 2(a) to 2(a) are cross-sectional views showing a method of forming islands in the semiconductor device shown in FIG. 1, respectively.
以下、同図を参照しつつその形成方法の説明をする。Hereinafter, a method for forming the same will be explained with reference to the same figure.
第２図（ａ）で示すような単結晶のｎ 基板２１表面に
レジスト２２を形成し、同図（ｂ）に示すようにバター
ニングする。そして、バターニングされたレジスト２２
をマスクとして、ｎ−基板２１をエツチングし、同図（
Ｃ）に示すようにＶ字型のくぼみ２３を形成する。各く
ぼみ２３間の距離ｌが各島閤の幅となる。A resist 22 is formed on the surface of a single-crystal n-type substrate 21 as shown in FIG. 2(a), and patterned as shown in FIG. 2(b). Then, the patterned resist 22
Using as a mask, the n-substrate 21 is etched as shown in the figure (
A V-shaped depression 23 is formed as shown in C). The distance l between each depression 23 is the width of each island.
次に、くぼみ２３を含むｎ 基板２１の表面上に高濃度
にｎ型の不純物を含むポリシリコン層３０ａを数十ミク
ロンの膜厚で形成する。その後、連続的に絶縁膜形成炉
に入れ、ポリシリコン層３０ａ上に絶縁膜２を数ミクロ
ンの膜厚で形成する。Next, a polysilicon layer 30a containing n-type impurities at a high concentration is formed on the surface of the n-type substrate 21 including the depression 23 to a thickness of several tens of microns. Thereafter, the insulating film 2 is continuously placed in an insulating film forming furnace to form an insulating film 2 with a thickness of several microns on the polysilicon layer 30a.
このとき、ポリシリコン層３０ａ中の不純物の熱拡散に
より、ポリシリコン層３０ａの周囲のｎ基板２１中に、
同図（ｄ）に示すようにｎ＋拡散層３０ｂが同時に形成
される。At this time, due to thermal diffusion of impurities in the polysilicon layer 30a, into the n-type substrate 21 around the polysilicon layer 30a,
As shown in FIG. 3(d), an n+ diffusion layer 30b is formed at the same time.
そして、絶縁ｌ！Ｉ２上にエピタキシャル成長技術によ
りｎ ポリシリコン層２４を同図（ｅ）に示すように形
成する。次に、ｎ−基板２１の裏面より研磨し、同図（
ｆ）に示すように、絶縁膜２．ポリシリコン層３０及び
ｎ１拡散層３０ｂをｎ−基板２１裏面に露出させる。And insulation! An n-polysilicon layer 24 is formed on I2 by epitaxial growth technique, as shown in FIG. 2(e). Next, the back surface of the n-substrate 21 is polished, and the same figure (
As shown in f), the insulating film 2. The polysilicon layer 30 and the n1 diffusion layer 30b are exposed on the back surface of the n- substrate 21.
その結果、このｎ−基板２１を裏返すと、ｎポリ９９１
７層２４を第１図のｎ ポリシリコン基体１とし、残っ
たｎ−基板２１を第１図のｎＪＩＷ４とし、絶縁ＷＡ２
により各々が絶縁された複数の島２５が完成する。As a result, when this n-board 21 is turned over, n-poly 991
The 7th layer 24 is the n polysilicon substrate 1 in FIG. 1, the remaining n-substrate 21 is the nJIW4 in FIG. 1, and the insulating WA2
As a result, a plurality of islands 25, each insulated, are completed.
このようにして得られた島２５の中に、以下の工程に従
い、電界効果トランジスタ１０Ａ、バイポーラトランジ
スタ１０Ｂが製造される。第５図（ａ）〜（ｄ）は電界
効果トランジスタ１０Ａ及びバイポーラトランジスタＩ
ＯＢの製造方法を示す断面図である。以下、同図を参照
しつつその製造方法の説明をする。まず、弗酸系の薬品
によりｎポリシリコン基体１の前処理を行う。次にｎ
ポリシリコン基体１の表面上に熱酸化法等により酸化１
１３１を形成し、写真製版技術により酸化ｆｆ１３１を
選択的にバターニングして窓３１ａを形成する。そして
、この酸化膜３１の窓３１ａからの不純物拡散により、
島２５ａのｎ−層４上層部ｐつｘ ）Ｌｔ領１ｉｔ！５
を、島２５ｂのｎ−層４上層部にｐベース領域１３を同
図（ａ）に示すようにそれぞれ形成する。In the thus obtained island 25, a field effect transistor 10A and a bipolar transistor 10B are manufactured according to the following steps. FIGS. 5(a) to 5(d) show a field effect transistor 10A and a bipolar transistor I.
FIG. 3 is a cross-sectional view showing a method for manufacturing an OB. The manufacturing method will be explained below with reference to the same figure. First, the n-polysilicon substrate 1 is pretreated with a hydrofluoric acid-based chemical. Then n
Oxidation 1 is applied to the surface of the polysilicon substrate 1 by a thermal oxidation method or the like.
131 is formed, and the oxidized FF131 is selectively patterned by photolithography to form the window 31a. Then, due to impurity diffusion from the window 31a of this oxide film 31,
Island 25a's n-layer 4 upper layer px) Lt area 1it! 5
A p base region 13 is formed in the upper part of the n- layer 4 of the island 25b, as shown in FIG.
次に、島２５ａにおける酸化ｍ３１を除去し、ｎ エピ
タキシャル基体１表面に熱酸化法等により酸化膜３２を
薄く形成し、この酸化ｗＡ３２上にポリシリコン１１３
３を形成する。この酸化膜３２は島２５ｂ上においては
酸化膜３１と合体して若干厚くなる。次に、ポリシリコ
ン層３３及び酸化１１１１３２を選択的にエツチングし
て窓３３ａを形成する。そして、同図（ｂ）に示すよう
に、ポリシリコン層３３の窓３３ａからｎ型の不純物を
拡散し、ｐウェル領域５及びｐベース領域１３の上層部
にｎ＋ソース領域６及びｎ 工くツタ領域１４を形成す
る。なお、電界効果トランジスタ１０Ａが２重拡散タイ
プであれば、ｎ＋ソース領域６形成前にｐ型の不純物を
窓３３ａから拡散する。Next, the oxide m31 on the island 25a is removed, and a thin oxide film 32 is formed on the surface of the n epitaxial substrate 1 by a thermal oxidation method, etc., and the polysilicon 113 is formed on this oxidized wA32.
form 3. This oxide film 32 is combined with the oxide film 31 on the island 25b and becomes slightly thicker. Next, polysilicon layer 33 and oxide 111132 are selectively etched to form window 33a. Then, as shown in FIG. 3B, n-type impurities are diffused through the window 33a of the polysilicon layer 33, and an n+ source region 6 and an n-type impurity are formed in the upper layer of the p-well region 5 and the p-base region 13. A region 14 is formed. Note that if the field effect transistor 10A is a double diffusion type, p-type impurities are diffused through the window 33a before forming the n+ source region 6.
その慢、ポリシリコン層３３を選択的にエツチングして
、同図（Ｃ）に示すように、島２５ａにポリシリコンゲ
ート８を形成する。次に、ｎ−エピタキシャル基体１全
而に酸化膜を形成し、この酸化膜を選択的にエツチング
し、同図（ｄ）に示すように、島２５ａａよび２５ｂに
パッシベーション膜１８を形成する。After that, the polysilicon layer 33 is selectively etched to form a polysilicon gate 8 on the island 25a, as shown in FIG. Next, an oxide film is formed over the entire n-epitaxial substrate 1, and this oxide film is selectively etched to form a passivation film 18 on the islands 25aa and 25b, as shown in FIG.
その後、パッシベーション膜１８を含むｎ エピタキシ
ャル基体１上に導電層を形成し、この導電層を選択的に
エツチングすることで、第１図に示すように島２５ａに
ドレイン電極９．ソース電極１１．ゲート電極１２が形
成され、島２５ｂにエミッタ電極１５．ベース電極１６
及びコレクタ電極１７が形成される。このようにして、
島２５ａに電界効果トランジスタ１０Ａが、島２５ｂに
バイポーラトランジスタ１０Ｂが形成される。Thereafter, a conductive layer is formed on the n-type epitaxial substrate 1 including the passivation film 18, and this conductive layer is selectively etched to form the drain electrode 9 on the island 25a as shown in FIG. Source electrode 11. A gate electrode 12 is formed, and an emitter electrode 15. is formed on the island 25b. Base electrode 16
and a collector electrode 17 is formed. In this way,
A field effect transistor 10A is formed on the island 25a, and a bipolar transistor 10B is formed on the island 25b.
上記実施例においては、島２５中の電極領域となるｎ＋
領領域高濃度にｎ型不純物がドープされたポリシリコン
層３０ａと、このポリシリコン層３０ａ中の不純物の拡
散により得られたｎ 拡散１ｔ１３０ｂとにより形成し
ている。ポリシリコン層３０ａは、１０ 〜１０２２ｍ
＋−３程度まで容易かつ正確に不純物濃度を高くするこ
とができる。また、２０μｍの膜厚のｎ＋層を形成する
には、従来の不純物拡散法では４時間程度要していたも
のが、ポリシリコン１１３０ａではわずか２０分程度で
形成できるため、短時間で膜厚を厚くすることができる
。したがって、所望の膜厚で高濃度なｎ＋層が島２５中
に作業性良く形成できる。In the above embodiment, n+ which becomes the electrode region in the island 25
The region is formed by a polysilicon layer 30a doped with n-type impurities at a high concentration, and an n-diffusion it130b obtained by diffusion of the impurity in this polysilicon layer 30a. The polysilicon layer 30a has a thickness of 10 to 1022 m.
The impurity concentration can be easily and accurately increased to about +-3. In addition, to form an n+ layer with a thickness of 20 μm, which used to take about 4 hours using conventional impurity diffusion methods, it can be formed in only about 20 minutes using polysilicon 1130a, so the film thickness can be increased in a short time. It can be made thicker. Therefore, a highly concentrated n+ layer with a desired thickness can be formed in the island 25 with good workability.
その結果、この島２５中に電界効果トランジスタ１０Ａ
を製造する場合は、ポリシリコン層３０ａ及び拡散１ｉ
１３０ｂをドレイン電極９とオーミック接続することで
、オン抵抗値、ドレイン−ソース間の順方向電圧を極力
小さくでき、島２５中に接合型トランジスタ１０Ｂを製
造する場合は、ポリシリコン層３０ａ及び拡散Ｊｉ１３
０ｂをコレクタ電極１７とオーミック接続することで、
コレクターエミッタ間飽和電圧を極力小さくできる。As a result, in this island 25 there is a field effect transistor 10A.
When manufacturing polysilicon layer 30a and diffusion 1i
130b is ohmically connected to the drain electrode 9, the on-resistance value and forward voltage between the drain and source can be minimized. When manufacturing the junction transistor 10B in the island 25, the polysilicon layer 30a and the diffusion
By ohmic connecting 0b with the collector electrode 17,
Collector-emitter saturation voltage can be minimized.
また、ｎ＋拡散層３０ｂは、絶縁１［１２の形成時に同
時に形成されるため、従来に比べ製造工程数が増えるこ
ともない。Furthermore, since the n+ diffusion layer 30b is formed at the same time as the insulation 1[12 is formed, the number of manufacturing steps is not increased compared to the conventional method.
なお、上記実施例では、素子分離型複合素子の半導体装
置を例に挙げたが、この発明は、半導体素子の能動領域
中に所望の膜厚で高濃度な電極領域を必要とするすべて
の半導体装置に適用することができる。In the above embodiments, a semiconductor device of an element isolation type composite element was taken as an example, but the present invention is applicable to all semiconductor devices that require a high concentration electrode region with a desired film thickness in the active region of a semiconductor element. It can be applied to the device.
以上説明したように、この発明によれば、電極領域を、
能動領域内に形成された所定の導電型の不純物を高濃度
に含む多結晶半導体層と、この多結晶半動体層を拡散源
とした拡散により形成可能な拡散層とから構成するため
、所望の膜厚で１Ｍｍ度な電極領域を有することができ
る効果がある。As explained above, according to the present invention, the electrode region is
It consists of a polycrystalline semiconductor layer containing a high concentration of impurities of a predetermined conductivity type formed in the active region and a diffusion layer that can be formed by diffusion using this polycrystalline semi-active layer as a diffusion source. This has the advantage of having an electrode area with a film thickness of about 1 mm.
第１図はこの発明の一実施例である素子分離型複合素子
構造の半導体装置を示す断面図、第２図は第１図で示し
た半導体装置の製造方法を示す断面図、第３図は従来の
素子分離型複合素子構造の半導体装置を示す断面図、第
４図は第３図で示した半導体装置の製造方法を示す断面
図、第５図は電界効果トランジスタ及びバイポーラトラ
ンジスタの製造方法を示す断面図である。
図において、１はｎ”ポリシリコン基体、２は絶縁膜、
３０ａはポリシリコン層、３０ｂはｎ＋拡散層、４はｎ
−層、２１はｎ″基板、２４はｎ−ポリシリコン層であ
る。
なお、各図中同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄
第２図（ぞの１）
２４・・・ｎ−ポリシリコン層
第
図（その２）
第
図
第４図（イの１）
第
図（その２）FIG. 1 is a cross-sectional view showing a semiconductor device with an element-separated composite element structure as an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1, and FIG. 4 is a cross-sectional view showing a conventional semiconductor device with an element-separated composite element structure, FIG. 4 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 3, and FIG. 5 is a cross-sectional view showing a method for manufacturing a field effect transistor and a bipolar transistor. FIG. In the figure, 1 is an n'' polysilicon base, 2 is an insulating film,
30a is a polysilicon layer, 30b is an n+ diffusion layer, 4 is an n
- layer, 21 is an n'' substrate, and 24 is an n-polysilicon layer. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa Figure 2 (Zone 1) 24.・・n-polysilicon layer Figure (Part 2) Figure 4 (A-1) Figure (Part 2)
Claims (2)
域と、 前記能動領域内に形成された、所定の導電型の不純物を
高濃度に含む多結晶半導体層および該多結晶半導体層の
周囲に形成された前記所定の導電型の拡散層より成る電
極領域とを備える半導体装置。(1) a semiconductor substrate, at least one active region formed on the semiconductor substrate, a polycrystalline semiconductor layer formed in the active region and containing a high concentration of impurities of a predetermined conductivity type, and the polycrystalline semiconductor layer. and an electrode region made of a diffusion layer of the predetermined conductivity type formed around a semiconductor layer.
動領域内に所定の導電型の不純物を高濃度に含む多結晶
半導体層を形成する工程と、前記多結晶半導体層を拡散
源として前記所定の導電型の不純物を拡散し、前記多結
晶半導体層の周囲に拡散層を形成する工程とを備え、前
記拡散層は前記多結晶半導体層とともに電極領域を形成
している半導体装置の製造方法。(2) a step of preparing a semiconductor substrate; a step of forming an active region on the semiconductor substrate; and a step of forming a polycrystalline semiconductor layer containing a high concentration of impurities of a predetermined conductivity type in the active region; diffusing the impurity of the predetermined conductivity type using the polycrystalline semiconductor layer as a diffusion source to form a diffusion layer around the polycrystalline semiconductor layer, the diffusion layer forming an electrode region together with the polycrystalline semiconductor layer. A method for manufacturing a semiconductor device forming a
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1021684A JP2757872B2 (en) | 1989-01-31 | 1989-01-31 | Semiconductor device and manufacturing method thereof |
| DE19904002673 DE4002673C2 (en) | 1989-01-31 | 1990-01-30 | Method of manufacturing a semiconductor device |
| US07/652,221 US5246877A (en) | 1989-01-31 | 1991-02-06 | Method of manufacturing a semiconductor device having a polycrystalline electrode region |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1021684A JP2757872B2 (en) | 1989-01-31 | 1989-01-31 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02202032A true JPH02202032A (en) | 1990-08-10 |
| JP2757872B2 JP2757872B2 (en) | 1998-05-25 |
Family
ID=12061894
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1021684A Expired - Lifetime JP2757872B2 (en) | 1989-01-31 | 1989-01-31 | Semiconductor device and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2757872B2 (en) |
| DE (1) | DE4002673C2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2567472B2 (en) * | 1989-05-24 | 1996-12-25 | 日産自動車株式会社 | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63124576A (en) * | 1986-11-14 | 1988-05-28 | Nec Corp | Field effect transistor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3722079A (en) * | 1970-06-05 | 1973-03-27 | Radiation Inc | Process for forming buried layers to reduce collector resistance in top contact transistors |
| JPS60186036A (en) * | 1984-03-05 | 1985-09-21 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor substrate and manufacture thereof |
-
1989
- 1989-01-31 JP JP1021684A patent/JP2757872B2/en not_active Expired - Lifetime
-
1990
- 1990-01-30 DE DE19904002673 patent/DE4002673C2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63124576A (en) * | 1986-11-14 | 1988-05-28 | Nec Corp | Field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2757872B2 (en) | 1998-05-25 |
| DE4002673C2 (en) | 1998-01-22 |
| DE4002673A1 (en) | 1990-08-02 |
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